NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST	100.0 % (83/83)	100.0 % (70/70)	100.0 % (508/508)	100.0 % (114/114)	N.A.	N.A.	100.0 % (775/775)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

215:        if (res_n = '0') then 
216:            mr_ctr_pres_ptx_q   <= '0'; 
...
224:            mr_ctr_pres_efd_q   <= mr_ctr_pres_efd; 
225:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

216: mr_ctr_pres_ptx_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

217: mr_ctr_pres_prx_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

218: mr_ctr_pres_enorm_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

219: mr_ctr_pres_efd_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

221: mr_ctr_pres_ptx_q <= mr_ctr_pres_ptx;
Count: 526374300
Threshold: 1

Signal assignment statement:

222: mr_ctr_pres_prx_q <= mr_ctr_pres_prx;
Count: 526374300
Threshold: 1

Signal assignment statement:

223: mr_ctr_pres_enorm_q <= mr_ctr_pres_enorm;
Count: 526374300
Threshold: 1

Signal assignment statement:

224: mr_ctr_pres_efd_q <= mr_ctr_pres_efd;
Count: 526374300
Threshold: 1

If statement:

228:    modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else 
229:                    '0';

Count: 214100
Threshold: 1

Signal assignment statement:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else
Count: 105450
Threshold: 1

Signal assignment statement:

229: '0';
Count: 108650
Threshold: 1

If statement:

232:    modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1') 
233:                        else 
234:                    '0';

Count: 303824
Threshold: 1

Signal assignment statement:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')
Count: 150328
Threshold: 1

Signal assignment statement:

234: '0';
Count: 153496
Threshold: 1

If statement:

239:    tx_err_ctr_dec <=  (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else 
240:                       tx_err_ctr_q;

Count: 32526
Threshold: 1

Signal assignment statement:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else
Count: 19096
Threshold: 1

Signal assignment statement:

240: tx_err_ctr_q;
Count: 13430
Threshold: 1

If statement:

244:    tx_err_ctr_d <= 
245:              unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else 
246:                        tx_err_ctr_q + 8 when (inc_eight = '1') else 
247:                          tx_err_ctr_dec;

Count: 260319
Threshold: 1

Signal assignment statement:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else
Count: 19928
Threshold: 1

Signal assignment statement:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else
Count: 107312
Threshold: 1

Signal assignment statement:

247: tx_err_ctr_dec;
Count: 133079
Threshold: 1

If statement:

251:    tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else 
252:                     '1' when (mr_ctr_pres_ptx_q = '1') else 
253:                     '0';

Count: 292880
Threshold: 1

Signal assignment statement:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else
Count: 82085
Threshold: 1

Signal assignment statement:

252: '1' when (mr_ctr_pres_ptx_q = '1') else
Count: 18698
Threshold: 1

Signal assignment statement:

253: '0';
Count: 192097
Threshold: 1

If statement:

258:    res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1') 
259:                          else 
260:                      '1';

Count: 32626
Threshold: 1

Signal assignment statement:

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')
Count: 14708
Threshold: 1

Signal assignment statement:

260: '1';
Count: 17918
Threshold: 1

If statement:

284:        if (res_err_ctrs_q_scan = '0') then 
285:            tx_err_ctr_q <= (others => '0'); 
...
289:            end if; 
290:        end if;

Count: 1055190354
Threshold: 1

Signal assignment statement:

285: tx_err_ctr_q <= (others => '0');
Count: 2451371
Threshold: 1

If statement:

287:            if (tx_err_ctr_ce = '1') then 
288:                tx_err_ctr_q <= tx_err_ctr_d; 
289:            end if;

Count: 526361182
Threshold: 1

Signal assignment statement:

288: tx_err_ctr_q <= tx_err_ctr_d;
Count: 43767
Threshold: 1

If statement:

297:    rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else 
298:                       (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else 
299:                            rx_err_ctr_q;

Count: 27245
Threshold: 1

Signal assignment statement:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else
Count: 8773
Threshold: 1

Signal assignment statement:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else
Count: 8981
Threshold: 1

Signal assignment statement:

299: rx_err_ctr_q;
Count: 9491
Threshold: 1

If statement:

303:    rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else 
304:                      rx_err_ctr_q + 8;

Count: 118601
Threshold: 1

Signal assignment statement:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else
Count: 56997
Threshold: 1

Signal assignment statement:

304: rx_err_ctr_q + 8;
Count: 61604
Threshold: 1

If statement:

307:    rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else 
308:                      rx_err_ctr_inc;

Count: 144246
Threshold: 1

Signal assignment statement:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else
Count: 697
Threshold: 1

Signal assignment statement:

308: rx_err_ctr_inc;
Count: 143549
Threshold: 1

If statement:

314:    rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else 
315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else 
316:                                rx_err_ctr_dec;

Count: 420748
Threshold: 1

Signal assignment statement:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else
Count: 21703
Threshold: 1

Signal assignment statement:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

Count: 151430
Threshold: 1

Signal assignment statement:

316: rx_err_ctr_dec;
Count: 247615
Threshold: 1

If statement:

320:    rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else 
321:                     '1' when (mr_ctr_pres_prx_q = '1') else 
322:                     '0';

Count: 405332
Threshold: 1

Signal assignment statement:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else
Count: 68157
Threshold: 1

Signal assignment statement:

321: '1' when (mr_ctr_pres_prx_q = '1') else
Count: 19085
Threshold: 1

Signal assignment statement:

322: '0';
Count: 318090
Threshold: 1

If statement:

329:        if (res_err_ctrs_q_scan = '0') then 
330:            rx_err_ctr_q <= (others => '0'); 
...
334:            end if; 
335:        end if;

Count: 1055190354
Threshold: 1

Signal assignment statement:

330: rx_err_ctr_q <= (others => '0');
Count: 2451371
Threshold: 1

If statement:

332:            if (rx_err_ctr_ce = '1') then 
333:                rx_err_ctr_q <= rx_err_ctr_d; 
334:            end if;

Count: 526361182
Threshold: 1

Signal assignment statement:

333: rx_err_ctr_q <= rx_err_ctr_d;
Count: 46648
Threshold: 1

If statement:

346:    nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else 
347:                       data_err_ctr_q;

Count: 95934
Threshold: 1

Signal assignment statement:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else
Count: 54294
Threshold: 1

Signal assignment statement:

347: data_err_ctr_q;
Count: 41640
Threshold: 1

Signal assignment statement:

349: nom_dat_sel_ctr_add <= nom_dat_sel_ctr + 1;
Count: 63423
Threshold: 1

If statement:

351:    nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0') 
352:                                         else 
353:                         (others => '0');

Count: 78507
Threshold: 1

Signal assignment statement:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')
Count: 69365
Threshold: 1

Signal assignment statement:

353: (others => '0');
Count: 9142
Threshold: 1

If statement:

355:    data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0') 
356:                                          else 
357:                         (others => '0');

Count: 78507
Threshold: 1

Signal assignment statement:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')
Count: 65096
Threshold: 1

Signal assignment statement:

357: (others => '0');
Count: 13411
Threshold: 1

If statement:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE)) 
363:                          else 
364:                      '0';

Count: 323883
Threshold: 1

Signal assignment statement:

360: nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or
Count: 126503
Threshold: 1

Signal assignment statement:

364: '0';
Count: 197380
Threshold: 1

If statement:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
369:                           else 
370:                       '0';

Count: 323883
Threshold: 1

Signal assignment statement:

366: data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or
Count: 19940
Threshold: 1

Signal assignment statement:

370: '0';
Count: 303943
Threshold: 1

If statement:

377:        if (res_err_ctrs_q_scan = '0') then 
378:            nom_err_ctr_q <= (others => '0'); 
...
382:            end if; 
383:        end if;

Count: 1055190354
Threshold: 1

Signal assignment statement:

378: nom_err_ctr_q <= (others => '0');
Count: 2451371
Threshold: 1

If statement:

380:            if (nom_err_ctr_ce = '1') then 
381:                nom_err_ctr_q <= nom_err_ctr_d; 
382:            end if;

Count: 526361182
Threshold: 1

Signal assignment statement:

381: nom_err_ctr_q <= nom_err_ctr_d;
Count: 22244
Threshold: 1

If statement:

388:        if (res_err_ctrs_q_scan = '0') then 
389:            data_err_ctr_q <= (others => '0'); 
...
393:            end if; 
394:        end if;

Count: 1055190354
Threshold: 1

Signal assignment statement:

389: data_err_ctr_q <= (others => '0');
Count: 2451371
Threshold: 1

If statement:

391:            if (data_err_ctr_ce = '1') then 
392:                data_err_ctr_q <= data_err_ctr_d; 
393:            end if;

Count: 526361182
Threshold: 1

Signal assignment statement:

392: data_err_ctr_q <= data_err_ctr_d;
Count: 16228
Threshold: 1

Signal assignment statement:

400: rx_err_ctr <= std_logic_vector(rx_err_ctr_q);
Count: 27245
Threshold: 1

Signal assignment statement:

401: tx_err_ctr <= std_logic_vector(tx_err_ctr_q);
Count: 32526
Threshold: 1

Signal assignment statement:

403: norm_err_ctr <= std_logic_vector(nom_err_ctr_q);
Count: 26506
Threshold: 1

Signal assignment statement:

404: data_err_ctr <= std_logic_vector(data_err_ctr_q);
Count: 14355
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

215: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

220: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	105450	1
Bin	False	108650	1

"if" / "when" / "else" condition:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	True	150328	1
Bin	False	153496	1

"if" / "when" / "else" condition:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	19096	1
Bin	False	13430	1

"if" / "when" / "else" condition:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19928	1
Bin	False	240391	1

"if" / "when" / "else" condition:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	107312	1
Bin	False	133079	1

"if" / "when" / "else" condition:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else

	Evaluated to	Count	Threshold
Bin	True	82085	1
Bin	False	210795	1

"if" / "when" / "else" condition:

252: '1' when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	18698	1
Bin	False	192097	1

"if" / "when" / "else" condition:

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')

	Evaluated to	Count	Threshold
Bin	True	14708	1
Bin	False	17918	1

"if" / "when" / "else" condition:

284: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2451371	1
Bin	False	1052738983	1

"if" / "when" / "else" condition:

286: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526361182	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

287: if (tx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	43767	1
Bin	False	526317415	1

"if" / "when" / "else" condition:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else

	Evaluated to	Count	Threshold
Bin	True	8773	1
Bin	False	18472	1

"if" / "when" / "else" condition:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	8981	1
Bin	False	9491	1

"if" / "when" / "else" condition:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	56997	1
Bin	False	61604	1

"if" / "when" / "else" condition:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else

	Evaluated to	Count	Threshold
Bin	True	697	1
Bin	False	143549	1

"if" / "when" / "else" condition:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	21703	1
Bin	False	399045	1

"if" / "when" / "else" condition:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	151430	1
Bin	False	247615	1

"if" / "when" / "else" condition:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	True	68157	1
Bin	False	337175	1

"if" / "when" / "else" condition:

321: '1' when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19085	1
Bin	False	318090	1

"if" / "when" / "else" condition:

329: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2451371	1
Bin	False	1052738983	1

"if" / "when" / "else" condition:

331: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526361182	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

332: if (rx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	46648	1
Bin	False	526314534	1

"if" / "when" / "else" condition:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	54294	1
Bin	False	41640	1

"if" / "when" / "else" condition:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')

	Evaluated to	Count	Threshold
Bin	True	69365	1
Bin	False	9142	1

"if" / "when" / "else" condition:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')

	Evaluated to	Count	Threshold
Bin	True	65096	1
Bin	False	13411	1

"if" / "when" / "else" condition:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	126503	1
Bin	False	197380	1

"if" / "when" / "else" condition:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	19940	1
Bin	False	303943	1

"if" / "when" / "else" condition:

377: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2451371	1
Bin	False	1052738983	1

"if" / "when" / "else" condition:

379: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526361182	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

380: if (nom_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	22244	1
Bin	False	526338938	1

"if" / "when" / "else" condition:

388: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2451371	1
Bin	False	1052738983	1

"if" / "when" / "else" condition:

390: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526361182	1
Bin	False	526377801	1

"if" / "when" / "else" condition:

391: if (data_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	16228	1
Bin	False	526344954	1

Uncovered toggles:

Excluded toggles:

Signal:

RX_ERR_CTR_DEC(8)

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file

Signal:

RX_ERR_CTR_DEC(7)

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SCAN_ENABLE

	From	To	Count	Threshold
Bin	0	1	5	1
Bin	1	0	1605	1

Port:

SP_CONTROL(1)

	From	To	Count	Threshold
Bin	0	1	4206	1
Bin	1	0	5806	1

Port:

SP_CONTROL(0)

	From	To	Count	Threshold
Bin	0	1	25548	1
Bin	1	0	27148	1

Port:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	44878	1
Bin	1	0	46478	1

Port:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	79370	1
Bin	1	0	80970	1

Port:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26080	1
Bin	1	0	27680	1

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6636	1
Bin	1	0	8236	1

Port:

IS_TRANSMITTER

	From	To	Count	Threshold
Bin	0	1	19892	1
Bin	1	0	21492	1

Port:

IS_RECEIVER

	From	To	Count	Threshold
Bin	0	1	30888	1
Bin	1	0	32482	1

Port:

MR_CTR_PRES_CTPV(8)

	From	To	Count	Threshold
Bin	0	1	264	1
Bin	1	0	1864	1

Port:

MR_CTR_PRES_CTPV(7)

	From	To	Count	Threshold
Bin	0	1	2166	1
Bin	1	0	3766	1

Port:

MR_CTR_PRES_CTPV(6)

	From	To	Count	Threshold
Bin	0	1	683	1
Bin	1	0	2283	1

Port:

MR_CTR_PRES_CTPV(5)

	From	To	Count	Threshold
Bin	0	1	2181	1
Bin	1	0	3781	1

Port:

MR_CTR_PRES_CTPV(4)

	From	To	Count	Threshold
Bin	0	1	2332	1
Bin	1	0	3932	1

Port:

MR_CTR_PRES_CTPV(3)

	From	To	Count	Threshold
Bin	0	1	919	1
Bin	1	0	2519	1

Port:

MR_CTR_PRES_CTPV(2)

	From	To	Count	Threshold
Bin	0	1	2414	1
Bin	1	0	4014	1

Port:

MR_CTR_PRES_CTPV(1)

	From	To	Count	Threshold
Bin	0	1	1008	1
Bin	1	0	2608	1

Port:

MR_CTR_PRES_CTPV(0)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold
Bin	0	1	18698	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold
Bin	0	1	19085	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	42871	1

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	42871	1

Port:

RX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	1736	1

Port:

RX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	1960	1

Port:

RX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1864	1

Port:

RX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	1931	1

Port:

RX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Port:

RX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2285	1

Port:

RX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	627	1
Bin	1	0	2227	1

Port:

RX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	1208	1
Bin	1	0	2808	1

Port:

RX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	11221	1
Bin	1	0	12815	1

Port:

TX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Port:

TX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	2121	1

Port:

TX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	2088	1

Port:

TX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2411	1

Port:

TX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	1931	1
Bin	1	0	3531	1

Port:

TX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	12094	1
Bin	1	0	13694	1

Port:

TX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	2980	1
Bin	1	0	4580	1

Port:

TX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	3318	1
Bin	1	0	4918	1

Port:

TX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	3517	1
Bin	1	0	5117	1

Port:

NORM_ERR_CTR(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1662	1

Port:

NORM_ERR_CTR(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1668	1

Port:

NORM_ERR_CTR(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1663	1

Port:

NORM_ERR_CTR(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1657	1

Port:

NORM_ERR_CTR(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1655	1

Port:

NORM_ERR_CTR(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Port:

NORM_ERR_CTR(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1665	1

Port:

NORM_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1670	1

Port:

NORM_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1676	1

Port:

NORM_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1698	1

Port:

NORM_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	1759	1

Port:

NORM_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	1878	1

Port:

NORM_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	2194	1

Port:

NORM_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	1361	1
Bin	1	0	2956	1

Port:

NORM_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	3048	1
Bin	1	0	4645	1

Port:

NORM_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	11189	1
Bin	1	0	12783	1

Port:

DATA_ERR_CTR(15)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1670	1

Port:

DATA_ERR_CTR(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1660	1

Port:

DATA_ERR_CTR(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Port:

DATA_ERR_CTR(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1662	1

Port:

DATA_ERR_CTR(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1657	1

Port:

DATA_ERR_CTR(10)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1656	1

Port:

DATA_ERR_CTR(9)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1670	1

Port:

DATA_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1683	1

Port:

DATA_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1701	1

Port:

DATA_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	1735	1

Port:

DATA_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1802	1

Port:

DATA_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	359	1
Bin	1	0	1956	1

Port:

DATA_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	679	1
Bin	1	0	2274	1

Port:

DATA_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	1295	1
Bin	1	0	2892	1

Port:

DATA_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	2524	1
Bin	1	0	4120	1

Port:

DATA_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	5478	1
Bin	1	0	7073	1

Signal:

TX_ERR_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	662	1
Bin	1	0	2262	1

Signal:

TX_ERR_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	3115	1
Bin	1	0	4715	1

Signal:

TX_ERR_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	4141	1
Bin	1	0	5741	1

Signal:

TX_ERR_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	8247	1
Bin	1	0	9847	1

Signal:

TX_ERR_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	32827	1
Bin	1	0	34427	1

Signal:

TX_ERR_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	67820	1
Bin	1	0	69420	1

Signal:

TX_ERR_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	35121	1
Bin	1	0	36721	1

Signal:

TX_ERR_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	46855	1
Bin	1	0	48455	1

Signal:

TX_ERR_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	51500	1
Bin	1	0	53100	1

Signal:

RX_ERR_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	304	1
Bin	1	0	1904	1

Signal:

RX_ERR_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	22307	1
Bin	1	0	23907	1

Signal:

RX_ERR_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	23070	1
Bin	1	0	24668	1

Signal:

RX_ERR_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	20407	1
Bin	1	0	22006	1

Signal:

RX_ERR_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	6630	1
Bin	1	0	8230	1

Signal:

RX_ERR_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	127974	1
Bin	1	0	129573	1

Signal:

RX_ERR_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	24069	1
Bin	1	0	25669	1

Signal:

RX_ERR_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	28147	1
Bin	1	0	29747	1

Signal:

RX_ERR_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	25856	1
Bin	1	0	27456	1

Signal:

TX_ERR_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Signal:

TX_ERR_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	2121	1

Signal:

TX_ERR_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	2088	1

Signal:

TX_ERR_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2411	1

Signal:

TX_ERR_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	1931	1
Bin	1	0	3531	1

Signal:

TX_ERR_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	12094	1
Bin	1	0	13694	1

Signal:

TX_ERR_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	2980	1
Bin	1	0	4580	1

Signal:

TX_ERR_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	3318	1
Bin	1	0	4918	1

Signal:

TX_ERR_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	3517	1
Bin	1	0	5117	1

Signal:

RX_ERR_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	1736	1

Signal:

RX_ERR_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	1960	1

Signal:

RX_ERR_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1864	1

Signal:

RX_ERR_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	1931	1

Signal:

RX_ERR_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Signal:

RX_ERR_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2285	1

Signal:

RX_ERR_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	627	1
Bin	1	0	2227	1

Signal:

RX_ERR_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	1208	1
Bin	1	0	2808	1

Signal:

RX_ERR_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	11221	1
Bin	1	0	12815	1

Signal:

RX_ERR_CTR_INC(8)

	From	To	Count	Threshold
Bin	0	1	140	1
Bin	1	0	1740	1

Signal:

RX_ERR_CTR_INC(7)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	2068	1

Signal:

RX_ERR_CTR_INC(6)

	From	To	Count	Threshold
Bin	0	1	454	1
Bin	1	0	2052	1

Signal:

RX_ERR_CTR_INC(5)

	From	To	Count	Threshold
Bin	0	1	822	1
Bin	1	0	2421	1

Signal:

RX_ERR_CTR_INC(4)

	From	To	Count	Threshold
Bin	0	1	2028	1
Bin	1	0	3627	1

Signal:

RX_ERR_CTR_INC(3)

	From	To	Count	Threshold
Bin	0	1	46848	1
Bin	1	0	45249	1

Signal:

RX_ERR_CTR_INC(2)

	From	To	Count	Threshold
Bin	0	1	5445	1
Bin	1	0	7045	1

Signal:

RX_ERR_CTR_INC(1)

	From	To	Count	Threshold
Bin	0	1	13032	1
Bin	1	0	14632	1

Signal:

RX_ERR_CTR_INC(0)

	From	To	Count	Threshold
Bin	0	1	56099	1
Bin	1	0	57693	1

Signal:

RX_ERR_CTR_SAT(8)

	From	To	Count	Threshold
Bin	0	1	650	1
Bin	1	0	2250	1

Signal:

RX_ERR_CTR_SAT(7)

	From	To	Count	Threshold
Bin	0	1	759	1
Bin	1	0	2359	1

Signal:

RX_ERR_CTR_SAT(6)

	From	To	Count	Threshold
Bin	0	1	843	1
Bin	1	0	2441	1

Signal:

RX_ERR_CTR_SAT(5)

	From	To	Count	Threshold
Bin	0	1	1158	1
Bin	1	0	2757	1

Signal:

RX_ERR_CTR_SAT(4)

	From	To	Count	Threshold
Bin	0	1	2211	1
Bin	1	0	3810	1

Signal:

RX_ERR_CTR_SAT(3)

	From	To	Count	Threshold
Bin	0	1	46890	1
Bin	1	0	45291	1

Signal:

RX_ERR_CTR_SAT(2)

	From	To	Count	Threshold
Bin	0	1	5639	1
Bin	1	0	7239	1

Signal:

RX_ERR_CTR_SAT(1)

	From	To	Count	Threshold
Bin	0	1	13240	1
Bin	1	0	14840	1

Signal:

RX_ERR_CTR_SAT(0)

	From	To	Count	Threshold
Bin	0	1	56422	1
Bin	1	0	58016	1

Signal:

TX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	100783	1
Bin	1	0	102383	1

Signal:

RX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	87242	1
Bin	1	0	88842	1

Signal:

MODIF_TX_CTR

	From	To	Count	Threshold
Bin	0	1	105450	1
Bin	1	0	107050	1

Signal:

MODIF_RX_CTR

	From	To	Count	Threshold
Bin	0	1	150296	1
Bin	1	0	151896	1

Signal:

TX_ERR_CTR_DEC(8)

	From	To	Count	Threshold
Bin	0	1	230	1
Bin	1	0	1830	1

Signal:

TX_ERR_CTR_DEC(7)

	From	To	Count	Threshold
Bin	0	1	497	1
Bin	1	0	2097	1

Signal:

TX_ERR_CTR_DEC(6)

	From	To	Count	Threshold
Bin	0	1	487	1
Bin	1	0	2087	1

Signal:

TX_ERR_CTR_DEC(5)

	From	To	Count	Threshold
Bin	0	1	754	1
Bin	1	0	2354	1

Signal:

TX_ERR_CTR_DEC(4)

	From	To	Count	Threshold
Bin	0	1	1567	1
Bin	1	0	3167	1

Signal:

TX_ERR_CTR_DEC(3)

	From	To	Count	Threshold
Bin	0	1	2908	1
Bin	1	0	4508	1

Signal:

TX_ERR_CTR_DEC(2)

	From	To	Count	Threshold
Bin	0	1	10220	1
Bin	1	0	11820	1

Signal:

TX_ERR_CTR_DEC(1)

	From	To	Count	Threshold
Bin	0	1	10254	1
Bin	1	0	11854	1

Signal:

TX_ERR_CTR_DEC(0)

	From	To	Count	Threshold
Bin	0	1	11129	1
Bin	1	0	12729	1

Signal:

RX_ERR_CTR_DEC(8)

	From	To	Count	Threshold
Bin	1	0	1600	1

Signal:

RX_ERR_CTR_DEC(7)

	From	To	Count	Threshold
Bin	1	0	1600	1

Signal:

RX_ERR_CTR_DEC(6)

	From	To	Count	Threshold
Bin	0	1	440	1
Bin	1	0	2038	1

Signal:

RX_ERR_CTR_DEC(5)

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	2067	1

Signal:

RX_ERR_CTR_DEC(4)

	From	To	Count	Threshold
Bin	0	1	599	1
Bin	1	0	2199	1

Signal:

RX_ERR_CTR_DEC(3)

	From	To	Count	Threshold
Bin	0	1	853	1
Bin	1	0	2452	1

Signal:

RX_ERR_CTR_DEC(2)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Signal:

RX_ERR_CTR_DEC(1)

	From	To	Count	Threshold
Bin	0	1	742	1
Bin	1	0	2342	1

Signal:

RX_ERR_CTR_DEC(0)

	From	To	Count	Threshold
Bin	0	1	1579	1
Bin	1	0	3179	1

Signal:

NOM_ERR_CTR_D(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	3262	1

Signal:

NOM_ERR_CTR_D(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3268	1

Signal:

NOM_ERR_CTR_D(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3263	1

Signal:

NOM_ERR_CTR_D(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	3257	1

Signal:

NOM_ERR_CTR_D(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	3255	1

Signal:

NOM_ERR_CTR_D(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3261	1

Signal:

NOM_ERR_CTR_D(9)

	From	To	Count	Threshold
Bin	0	1	4549	1
Bin	1	0	7746	1

Signal:

NOM_ERR_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	4564	1
Bin	1	0	7761	1

Signal:

NOM_ERR_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	4628	1
Bin	1	0	7825	1

Signal:

NOM_ERR_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	4946	1
Bin	1	0	8143	1

Signal:

NOM_ERR_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	5408	1
Bin	1	0	8606	1

Signal:

NOM_ERR_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	6028	1
Bin	1	0	9225	1

Signal:

NOM_ERR_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	7166	1
Bin	1	0	10361	1

Signal:

NOM_ERR_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	9264	1
Bin	1	0	12459	1

Signal:

NOM_ERR_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	22534	1
Bin	1	0	25729	1

Signal:

NOM_ERR_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	26905	1
Bin	1	0	26911	1

Signal:

DATA_ERR_CTR_D(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	3262	1

Signal:

DATA_ERR_CTR_D(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	3268	1

Signal:

DATA_ERR_CTR_D(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	3263	1

Signal:

DATA_ERR_CTR_D(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	3257	1

Signal:

DATA_ERR_CTR_D(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	3255	1

Signal:

DATA_ERR_CTR_D(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	3261	1

Signal:

DATA_ERR_CTR_D(9)

	From	To	Count	Threshold
Bin	0	1	4549	1
Bin	1	0	7746	1

Signal:

DATA_ERR_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	4564	1
Bin	1	0	7761	1

Signal:

DATA_ERR_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	4628	1
Bin	1	0	7825	1

Signal:

DATA_ERR_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	4946	1
Bin	1	0	8143	1

Signal:

DATA_ERR_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	5408	1
Bin	1	0	8606	1

Signal:

DATA_ERR_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	6005	1
Bin	1	0	9202	1

Signal:

DATA_ERR_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	7146	1
Bin	1	0	10341	1

Signal:

DATA_ERR_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	9016	1
Bin	1	0	12211	1

Signal:

DATA_ERR_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	18535	1
Bin	1	0	21730	1

Signal:

DATA_ERR_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	26905	1
Bin	1	0	26911	1

Signal:

NOM_ERR_CTR_Q(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1662	1

Signal:

NOM_ERR_CTR_Q(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1668	1

Signal:

NOM_ERR_CTR_Q(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1663	1

Signal:

NOM_ERR_CTR_Q(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1657	1

Signal:

NOM_ERR_CTR_Q(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1655	1

Signal:

NOM_ERR_CTR_Q(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Signal:

NOM_ERR_CTR_Q(9)

	From	To	Count	Threshold
Bin	0	1	68	1
Bin	1	0	1665	1

Signal:

NOM_ERR_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1670	1

Signal:

NOM_ERR_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1676	1

Signal:

NOM_ERR_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1698	1

Signal:

NOM_ERR_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	160	1
Bin	1	0	1759	1

Signal:

NOM_ERR_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	282	1
Bin	1	0	1878	1

Signal:

NOM_ERR_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	2194	1

Signal:

NOM_ERR_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	1361	1
Bin	1	0	2956	1

Signal:

NOM_ERR_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	3048	1
Bin	1	0	4645	1

Signal:

NOM_ERR_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	11189	1
Bin	1	0	12783	1

Signal:

DATA_ERR_CTR_Q(15)

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	1670	1

Signal:

DATA_ERR_CTR_Q(14)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1660	1

Signal:

DATA_ERR_CTR_Q(13)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Signal:

DATA_ERR_CTR_Q(12)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1662	1

Signal:

DATA_ERR_CTR_Q(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1657	1

Signal:

DATA_ERR_CTR_Q(10)

	From	To	Count	Threshold
Bin	0	1	58	1
Bin	1	0	1656	1

Signal:

DATA_ERR_CTR_Q(9)

	From	To	Count	Threshold
Bin	0	1	74	1
Bin	1	0	1670	1

Signal:

DATA_ERR_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	85	1
Bin	1	0	1683	1

Signal:

DATA_ERR_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	103	1
Bin	1	0	1701	1

Signal:

DATA_ERR_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	138	1
Bin	1	0	1735	1

Signal:

DATA_ERR_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	205	1
Bin	1	0	1802	1

Signal:

DATA_ERR_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	359	1
Bin	1	0	1956	1

Signal:

DATA_ERR_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	679	1
Bin	1	0	2274	1

Signal:

DATA_ERR_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	1295	1
Bin	1	0	2892	1

Signal:

DATA_ERR_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	2524	1
Bin	1	0	4120	1

Signal:

DATA_ERR_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	5478	1
Bin	1	0	7073	1

Signal:

NOM_DAT_SEL_CTR(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1662	1

Signal:

NOM_DAT_SEL_CTR(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1668	1

Signal:

NOM_DAT_SEL_CTR(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1663	1

Signal:

NOM_DAT_SEL_CTR(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1657	1

Signal:

NOM_DAT_SEL_CTR(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1655	1

Signal:

NOM_DAT_SEL_CTR(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Signal:

NOM_DAT_SEL_CTR(9)

	From	To	Count	Threshold
Bin	0	1	4541	1
Bin	1	0	6138	1

Signal:

NOM_DAT_SEL_CTR(8)

	From	To	Count	Threshold
Bin	0	1	4555	1
Bin	1	0	6152	1

Signal:

NOM_DAT_SEL_CTR(7)

	From	To	Count	Threshold
Bin	0	1	4619	1
Bin	1	0	6216	1

Signal:

NOM_DAT_SEL_CTR(6)

	From	To	Count	Threshold
Bin	0	1	4921	1
Bin	1	0	6518	1

Signal:

NOM_DAT_SEL_CTR(5)

	From	To	Count	Threshold
Bin	0	1	5404	1
Bin	1	0	7003	1

Signal:

NOM_DAT_SEL_CTR(4)

	From	To	Count	Threshold
Bin	0	1	5847	1
Bin	1	0	7443	1

Signal:

NOM_DAT_SEL_CTR(3)

	From	To	Count	Threshold
Bin	0	1	7111	1
Bin	1	0	8705	1

Signal:

NOM_DAT_SEL_CTR(2)

	From	To	Count	Threshold
Bin	0	1	8708	1
Bin	1	0	10303	1

Signal:

NOM_DAT_SEL_CTR(1)

	From	To	Count	Threshold
Bin	0	1	12007	1
Bin	1	0	13604	1

Signal:

NOM_DAT_SEL_CTR(0)

	From	To	Count	Threshold
Bin	0	1	23333	1
Bin	1	0	24927	1

Signal:

NOM_DAT_SEL_CTR_ADD(15)

	From	To	Count	Threshold
Bin	0	1	66	1
Bin	1	0	1662	1

Signal:

NOM_DAT_SEL_CTR_ADD(14)

	From	To	Count	Threshold
Bin	0	1	69	1
Bin	1	0	1668	1

Signal:

NOM_DAT_SEL_CTR_ADD(13)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1663	1

Signal:

NOM_DAT_SEL_CTR_ADD(12)

	From	To	Count	Threshold
Bin	0	1	61	1
Bin	1	0	1657	1

Signal:

NOM_DAT_SEL_CTR_ADD(11)

	From	To	Count	Threshold
Bin	0	1	59	1
Bin	1	0	1655	1

Signal:

NOM_DAT_SEL_CTR_ADD(10)

	From	To	Count	Threshold
Bin	0	1	63	1
Bin	1	0	1661	1

Signal:

NOM_DAT_SEL_CTR_ADD(9)

	From	To	Count	Threshold
Bin	0	1	4549	1
Bin	1	0	6146	1

Signal:

NOM_DAT_SEL_CTR_ADD(8)

	From	To	Count	Threshold
Bin	0	1	4564	1
Bin	1	0	6161	1

Signal:

NOM_DAT_SEL_CTR_ADD(7)

	From	To	Count	Threshold
Bin	0	1	4628	1
Bin	1	0	6225	1

Signal:

NOM_DAT_SEL_CTR_ADD(6)

	From	To	Count	Threshold
Bin	0	1	4946	1
Bin	1	0	6543	1

Signal:

NOM_DAT_SEL_CTR_ADD(5)

	From	To	Count	Threshold
Bin	0	1	5408	1
Bin	1	0	7006	1

Signal:

NOM_DAT_SEL_CTR_ADD(4)

	From	To	Count	Threshold
Bin	0	1	6005	1
Bin	1	0	7602	1

Signal:

NOM_DAT_SEL_CTR_ADD(3)

	From	To	Count	Threshold
Bin	0	1	7146	1
Bin	1	0	8741	1

Signal:

NOM_DAT_SEL_CTR_ADD(2)

	From	To	Count	Threshold
Bin	0	1	9016	1
Bin	1	0	10611	1

Signal:

NOM_DAT_SEL_CTR_ADD(1)

	From	To	Count	Threshold
Bin	0	1	18535	1
Bin	1	0	20130	1

Signal:

NOM_DAT_SEL_CTR_ADD(0)

	From	To	Count	Threshold
Bin	0	1	24927	1
Bin	1	0	23333	1

Signal:

NOM_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	126471	1
Bin	1	0	128071	1

Signal:

DATA_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	19915	1
Bin	1	0	21515	1

Signal:

RES_ERR_CTRS_D

	From	To	Count	Threshold
Bin	0	1	14718	1
Bin	1	0	14708	1

Signal:

RES_ERR_CTRS_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	14717	1
Bin	1	0	14708	1

Signal:

MR_CTR_PRES_PTX_Q

	From	To	Count	Threshold
Bin	0	1	18698	1
Bin	1	0	20298	1

Signal:

MR_CTR_PRES_PRX_Q

	From	To	Count	Threshold
Bin	0	1	19085	1
Bin	1	0	20685	1

Signal:

MR_CTR_PRES_ENORM_Q

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	7542	1

Signal:

MR_CTR_PRES_EFD_Q

	From	To	Count	Threshold
Bin	0	1	5942	1
Bin	1	0	7542	1

Uncovered expressions:

Excluded expressions:

"and" expression

361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"or" expression

368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
                                      <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression

367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

Covered expressions:

"=" expression

215: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else

	Evaluated to	Count	Threshold
Bin	False	134730	1
Bin	True	79370	1

"=" expression

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else

	Evaluated to	Count	Threshold
Bin	False	188020	1
Bin	True	26080	1

"or" expression

228:    modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else 
                                  <-----LHS----->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	108650	1
Bin	False	True	26080	1
Bin	True	False	79370	1

"=" expression

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	False	258946	1
Bin	True	44878	1

"=" expression

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	False	224454	1
Bin	True	79370	1

"or" expression

232:    modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1') 
                                  <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	179576	1
Bin	False	True	79370	1
Bin	True	False	44878	1

"=" expression

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	False	277744	1
Bin	True	26080	1

"or" expression

232:    modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1') 
                                  <-------------LHS-------------->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	153496	1
Bin	False	True	26080	1
Bin	True	False	124248	1

"=" expression

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	240391	1
Bin	True	19928	1

"=" expression

246: tx_err_ctr_q + 8 when (inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	False	133079	1
Bin	True	107312	1

"=" expression

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else

	Evaluated to	Count	Threshold
Bin	False	187430	1
Bin	True	105450	1

"=" expression

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else

	Evaluated to	Count	Threshold
Bin	False	108594	1
Bin	True	184286	1

"and" expression

251:    tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else 
                                   <------LHS------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	102201	1
Bin	True	False	23365	1
Bin	True	True	82085	1

"=" expression

252: '1' when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	192097	1
Bin	True	18698	1

"=" expression

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')

	Evaluated to	Count	Threshold
Bin	False	24554	1
Bin	True	8072	1

"=" expression

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')

	Evaluated to	Count	Threshold
Bin	False	25990	1
Bin	True	6636	1

"or" expression

258:    res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1') 
                                    <---LHS--->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	17918	1
Bin	False	True	6636	1
Bin	True	False	8072	1

"=" expression

284: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052738983	1
Bin	True	2451371	1

"=" expression

287: if (tx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526317415	1
Bin	True	43767	1

"=" expression

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else

	Evaluated to	Count	Threshold
Bin	False	61604	1
Bin	True	56997	1

"=" expression

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	399045	1
Bin	True	21703	1

"=" expression

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	False	327863	1
Bin	True	71182	1

"=" expression

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	False	318797	1
Bin	True	80248	1

"or" expression

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else 
                                                         <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	247615	1
Bin	False	True	80248	1
Bin	True	False	71182	1

"=" expression

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	False	255036	1
Bin	True	150296	1

"=" expression

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	False	238130	1
Bin	True	167202	1

"and" expression

320:    rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else 
                                   <------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	99045	1
Bin	True	False	82139	1
Bin	True	True	68157	1

"=" expression

321: '1' when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	318090	1
Bin	True	19085	1

"=" expression

329: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052738983	1
Bin	True	2451371	1

"=" expression

332: if (rx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526314534	1
Bin	True	46648	1

"=" expression

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')

	Evaluated to	Count	Threshold
Bin	False	9142	1
Bin	True	69365	1

"=" expression

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')

	Evaluated to	Count	Threshold
Bin	False	13411	1
Bin	True	65096	1

"=" expression

360: nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or

	Evaluated to	Count	Threshold
Bin	False	317941	1
Bin	True	5942	1

"=" expression

361: ((inc_one = '1' or inc_eight = '1') and

	Evaluated to	Count	Threshold
Bin	False	266610	1
Bin	True	51331	1

"=" expression

361: ((inc_one = '1' or inc_eight = '1') and

	Evaluated to	Count	Threshold
Bin	False	234713	1
Bin	True	83228	1

"or" expression

361:                               ((inc_one = '1' or inc_eight = '1') and 
                                     <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	183382	1
Bin	False	True	83228	1
Bin	True	False	51331	1

"and" expression

361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	True	False	13998	1
Bin	True	True	120561	1

"or" expression

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	False	False	197380	1
Bin	False	True	120561	1

"=" expression

366: data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or

	Evaluated to	Count	Threshold
Bin	False	317941	1
Bin	True	5942	1

"=" expression

367: ((inc_one = '1' or inc_eight = '1') and

	Evaluated to	Count	Threshold
Bin	False	266610	1
Bin	True	51331	1

"=" expression

367: ((inc_one = '1' or inc_eight = '1') and

	Evaluated to	Count	Threshold
Bin	False	234713	1
Bin	True	83228	1

"or" expression

367:                                ((inc_one = '1' or inc_eight = '1') and 
                                      <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	183382	1
Bin	False	True	83228	1
Bin	True	False	51331	1

"or" expression

368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
                                      <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	120561	1
Bin	False	True	1754	1

"and" expression

367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	True	False	120561	1
Bin	True	True	13998	1

"or" expression

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	LHS	RHS	Count	Threshold
Bin	False	False	303943	1
Bin	False	True	13998	1

"=" expression

377: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052738983	1
Bin	True	2451371	1

"=" expression

380: if (nom_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526338938	1
Bin	True	22244	1

"=" expression

388: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052738983	1
Bin	True	2451371	1

"=" expression

391: if (data_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526344954	1
Bin	True	16228	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/err_counters.vhd

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