NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
RST_REG_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST	100.0 % (83/83)	100.0 % (70/70)	100.0 % (508/508)	100.0 % (114/114)	N.A.	N.A.	100.0 % (775/775)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 215 to 225:

215:        if (res_n = '0') then 
216:            mr_ctr_pres_ptx_q   <= '0'; 
...
224:            mr_ctr_pres_efd_q   <= mr_ctr_pres_efd; 
225:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 216:

216: mr_ctr_pres_ptx_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 217:

217: mr_ctr_pres_prx_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 218:

218: mr_ctr_pres_enorm_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 219:

219: mr_ctr_pres_efd_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 221:

221: mr_ctr_pres_ptx_q <= mr_ctr_pres_ptx;
Count: 543791678
Threshold: 1

Signal assignment statement on line 222:

222: mr_ctr_pres_prx_q <= mr_ctr_pres_prx;
Count: 543791678
Threshold: 1

Signal assignment statement on line 223:

223: mr_ctr_pres_enorm_q <= mr_ctr_pres_enorm;
Count: 543791678
Threshold: 1

Signal assignment statement on line 224:

224: mr_ctr_pres_efd_q <= mr_ctr_pres_efd;
Count: 543791678
Threshold: 1

If statement on lines 228 to 229:

228:    modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else 
229:                    '0';

Count: 216750
Threshold: 1

Signal assignment statement on line 228:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else
Count: 106774
Threshold: 1

Signal assignment statement on line 229:

229: '0';
Count: 109976
Threshold: 1

If statement on lines 232 to 234:

232:    modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1') 
233:                        else 
234:                    '0';

Count: 306338
Threshold: 1

Signal assignment statement on line 232:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')
Count: 151584
Threshold: 1

Signal assignment statement on line 234:

234: '0';
Count: 154754
Threshold: 1

If statement on lines 239 to 240:

239:    tx_err_ctr_dec <=  (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else 
240:                       tx_err_ctr_q;

Count: 33426
Threshold: 1

Signal assignment statement on line 239:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else
Count: 19570
Threshold: 1

Signal assignment statement on line 240:

240: tx_err_ctr_q;
Count: 13856
Threshold: 1

If statement on lines 244 to 247:

244:    tx_err_ctr_d <= 
245:              unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else 
246:                        tx_err_ctr_q + 8 when (inc_eight = '1') else 
247:                          tx_err_ctr_dec;

Count: 266083
Threshold: 1

Signal assignment statement on line 245:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else
Count: 20359
Threshold: 1

Signal assignment statement on line 246:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else
Count: 109505
Threshold: 1

Signal assignment statement on line 247:

247: tx_err_ctr_dec;
Count: 136219
Threshold: 1

If statement on lines 251 to 253:

251:    tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else 
252:                     '1' when (mr_ctr_pres_ptx_q = '1') else 
253:                     '0';

Count: 297234
Threshold: 1

Signal assignment statement on line 251:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else
Count: 83387
Threshold: 1

Signal assignment statement on line 252:

252: '1' when (mr_ctr_pres_ptx_q = '1') else
Count: 19126
Threshold: 1

Signal assignment statement on line 253:

253: '0';
Count: 194721
Threshold: 1

If statement on lines 258 to 260:

258:    res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1') 
259:                          else 
260:                      '1';

Count: 32632
Threshold: 1

Signal assignment statement on line 258:

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')
Count: 14709
Threshold: 1

Signal assignment statement on line 260:

260: '1';
Count: 17923
Threshold: 1

If statement on lines 284 to 290:

284:        if (res_err_ctrs_q_scan = '0') then 
285:            tx_err_ctr_q <= (others => '0'); 
...
289:            end if; 
290:        end if;

Count: 1090031479
Threshold: 1

Signal assignment statement on line 285:

285: tx_err_ctr_q <= (others => '0');
Count: 2457760
Threshold: 1

If statement on lines 287 to 289:

287:            if (tx_err_ctr_ce = '1') then 
288:                tx_err_ctr_q <= tx_err_ctr_d; 
289:            end if;

Count: 543778558
Threshold: 1

Signal assignment statement on line 288:

288: tx_err_ctr_q <= tx_err_ctr_d;
Count: 44649
Threshold: 1

If statement on lines 297 to 299:

297:    rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else 
298:                       (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else 
299:                            rx_err_ctr_q;

Count: 27286
Threshold: 1

Signal assignment statement on line 297:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else
Count: 8752
Threshold: 1

Signal assignment statement on line 298:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else
Count: 9029
Threshold: 1

Signal assignment statement on line 299:

299: rx_err_ctr_q;
Count: 9505
Threshold: 1

If statement on lines 303 to 304:

303:    rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else 
304:                      rx_err_ctr_q + 8;

Count: 118507
Threshold: 1

Signal assignment statement on line 303:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else
Count: 56949
Threshold: 1

Signal assignment statement on line 304:

304: rx_err_ctr_q + 8;
Count: 61558
Threshold: 1

If statement on lines 307 to 308:

307:    rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else 
308:                      rx_err_ctr_inc;

Count: 144192
Threshold: 1

Signal assignment statement on line 307:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else
Count: 695
Threshold: 1

Signal assignment statement on line 308:

308: rx_err_ctr_inc;
Count: 143497
Threshold: 1

If statement on lines 314 to 316:

314:    rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else 
315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else 
316:                                rx_err_ctr_dec;

Count: 424933
Threshold: 1

Signal assignment statement on line 314:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else
Count: 22598
Threshold: 1

Signal assignment statement on line 315:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

Count: 152735
Threshold: 1

Signal assignment statement on line 316:

316: rx_err_ctr_dec;
Count: 249600
Threshold: 1

If statement on lines 320 to 322:

320:    rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else 
321:                     '1' when (mr_ctr_pres_prx_q = '1') else 
322:                     '0';

Count: 408760
Threshold: 1

Signal assignment statement on line 320:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else
Count: 68111
Threshold: 1

Signal assignment statement on line 321:

321: '1' when (mr_ctr_pres_prx_q = '1') else
Count: 19522
Threshold: 1

Signal assignment statement on line 322:

322: '0';
Count: 321127
Threshold: 1

If statement on lines 329 to 335:

329:        if (res_err_ctrs_q_scan = '0') then 
330:            rx_err_ctr_q <= (others => '0'); 
...
334:            end if; 
335:        end if;

Count: 1090031479
Threshold: 1

Signal assignment statement on line 330:

330: rx_err_ctr_q <= (others => '0');
Count: 2457760
Threshold: 1

If statement on lines 332 to 334:

332:            if (rx_err_ctr_ce = '1') then 
333:                rx_err_ctr_q <= rx_err_ctr_d; 
334:            end if;

Count: 543778558
Threshold: 1

Signal assignment statement on line 333:

333: rx_err_ctr_q <= rx_err_ctr_d;
Count: 47116
Threshold: 1

If statement on lines 346 to 347:

346:    nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else 
347:                       data_err_ctr_q;

Count: 96242
Threshold: 1

Signal assignment statement on line 346:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else
Count: 54945
Threshold: 1

Signal assignment statement on line 347:

347: data_err_ctr_q;
Count: 41297
Threshold: 1

Signal assignment statement on line 349:

349: nom_dat_sel_ctr_add <= nom_dat_sel_ctr + 1;
Count: 63624
Threshold: 1

If statement on lines 351 to 353:

351:    nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0') 
352:                                         else 
353:                         (others => '0');

Count: 79564
Threshold: 1

Signal assignment statement on line 351:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')
Count: 69993
Threshold: 1

Signal assignment statement on line 353:

353: (others => '0');
Count: 9571
Threshold: 1

If statement on lines 355 to 357:

355:    data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0') 
356:                                          else 
357:                         (others => '0');

Count: 79564
Threshold: 1

Signal assignment statement on line 355:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')
Count: 65432
Threshold: 1

Signal assignment statement on line 357:

357: (others => '0');
Count: 14132
Threshold: 1

If statement on lines 360 to 364:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE)) 
363:                          else 
364:                      '0';

Count: 326633
Threshold: 1

Signal assignment statement on line 360:

360: nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or
Count: 128437
Threshold: 1

Signal assignment statement on line 364:

364: '0';
Count: 198196
Threshold: 1

If statement on lines 366 to 370:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
369:                           else 
370:                       '0';

Count: 326633
Threshold: 1

Signal assignment statement on line 366:

366: data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or
Count: 20221
Threshold: 1

Signal assignment statement on line 370:

370: '0';
Count: 306412
Threshold: 1

If statement on lines 377 to 383:

377:        if (res_err_ctrs_q_scan = '0') then 
378:            nom_err_ctr_q <= (others => '0'); 
...
382:            end if; 
383:        end if;

Count: 1090031479
Threshold: 1

Signal assignment statement on line 378:

378: nom_err_ctr_q <= (others => '0');
Count: 2457760
Threshold: 1

If statement on lines 380 to 382:

380:            if (nom_err_ctr_ce = '1') then 
381:                nom_err_ctr_q <= nom_err_ctr_d; 
382:            end if;

Count: 543778558
Threshold: 1

Signal assignment statement on line 381:

381: nom_err_ctr_q <= nom_err_ctr_d;
Count: 23026
Threshold: 1

If statement on lines 388 to 394:

388:        if (res_err_ctrs_q_scan = '0') then 
389:            data_err_ctr_q <= (others => '0'); 
...
393:            end if; 
394:        end if;

Count: 1090031479
Threshold: 1

Signal assignment statement on line 389:

389: data_err_ctr_q <= (others => '0');
Count: 2457760
Threshold: 1

If statement on lines 391 to 393:

391:            if (data_err_ctr_ce = '1') then 
392:                data_err_ctr_q <= data_err_ctr_d; 
393:            end if;

Count: 543778558
Threshold: 1

Signal assignment statement on line 392:

392: data_err_ctr_q <= data_err_ctr_d;
Count: 16773
Threshold: 1

Signal assignment statement on line 400:

400: rx_err_ctr <= std_logic_vector(rx_err_ctr_q);
Count: 27286
Threshold: 1

Signal assignment statement on line 401:

401: tx_err_ctr <= std_logic_vector(tx_err_ctr_q);
Count: 33426
Threshold: 1

Signal assignment statement on line 403:

403: norm_err_ctr <= std_logic_vector(nom_err_ctr_q);
Count: 27160
Threshold: 1

Signal assignment statement on line 404:

404: data_err_ctr <= std_logic_vector(data_err_ctr_q);
Count: 14587
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 215:

215: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 220:

220: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 228:

228: modif_tx_ctr <= '1' when (inc_eight = '1' or dec_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	106774	1
Bin	False	109976	1

"if" / "when" / "else" condition on line 232:

232: modif_rx_ctr <= '1' when (inc_one = '1' or inc_eight = '1' or dec_one = '1')

	Evaluated to	Count	Threshold
Bin	True	151584	1
Bin	False	154754	1

"if" / "when" / "else" condition on line 239:

239: tx_err_ctr_dec <= (tx_err_ctr_q - 1) when (tx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	19570	1
Bin	False	13856	1

"if" / "when" / "else" condition on line 245:

245: unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	20359	1
Bin	False	245724	1

"if" / "when" / "else" condition on line 246:

246: tx_err_ctr_q + 8 when (inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	109505	1
Bin	False	136219	1

"if" / "when" / "else" condition on line 251:

251: tx_err_ctr_ce <= '1' when (modif_tx_ctr = '1' and is_transmitter = '1') else

	Evaluated to	Count	Threshold
Bin	True	83387	1
Bin	False	213847	1

"if" / "when" / "else" condition on line 252:

252: '1' when (mr_ctr_pres_ptx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19126	1
Bin	False	194721	1

"if" / "when" / "else" condition on line 258:

258: res_err_ctrs_d <= '0' when (res_n = '0' or set_err_active = '1')

	Evaluated to	Count	Threshold
Bin	True	14709	1
Bin	False	17923	1

"if" / "when" / "else" condition on line 284:

284: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2457760	1
Bin	False	1087573719	1

"if" / "when" / "else" condition on line 286:

286: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543778558	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 287:

287: if (tx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	44649	1
Bin	False	543733909	1

"if" / "when" / "else" condition on line 297:

297: rx_err_ctr_dec <= to_unsigned(120, 9) when (rx_err_ctr_q > 127) else

	Evaluated to	Count	Threshold
Bin	True	8752	1
Bin	False	18534	1

"if" / "when" / "else" condition on line 298:

298: (rx_err_ctr_q - 1) when (rx_err_ctr_q > 0) else

	Evaluated to	Count	Threshold
Bin	True	9029	1
Bin	False	9505	1

"if" / "when" / "else" condition on line 303:

303: rx_err_ctr_inc <= rx_err_ctr_q + 1 when (inc_one = '1') else

	Evaluated to	Count	Threshold
Bin	True	56949	1
Bin	False	61558	1

"if" / "when" / "else" condition on line 307:

307: rx_err_ctr_sat <= (others => '1') when (rx_err_ctr_inc < rx_err_ctr_q) else

	Evaluated to	Count	Threshold
Bin	True	695	1
Bin	False	143497	1

"if" / "when" / "else" condition on line 314:

314: rx_err_ctr_d <= unsigned(mr_ctr_pres_ctpv) when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	22598	1
Bin	False	402335	1

"if" / "when" / "else" condition on line 315:

315:                                rx_err_ctr_sat when (inc_one = '1' or inc_eight = '1') else

	Evaluated to	Count	Threshold
Bin	True	152735	1
Bin	False	249600	1

"if" / "when" / "else" condition on line 320:

320: rx_err_ctr_ce <= '1' when (modif_rx_ctr = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	True	68111	1
Bin	False	340649	1

"if" / "when" / "else" condition on line 321:

321: '1' when (mr_ctr_pres_prx_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	19522	1
Bin	False	321127	1

"if" / "when" / "else" condition on line 329:

329: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2457760	1
Bin	False	1087573719	1

"if" / "when" / "else" condition on line 331:

331: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543778558	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 332:

332: if (rx_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	47116	1
Bin	False	543731442	1

"if" / "when" / "else" condition on line 346:

346: nom_dat_sel_ctr <= nom_err_ctr_q when (sp_control = NOMINAL_SAMPLE) else

	Evaluated to	Count	Threshold
Bin	True	54945	1
Bin	False	41297	1

"if" / "when" / "else" condition on line 351:

351: nom_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_enorm_q = '0')

	Evaluated to	Count	Threshold
Bin	True	69993	1
Bin	False	9571	1

"if" / "when" / "else" condition on line 355:

355: data_err_ctr_d <= nom_dat_sel_ctr_add when (mr_ctr_pres_efd_q = '0')

	Evaluated to	Count	Threshold
Bin	True	65432	1
Bin	False	14132	1

"if" / "when" / "else" condition on lines 360 to 362:

360:    nom_err_ctr_ce <= '1' when (mr_ctr_pres_enorm_q = '1') or 
361:                               ((inc_one = '1' or inc_eight = '1') and 
362:                                (sp_control = NOMINAL_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	128437	1
Bin	False	198196	1

"if" / "when" / "else" condition on lines 366 to 368:

366:    data_err_ctr_ce <= '1' when (mr_ctr_pres_efd_q = '1') or 
367:                                ((inc_one = '1' or inc_eight = '1') and 
368:                                 (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE))

	Evaluated to	Count	Threshold
Bin	True	20221	1
Bin	False	306412	1

"if" / "when" / "else" condition on line 377:

377: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2457760	1
Bin	False	1087573719	1

"if" / "when" / "else" condition on line 379:

379: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543778558	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 380:

380: if (nom_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	23026	1
Bin	False	543755532	1

"if" / "when" / "else" condition on line 388:

388: if (res_err_ctrs_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	2457760	1
Bin	False	1087573719	1

"if" / "when" / "else" condition on line 390:

390: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543778558	1
Bin	False	543795161	1

"if" / "when" / "else" condition on line 391:

391: if (data_err_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	16773	1
Bin	False	543761785	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SP_CONTROL

	Element	From	To	Threshold	Excluded due to
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

INC_ONE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

INC_EIGHT

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DEC_ONE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_CTPV

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_CTR_PRES_PTX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_PRX

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_ENORM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_CTR_PRES_EFD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Signal:

RX_ERR_CTR_DEC

	Element	From	To	Count	Threshold	Excluded due to
Bin	(8)	0	1	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file

Covered toggles:

Port:

RX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126	1
Bin	(8)	1	0	1727	1
Bin	(7)	0	1	344	1
Bin	(7)	1	0	1945	1
Bin	(6)	0	1	262	1
Bin	(6)	1	0	1860	1
Bin	(5)	0	1	343	1
Bin	(5)	1	0	1943	1
Bin	(4)	0	1	501	1
Bin	(4)	1	0	2101	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2280	1
Bin	(2)	0	1	639	1
Bin	(2)	1	0	2240	1
Bin	(1)	0	1	1198	1
Bin	(1)	1	0	2799	1
Bin	(0)	0	1	11242	1
Bin	(0)	1	0	12836	1

Port:

TX_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(8)	0	1	246	1
Bin	(8)	1	0	1847	1
Bin	(7)	0	1	506	1
Bin	(7)	1	0	2107	1
Bin	(6)	0	1	504	1
Bin	(6)	1	0	2105	1
Bin	(5)	0	1	787	1
Bin	(5)	1	0	2388	1
Bin	(4)	0	1	1957	1
Bin	(4)	1	0	3557	1
Bin	(3)	0	1	12521	1
Bin	(3)	1	0	14122	1
Bin	(2)	0	1	2978	1
Bin	(2)	1	0	4579	1
Bin	(1)	0	1	3314	1
Bin	(1)	1	0	4915	1
Bin	(0)	0	1	3548	1
Bin	(0)	1	0	5149	1

Port:

NORM_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	54	1
Bin	(9)	1	0	1654	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1668	1
Bin	(7)	0	1	83	1
Bin	(7)	1	0	1682	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1695	1
Bin	(5)	0	1	150	1
Bin	(5)	1	0	1747	1
Bin	(4)	0	1	271	1
Bin	(4)	1	0	1869	1
Bin	(3)	0	1	605	1
Bin	(3)	1	0	2200	1
Bin	(2)	0	1	1369	1
Bin	(2)	1	0	2967	1
Bin	(1)	0	1	3083	1
Bin	(1)	1	0	4677	1
Bin	(0)	0	1	11506	1
Bin	(0)	1	0	13100	1

Port:

DATA_ERR_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	59	1
Bin	(15)	1	0	1657	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1666	1
Bin	(13)	0	1	70	1
Bin	(13)	1	0	1669	1
Bin	(12)	0	1	66	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	63	1
Bin	(11)	1	0	1663	1
Bin	(10)	0	1	68	1
Bin	(10)	1	0	1666	1
Bin	(9)	0	1	77	1
Bin	(9)	1	0	1674	1
Bin	(8)	0	1	90	1
Bin	(8)	1	0	1688	1
Bin	(7)	0	1	99	1
Bin	(7)	1	0	1698	1
Bin	(6)	0	1	126	1
Bin	(6)	1	0	1723	1
Bin	(5)	0	1	212	1
Bin	(5)	1	0	1809	1
Bin	(4)	0	1	363	1
Bin	(4)	1	0	1962	1
Bin	(3)	0	1	679	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1288	1
Bin	(2)	1	0	2888	1
Bin	(1)	0	1	2512	1
Bin	(1)	1	0	4112	1
Bin	(0)	0	1	5598	1
Bin	(0)	1	0	7196	1

Signal:

TX_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	654	1
Bin	(8)	1	0	2255	1
Bin	(7)	0	1	3044	1
Bin	(7)	1	0	4645	1
Bin	(6)	0	1	4270	1
Bin	(6)	1	0	5871	1
Bin	(5)	0	1	7977	1
Bin	(5)	1	0	9578	1
Bin	(4)	0	1	33197	1
Bin	(4)	1	0	34798	1
Bin	(3)	0	1	69306	1
Bin	(3)	1	0	70906	1
Bin	(2)	0	1	35807	1
Bin	(2)	1	0	37407	1
Bin	(1)	0	1	47620	1
Bin	(1)	1	0	49220	1
Bin	(0)	0	1	52363	1
Bin	(0)	1	0	53963	1

Signal:

RX_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	293	1
Bin	(8)	1	0	1894	1
Bin	(7)	0	1	24062	1
Bin	(7)	1	0	25663	1
Bin	(6)	0	1	24807	1
Bin	(6)	1	0	26405	1
Bin	(5)	0	1	20883	1
Bin	(5)	1	0	22483	1
Bin	(4)	0	1	7054	1
Bin	(4)	1	0	8654	1
Bin	(3)	0	1	128325	1
Bin	(3)	1	0	129925	1
Bin	(2)	0	1	25850	1
Bin	(2)	1	0	27451	1
Bin	(1)	0	1	28176	1
Bin	(1)	1	0	29777	1
Bin	(0)	0	1	25897	1
Bin	(0)	1	0	27498	1

Signal:

TX_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	246	1
Bin	(8)	1	0	1847	1
Bin	(7)	0	1	506	1
Bin	(7)	1	0	2107	1
Bin	(6)	0	1	504	1
Bin	(6)	1	0	2105	1
Bin	(5)	0	1	787	1
Bin	(5)	1	0	2388	1
Bin	(4)	0	1	1957	1
Bin	(4)	1	0	3557	1
Bin	(3)	0	1	12521	1
Bin	(3)	1	0	14122	1
Bin	(2)	0	1	2978	1
Bin	(2)	1	0	4579	1
Bin	(1)	0	1	3314	1
Bin	(1)	1	0	4915	1
Bin	(0)	0	1	3548	1
Bin	(0)	1	0	5149	1

Signal:

RX_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	126	1
Bin	(8)	1	0	1727	1
Bin	(7)	0	1	344	1
Bin	(7)	1	0	1945	1
Bin	(6)	0	1	262	1
Bin	(6)	1	0	1860	1
Bin	(5)	0	1	343	1
Bin	(5)	1	0	1943	1
Bin	(4)	0	1	501	1
Bin	(4)	1	0	2101	1
Bin	(3)	0	1	680	1
Bin	(3)	1	0	2280	1
Bin	(2)	0	1	639	1
Bin	(2)	1	0	2240	1
Bin	(1)	0	1	1198	1
Bin	(1)	1	0	2799	1
Bin	(0)	0	1	11242	1
Bin	(0)	1	0	12836	1

Signal:

RX_ERR_CTR_INC

	Element	From	To	Count	Threshold
Bin	(8)	0	1	131	1
Bin	(8)	1	0	1732	1
Bin	(7)	0	1	448	1
Bin	(7)	1	0	2049	1
Bin	(6)	0	1	448	1
Bin	(6)	1	0	2046	1
Bin	(5)	0	1	819	1
Bin	(5)	1	0	2419	1
Bin	(4)	0	1	2022	1
Bin	(4)	1	0	3621	1
Bin	(3)	0	1	46770	1
Bin	(3)	1	0	45170	1
Bin	(2)	0	1	5465	1
Bin	(2)	1	0	7066	1
Bin	(1)	0	1	13025	1
Bin	(1)	1	0	14626	1
Bin	(0)	0	1	56052	1
Bin	(0)	1	0	57646	1

Signal:

RX_ERR_CTR_SAT

	Element	From	To	Count	Threshold
Bin	(8)	0	1	641	1
Bin	(8)	1	0	2242	1
Bin	(7)	0	1	751	1
Bin	(7)	1	0	2352	1
Bin	(6)	0	1	824	1
Bin	(6)	1	0	2422	1
Bin	(5)	0	1	1154	1
Bin	(5)	1	0	2754	1
Bin	(4)	0	1	2209	1
Bin	(4)	1	0	3808	1
Bin	(3)	0	1	46812	1
Bin	(3)	1	0	45212	1
Bin	(2)	0	1	5642	1
Bin	(2)	1	0	7243	1
Bin	(1)	0	1	13218	1
Bin	(1)	1	0	14819	1
Bin	(0)	0	1	56377	1
Bin	(0)	1	0	57971	1

Signal:

TX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	102512	1
Bin	1	0	104113	1

Signal:

RX_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	87633	1
Bin	1	0	89234	1

Signal:

MODIF_TX_CTR

	From	To	Count	Threshold
Bin	0	1	106774	1
Bin	1	0	108375	1

Signal:

MODIF_RX_CTR

	From	To	Count	Threshold
Bin	0	1	151552	1
Bin	1	0	153153	1

Signal:

TX_ERR_CTR_DEC

	Element	From	To	Count	Threshold
Bin	(8)	0	1	230	1
Bin	(8)	1	0	1831	1
Bin	(7)	0	1	479	1
Bin	(7)	1	0	2080	1
Bin	(6)	0	1	498	1
Bin	(6)	1	0	2099	1
Bin	(5)	0	1	731	1
Bin	(5)	1	0	2332	1
Bin	(4)	0	1	1568	1
Bin	(4)	1	0	3169	1
Bin	(3)	0	1	2927	1
Bin	(3)	1	0	4527	1
Bin	(2)	0	1	10627	1
Bin	(2)	1	0	12227	1
Bin	(1)	0	1	10669	1
Bin	(1)	1	0	12269	1
Bin	(0)	0	1	11541	1
Bin	(0)	1	0	13141	1

Signal:

RX_ERR_CTR_DEC

	Element	From	To	Count	Threshold
Bin	(8)	1	0	1601	1
Bin	(7)	1	0	1601	1
Bin	(6)	0	1	427	1
Bin	(6)	1	0	2025	1
Bin	(5)	0	1	471	1
Bin	(5)	1	0	2071	1
Bin	(4)	0	1	594	1
Bin	(4)	1	0	2194	1
Bin	(3)	0	1	850	1
Bin	(3)	1	0	2450	1
Bin	(2)	0	1	526	1
Bin	(2)	1	0	2127	1
Bin	(1)	0	1	749	1
Bin	(1)	1	0	2350	1
Bin	(0)	0	1	1619	1
Bin	(0)	1	0	3220	1

Signal:

NOM_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	3266	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	3264	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	3263	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	3260	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	3271	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	3266	1
Bin	(9)	0	1	4535	1
Bin	(9)	1	0	7736	1
Bin	(8)	0	1	4560	1
Bin	(8)	1	0	7758	1
Bin	(7)	0	1	4634	1
Bin	(7)	1	0	7834	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	8143	1
Bin	(5)	0	1	5402	1
Bin	(5)	1	0	8600	1
Bin	(4)	0	1	5999	1
Bin	(4)	1	0	9198	1
Bin	(3)	0	1	7058	1
Bin	(3)	1	0	10254	1
Bin	(2)	0	1	9099	1
Bin	(2)	1	0	12295	1
Bin	(1)	0	1	22991	1
Bin	(1)	1	0	26185	1
Bin	(0)	0	1	27358	1
Bin	(0)	1	0	27365	1

Signal:

DATA_ERR_CTR_D

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	3266	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	3264	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	3263	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	3260	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	3271	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	3266	1
Bin	(9)	0	1	4535	1
Bin	(9)	1	0	7736	1
Bin	(8)	0	1	4560	1
Bin	(8)	1	0	7758	1
Bin	(7)	0	1	4634	1
Bin	(7)	1	0	7834	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	8143	1
Bin	(5)	0	1	5402	1
Bin	(5)	1	0	8600	1
Bin	(4)	0	1	5976	1
Bin	(4)	1	0	9175	1
Bin	(3)	0	1	7035	1
Bin	(3)	1	0	10231	1
Bin	(2)	0	1	8871	1
Bin	(2)	1	0	12067	1
Bin	(1)	0	1	18682	1
Bin	(1)	1	0	21876	1
Bin	(0)	0	1	27358	1
Bin	(0)	1	0	27365	1

Signal:

NOM_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	54	1
Bin	(9)	1	0	1654	1
Bin	(8)	0	1	71	1
Bin	(8)	1	0	1668	1
Bin	(7)	0	1	83	1
Bin	(7)	1	0	1682	1
Bin	(6)	0	1	97	1
Bin	(6)	1	0	1695	1
Bin	(5)	0	1	150	1
Bin	(5)	1	0	1747	1
Bin	(4)	0	1	271	1
Bin	(4)	1	0	1869	1
Bin	(3)	0	1	605	1
Bin	(3)	1	0	2200	1
Bin	(2)	0	1	1369	1
Bin	(2)	1	0	2967	1
Bin	(1)	0	1	3083	1
Bin	(1)	1	0	4677	1
Bin	(0)	0	1	11506	1
Bin	(0)	1	0	13100	1

Signal:

DATA_ERR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(15)	0	1	59	1
Bin	(15)	1	0	1657	1
Bin	(14)	0	1	68	1
Bin	(14)	1	0	1666	1
Bin	(13)	0	1	70	1
Bin	(13)	1	0	1669	1
Bin	(12)	0	1	66	1
Bin	(12)	1	0	1665	1
Bin	(11)	0	1	63	1
Bin	(11)	1	0	1663	1
Bin	(10)	0	1	68	1
Bin	(10)	1	0	1666	1
Bin	(9)	0	1	77	1
Bin	(9)	1	0	1674	1
Bin	(8)	0	1	90	1
Bin	(8)	1	0	1688	1
Bin	(7)	0	1	99	1
Bin	(7)	1	0	1698	1
Bin	(6)	0	1	126	1
Bin	(6)	1	0	1723	1
Bin	(5)	0	1	212	1
Bin	(5)	1	0	1809	1
Bin	(4)	0	1	363	1
Bin	(4)	1	0	1962	1
Bin	(3)	0	1	679	1
Bin	(3)	1	0	2278	1
Bin	(2)	0	1	1288	1
Bin	(2)	1	0	2888	1
Bin	(1)	0	1	2512	1
Bin	(1)	1	0	4112	1
Bin	(0)	0	1	5598	1
Bin	(0)	1	0	7196	1

Signal:

NOM_DAT_SEL_CTR

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	4527	1
Bin	(9)	1	0	6127	1
Bin	(8)	0	1	4553	1
Bin	(8)	1	0	6150	1
Bin	(7)	0	1	4623	1
Bin	(7)	1	0	6222	1
Bin	(6)	0	1	4917	1
Bin	(6)	1	0	6515	1
Bin	(5)	0	1	5394	1
Bin	(5)	1	0	6991	1
Bin	(4)	0	1	5832	1
Bin	(4)	1	0	7430	1
Bin	(3)	0	1	7015	1
Bin	(3)	1	0	8610	1
Bin	(2)	0	1	8569	1
Bin	(2)	1	0	10167	1
Bin	(1)	0	1	11762	1
Bin	(1)	1	0	13356	1
Bin	(0)	0	1	23624	1
Bin	(0)	1	0	25218	1

Signal:

NOM_DAT_SEL_CTR_ADD

	Element	From	To	Count	Threshold
Bin	(15)	0	1	67	1
Bin	(15)	1	0	1665	1
Bin	(14)	0	1	65	1
Bin	(14)	1	0	1663	1
Bin	(13)	0	1	66	1
Bin	(13)	1	0	1662	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	1659	1
Bin	(11)	0	1	71	1
Bin	(11)	1	0	1670	1
Bin	(10)	0	1	67	1
Bin	(10)	1	0	1665	1
Bin	(9)	0	1	4535	1
Bin	(9)	1	0	6135	1
Bin	(8)	0	1	4560	1
Bin	(8)	1	0	6157	1
Bin	(7)	0	1	4634	1
Bin	(7)	1	0	6233	1
Bin	(6)	0	1	4944	1
Bin	(6)	1	0	6542	1
Bin	(5)	0	1	5402	1
Bin	(5)	1	0	6999	1
Bin	(4)	0	1	5976	1
Bin	(4)	1	0	7574	1
Bin	(3)	0	1	7035	1
Bin	(3)	1	0	8630	1
Bin	(2)	0	1	8871	1
Bin	(2)	1	0	10466	1
Bin	(1)	0	1	18682	1
Bin	(1)	1	0	20275	1
Bin	(0)	0	1	25218	1
Bin	(0)	1	0	23624	1

Signal:

NOM_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	128405	1
Bin	1	0	130006	1

Signal:

DATA_ERR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	20196	1
Bin	1	0	21797	1

Signal:

RES_ERR_CTRS_D

	From	To	Count	Threshold
Bin	0	1	14721	1
Bin	1	0	14709	1

Signal:

RES_ERR_CTRS_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	14720	1
Bin	1	0	14709	1

Signal:

MR_CTR_PRES_PTX_Q

	From	To	Count	Threshold
Bin	0	1	19125	1
Bin	1	0	20726	1

Signal:

MR_CTR_PRES_PRX_Q

	From	To	Count	Threshold
Bin	0	1	19522	1
Bin	1	0	21123	1

Signal:

MR_CTR_PRES_ENORM_Q

	From	To	Count	Threshold
Bin	0	1	6369	1
Bin	1	0	7970	1

Signal:

MR_CTR_PRES_EFD_Q

	From	To	Count	Threshold
Bin	0	1	6369	1
Bin	1	0	7970	1

Uncovered expressions:

Excluded expressions:

"or" expression on lines 360 to 362:

 (mr_ctr_pres_enorm_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE)) 
  <----------LHS---------->      <-------------------------------RHS-------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 361 to 362:

 (inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE) 
  <-------------LHS-------------->       <-----------RHS----------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression on lines 366 to 368:

 (mr_ctr_pres_efd_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
  <---------LHS--------->      <----------------------------------------------RHS----------------------------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

"and" expression on lines 367 to 368:

 (inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
  <-------------LHS-------------->       <--------------------------RHS-------------------------->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

"or" expression on line 368:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold	Excluded due to
Bin	True	False	0	1	Unreachable

Covered expressions:

"=" expression on line 215:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"or" expression on line 228:

 inc_eight = '1' or dec_one = '1' 
 <-----LHS----->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	109976	1
Bin	False	True	26093	1
Bin	True	False	80681	1

"=" expression on line 228:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	136069	1
Bin	True	80681	1

"=" expression on line 228:

dec_one = '1'

	Evaluated to	Count	Threshold
Bin	False	190657	1
Bin	True	26093	1

"or" expression on line 232:

 inc_one = '1' or inc_eight = '1' or dec_one = '1' 
 <-------------LHS-------------->    <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	False	154754	1
Bin	False	True	26093	1
Bin	True	False	125491	1

"or" expression on line 232:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	180847	1
Bin	False	True	80681	1
Bin	True	False	44810	1

"=" expression on line 232:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	261528	1
Bin	True	44810	1

"=" expression on line 232:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	225657	1
Bin	True	80681	1

"=" expression on line 232:

dec_one = '1'

	Evaluated to	Count	Threshold
Bin	False	280245	1
Bin	True	26093	1

"=" expression on line 245:

mr_ctr_pres_ptx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	245724	1
Bin	True	20359	1

"=" expression on line 246:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	136219	1
Bin	True	109505	1

"and" expression on line 251:

 modif_tx_ctr = '1' and is_transmitter = '1' 
 <------LHS------->     <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	True	103919	1
Bin	True	False	23387	1
Bin	True	True	83387	1

"=" expression on line 251:

modif_tx_ctr = '1'

	Evaluated to	Count	Threshold
Bin	False	190460	1
Bin	True	106774	1

"=" expression on line 251:

is_transmitter = '1'

	Evaluated to	Count	Threshold
Bin	False	109928	1
Bin	True	187306	1

"=" expression on line 252:

mr_ctr_pres_ptx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	194721	1
Bin	True	19126	1

"or" expression on line 258:

 res_n = '0' or set_err_active = '1' 
 <---LHS--->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	17923	1
Bin	False	True	6637	1
Bin	True	False	8072	1

"=" expression on line 258:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	24560	1
Bin	True	8072	1

"=" expression on line 258:

set_err_active = '1'

	Evaluated to	Count	Threshold
Bin	False	25995	1
Bin	True	6637	1

"=" expression on line 284:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087573719	1
Bin	True	2457760	1

"=" expression on line 287:

tx_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543733909	1
Bin	True	44649	1

"=" expression on line 303:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	61558	1
Bin	True	56949	1

"=" expression on line 314:

mr_ctr_pres_prx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	402335	1
Bin	True	22598	1

"or" expression on line 315:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	249600	1
Bin	False	True	81575	1
Bin	True	False	71160	1

"=" expression on line 315:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	331175	1
Bin	True	71160	1

"=" expression on line 315:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	320760	1
Bin	True	81575	1

"and" expression on line 320:

 modif_rx_ctr = '1' and is_receiver = '1' 
 <------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	99019	1
Bin	True	False	83441	1
Bin	True	True	68111	1

"=" expression on line 320:

modif_rx_ctr = '1'

	Evaluated to	Count	Threshold
Bin	False	257208	1
Bin	True	151552	1

"=" expression on line 320:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	241630	1
Bin	True	167130	1

"=" expression on line 321:

mr_ctr_pres_prx_q = '1'

	Evaluated to	Count	Threshold
Bin	False	321127	1
Bin	True	19522	1

"=" expression on line 329:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087573719	1
Bin	True	2457760	1

"=" expression on line 332:

rx_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543731442	1
Bin	True	47116	1

"=" expression on line 351:

mr_ctr_pres_enorm_q = '0'

	Evaluated to	Count	Threshold
Bin	False	9571	1
Bin	True	69993	1

"=" expression on line 355:

mr_ctr_pres_efd_q = '0'

	Evaluated to	Count	Threshold
Bin	False	14132	1
Bin	True	65432	1

"or" expression on lines 360 to 362:

 (mr_ctr_pres_enorm_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE)) 
  <----------LHS---------->      <-------------------------------RHS-------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	198196	1
Bin	False	True	122068	1

"=" expression on line 360:

mr_ctr_pres_enorm_q = '1'

	Evaluated to	Count	Threshold
Bin	False	320264	1
Bin	True	6369	1

"and" expression on lines 361 to 362:

 (inc_one = '1' or inc_eight = '1') and (sp_control = NOMINAL_SAMPLE) 
  <-------------LHS-------------->       <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	True	False	13852	1
Bin	True	True	122068	1

"or" expression on line 361:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	184344	1
Bin	False	True	84656	1
Bin	True	False	51264	1

"=" expression on line 361:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	269000	1
Bin	True	51264	1

"=" expression on line 361:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	235608	1
Bin	True	84656	1

"or" expression on lines 366 to 368:

 (mr_ctr_pres_efd_q = '1') or ((inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE)) 
  <---------LHS--------->      <----------------------------------------------RHS----------------------------------------------->

	LHS	RHS	Count	Threshold
Bin	False	False	306412	1
Bin	False	True	13852	1

"=" expression on line 366:

mr_ctr_pres_efd_q = '1'

	Evaluated to	Count	Threshold
Bin	False	320264	1
Bin	True	6369	1

"and" expression on lines 367 to 368:

 (inc_one = '1' or inc_eight = '1') and (sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE) 
  <-------------LHS-------------->       <--------------------------RHS-------------------------->

	LHS	RHS	Count	Threshold
Bin	True	False	122068	1
Bin	True	True	13852	1

"or" expression on line 367:

 inc_one = '1' or inc_eight = '1' 
 <----LHS---->    <-----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	184344	1
Bin	False	True	84656	1
Bin	True	False	51264	1

"=" expression on line 367:

inc_one = '1'

	Evaluated to	Count	Threshold
Bin	False	269000	1
Bin	True	51264	1

"=" expression on line 367:

inc_eight = '1'

	Evaluated to	Count	Threshold
Bin	False	235608	1
Bin	True	84656	1

"or" expression on line 368:

 sp_control = DATA_SAMPLE or sp_control = SECONDARY_SAMPLE 
 <---------LHS---------->    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	False	122068	1
Bin	False	True	1472	1

"=" expression on line 377:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087573719	1
Bin	True	2457760	1

"=" expression on line 380:

nom_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543755532	1
Bin	True	23026	1

"=" expression on line 388:

res_err_ctrs_q_scan = '0'

	Evaluated to	Count	Threshold
Bin	False	1087573719	1
Bin	True	2457760	1

"=" expression on line 391:

data_err_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	543761785	1
Bin	True	16773	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

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Covered statements:

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Signal assignment statement on line 216:

Signal assignment statement on line 217:

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Signal assignment statement on line 224:

If statement on lines 228 to 229:

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Signal assignment statement on line 229:

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Signal assignment statement on line 234:

If statement on lines 239 to 240:

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Signal assignment statement on line 240:

If statement on lines 244 to 247:

Signal assignment statement on line 245:

Signal assignment statement on line 246:

Signal assignment statement on line 247:

If statement on lines 251 to 253:

Signal assignment statement on line 251:

Signal assignment statement on line 252:

Signal assignment statement on line 253:

If statement on lines 258 to 260:

Signal assignment statement on line 258:

Signal assignment statement on line 260:

If statement on lines 284 to 290:

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If statement on lines 287 to 289:

Signal assignment statement on line 288:

If statement on lines 297 to 299:

Signal assignment statement on line 297:

Signal assignment statement on line 298:

Signal assignment statement on line 299:

If statement on lines 303 to 304:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

If statement on lines 307 to 308:

Signal assignment statement on line 307:

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Signal assignment statement on line 320:

Signal assignment statement on line 321:

Signal assignment statement on line 322:

If statement on lines 329 to 335:

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Signal assignment statement on line 333:

If statement on lines 346 to 347:

Signal assignment statement on line 346:

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If statement on lines 351 to 353:

Signal assignment statement on line 351:

Signal assignment statement on line 353:

If statement on lines 355 to 357:

Signal assignment statement on line 355:

Signal assignment statement on line 357:

If statement on lines 360 to 364:

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Signal assignment statement on line 364:

If statement on lines 366 to 370:

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Signal assignment statement on line 370:

If statement on lines 377 to 383: