File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Fault confinement
71: --
72: -- Sub-modules:
73: -- 1. Fault confinement rules
74: -- 2. Error counters
75: -- 3. Fault confinement FSM.
76: --------------------------------------------------------------------------------
77:
78: Library ieee;
79: use ieee.std_logic_1164.all;
80: use ieee.numeric_std.ALL;
81:
82: Library ctu_can_fd_rtl;
83: use ctu_can_fd_rtl.can_constants_pkg.all;
84: use ctu_can_fd_rtl.can_types_pkg.all;
85:
86: use ctu_can_fd_rtl.CAN_FD_register_map.all;
87: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
88:
89: entity fault_confinement is
90: port (
91: -------------------------------------------------------------------------------------------
92: -- Clock and Asynchronous Reset
93: -------------------------------------------------------------------------------------------
94: clk_sys : in std_logic;
95: res_n : in std_logic;
96:
97: -------------------------------------------------------------------------------------------
98: -- DFT support
99: -------------------------------------------------------------------------------------------
100: scan_enable : in std_logic;
101:
102: -------------------------------------------------------------------------------------------
103: -- Memory registers interface
104: -------------------------------------------------------------------------------------------
105: mr_mode_rom : in std_logic;
106: mr_ewl_ew_limit : in std_logic_vector(7 downto 0);
107: mr_erp_erp_limit : in std_logic_vector(7 downto 0);
108: mr_ctr_pres_ctpv : in std_logic_vector(8 downto 0);
109: mr_ctr_pres_ptx : in std_logic;
110: mr_ctr_pres_prx : in std_logic;
111: mr_ctr_pres_enorm : in std_logic;
112: mr_ctr_pres_efd : in std_logic;
113: mr_status_ewl : out std_logic;
114:
115: -------------------------------------------------------------------------------------------
116: -- Error signalling for interrupts
117: -------------------------------------------------------------------------------------------
118: -- Fault confinement state changed
119: fcs_changed : out std_logic;
120:
121: -- Error warning limit was reached
122: err_warning_limit_pulse : out std_logic;
123:
124: -------------------------------------------------------------------------------------------
125: -- Operation control Interface
126: -------------------------------------------------------------------------------------------
127: -- Unit is transmitter
128: is_transmitter : in std_logic;
129:
130: -- Unit is receiver
131: is_receiver : in std_logic;
132:
133: -------------------------------------------------------------------------------------------
134: -- Protocol control Interface
135: -------------------------------------------------------------------------------------------
136: -- Sample control (Nominal, Data, Secondary)
137: sp_control : in std_logic_vector(1 downto 0);
138:
139: -- Set unit to error active (after re-integration). Erases eror counters to 0.
140: set_err_active : in std_logic;
141:
142: -- Error is detected
143: err_detected : in std_logic;
144:
145: -- Error counter should remain unchanged
146: err_ctrs_unchanged : in std_logic;
147:
148: -- Primary Error
149: primary_err : in std_logic;
150:
151: -- Active Error Flag or Overload flag is being tranmsmitted
152: act_err_ovr_flag : in std_logic;
153:
154: -- Error delimiter too late
155: err_delim_late : in std_logic;
156:
157: -- Transmission of frame valid
158: tran_valid : in std_logic;
159:
160: -- Decrement receive Error counter
161: decrement_rec : in std_logic;
162:
163: -- Bit Error after ACK error in Passive Error flag
164: bit_err_after_ack_err : in std_logic;
165:
166: -------------------------------------------------------------------------------------------
167: -- Fault confinement State indication
168: -------------------------------------------------------------------------------------------
169: -- Unit is error active
170: is_err_active : out std_logic;
171:
172: -- Unit is error passive
173: is_err_passive : out std_logic;
174:
175: -- Unit is Bus-off
176: is_bus_off : out std_logic;
177:
178: -------------------------------------------------------------------------------------------
179: -- Error counters
180: -------------------------------------------------------------------------------------------
181: -- TX Error counter
182: tx_err_ctr : out std_logic_vector(8 downto 0);
183:
184: -- RX Error counter
185: rx_err_ctr : out std_logic_vector(8 downto 0);
186:
187: -- Error counter in Nominal Bit-rate
188: norm_err_ctr : out std_logic_vector(15 downto 0);
189:
190: -- Error counter in Data Bit-rate
191: data_err_ctr : out std_logic_vector(15 downto 0)
192: );
193: end entity;
194:
195: architecture rtl of fault_confinement is
196:
197: -- Internal TX/RX Error counter values
198: signal tx_err_ctr_i : std_logic_vector(8 downto 0);
199: signal rx_err_ctr_i : std_logic_vector(8 downto 0);
200:
201: -- Increment decrement commands
202: signal inc_one : std_logic;
203: signal inc_eight : std_logic;
204: signal dec_one : std_logic;
205:
206: begin
207:
208: -----------------------------------------------------------------------------------------------
209: -- Fault confinement FSM
210: -----------------------------------------------------------------------------------------------
211: fault_confinement_fsm_inst : entity ctu_can_fd_rtl.fault_confinement_fsm
212: port map(
213: res_n => res_n, -- IN
214: clk_sys => clk_sys, -- IN
215:
216: mr_ewl_ew_limit => mr_ewl_ew_limit, -- IN
217: mr_erp_erp_limit => mr_erp_erp_limit, -- IN
218: mr_status_ewl => mr_status_ewl, -- OUT
219:
220: set_err_active => set_err_active, -- IN
221: tx_err_ctr => tx_err_ctr_i, -- IN
222: rx_err_ctr => rx_err_ctr_i, -- IN
223:
224: is_err_active => is_err_active, -- OUT
225: is_err_passive => is_err_passive, -- OUT
226: is_bus_off => is_bus_off, -- OUT
227:
228: fcs_changed => fcs_changed, -- OUT
229: err_warning_limit_pulse => err_warning_limit_pulse -- OUT
230: );
231:
232:
233: -----------------------------------------------------------------------------------------------
234: -- Error counters
235: -----------------------------------------------------------------------------------------------
236: err_counters_inst : entity ctu_can_fd_rtl.err_counters
237: port map(
238: clk_sys => clk_sys, -- IN
239: res_n => res_n, -- IN
240: scan_enable => scan_enable, -- IN
241:
242: sp_control => sp_control, -- IN
243: inc_one => inc_one, -- IN
244: inc_eight => inc_eight, -- IN
245: dec_one => dec_one, -- IN
246: set_err_active => set_err_active, -- IN
247: is_transmitter => is_transmitter, -- IN
248: is_receiver => is_receiver, -- IN
249:
250: mr_ctr_pres_ctpv => mr_ctr_pres_ctpv, -- IN
251: mr_ctr_pres_ptx => mr_ctr_pres_ptx, -- IN
252: mr_ctr_pres_prx => mr_ctr_pres_prx, -- IN
253: mr_ctr_pres_enorm => mr_ctr_pres_enorm, -- IN
254: mr_ctr_pres_efd => mr_ctr_pres_efd, -- IN
255:
256: rx_err_ctr => rx_err_ctr_i, -- OUT
257: tx_err_ctr => tx_err_ctr_i, -- OUT
258: norm_err_ctr => norm_err_ctr, -- OUT
259: data_err_ctr => data_err_ctr -- OUT
260: );
261:
262: -----------------------------------------------------------------------------------------------
263: -- Fault confinement rules
264: -----------------------------------------------------------------------------------------------
265: fault_confinement_rules_inst : entity ctu_can_fd_rtl.fault_confinement_rules
266: port map(
267: clk_sys => clk_sys, -- IN
268:
269: is_transmitter => is_transmitter, -- IN
270: is_receiver => is_receiver, -- IN
271: err_detected => err_detected, -- IN
272: err_ctrs_unchanged => err_ctrs_unchanged, -- IN
273: primary_err => primary_err, -- IN
274: act_err_ovr_flag => act_err_ovr_flag, -- IN
275: err_delim_late => err_delim_late, -- IN
276: tran_valid => tran_valid, -- IN
277: decrement_rec => decrement_rec, -- IN
278: bit_err_after_ack_err => bit_err_after_ack_err, -- IN
279:
280: mr_mode_rom => mr_mode_rom, -- IN
281:
282: inc_one => inc_one, -- OUT
283: inc_eight => inc_eight, -- OUT
284: dec_one => dec_one -- OUT
285: );
286:
287: -----------------------------------------------------------------------------------------------
288: -- Internal signals to output propagation
289: -----------------------------------------------------------------------------------------------
290: tx_err_ctr <= tx_err_ctr_i;
291: rx_err_ctr <= rx_err_ctr_i;
292:
293: end architecture;