NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
ADDRESS_DECODER_CONTROL_REGISTERS_COMP	100.0 % (121/121)	100.0 % (80/80)	100.0 % (252/252)	100.0 % (2/2)	N.A.	N.A.	100.0 % (455/455)
MODE_RST_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
MODE_BMM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_STM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_AFM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_FDE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_TTTM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_ROM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_ACF_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_TSTM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_RXBAM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_TXBBM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_SAM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
MODE_ERFM_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_RTRLE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_RTRTH_REG_COMP	100.0 % (18/18)	100.0 % (24/24)	100.0 % (34/34)	100.0 % (19/19)	N.A.	N.A.	100.0 % (95/95)
SETTINGS_ILBP_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_ENA_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_NISOFD_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_PEX_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_TBFBO_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_FDRF_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
SETTINGS_PCHKE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
COMMAND_RXRPMV_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_RRB_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_CDO_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_ERCRST_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_RXFCRST_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_TXFCRST_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_CPEXS_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_CRXPE_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_CTXPE_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
COMMAND_CTXDPE_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_RXI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_TXI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_EWLI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_DOI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_FCSI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_ALI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_BEI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_OFI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_RXFI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_BSI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_RBNEI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_STAT_TXBHCI_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
INT_ENA_SET_INT_ENA_SET_SLICE_1_REG_COMP	100.0 % (26/26)	100.0 % (16/16)	100.0 % (58/58)	100.0 % (19/19)	N.A.	N.A.	100.0 % (119/119)
INT_ENA_SET_INT_ENA_SET_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (8/8)	100.0 % (34/34)	100.0 % (11/11)	N.A.	N.A.	100.0 % (67/67)
INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG_COMP	100.0 % (26/26)	100.0 % (16/16)	100.0 % (58/58)	100.0 % (19/19)	N.A.	N.A.	100.0 % (119/119)
INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (8/8)	100.0 % (34/34)	100.0 % (11/11)	N.A.	N.A.	100.0 % (67/67)
INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP	100.0 % (26/26)	100.0 % (16/16)	100.0 % (58/58)	100.0 % (19/19)	N.A.	N.A.	100.0 % (119/119)
INT_MASK_SET_INT_MASK_SET_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (8/8)	100.0 % (34/34)	100.0 % (11/11)	N.A.	N.A.	100.0 % (67/67)
INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG_COMP	100.0 % (26/26)	100.0 % (16/16)	100.0 % (58/58)	100.0 % (19/19)	N.A.	N.A.	100.0 % (119/119)
INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (8/8)	100.0 % (34/34)	100.0 % (11/11)	N.A.	N.A.	100.0 % (67/67)
BTR_PROP_REG_COMP	100.0 % (30/30)	100.0 % (42/42)	100.0 % (54/54)	100.0 % (34/34)	N.A.	N.A.	100.0 % (160/160)
BTR_PH1_SLICE_1_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (40/40)
BTR_PH1_SLICE_2_REG_COMP	100.0 % (22/22)	100.0 % (30/30)	100.0 % (42/42)	100.0 % (26/26)	N.A.	N.A.	100.0 % (120/120)
BTR_PH2_SLICE_1_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (30/30)	100.0 % (18/18)	N.A.	N.A.	100.0 % (80/80)
BTR_PH2_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (30/30)	100.0 % (18/18)	N.A.	N.A.	100.0 % (80/80)
BTR_BRP_SLICE_1_REG_COMP	100.0 % (22/22)	100.0 % (30/30)	100.0 % (42/42)	100.0 % (26/26)	N.A.	N.A.	100.0 % (120/120)
BTR_BRP_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (30/30)	100.0 % (18/18)	N.A.	N.A.	100.0 % (80/80)
BTR_SJW_REG_COMP	100.0 % (22/22)	100.0 % (30/30)	100.0 % (42/42)	100.0 % (26/26)	N.A.	N.A.	100.0 % (120/120)
BTR_FD_PROP_FD_REG_COMP	100.0 % (26/26)	100.0 % (36/36)	100.0 % (48/48)	100.0 % (30/30)	N.A.	N.A.	100.0 % (140/140)
BTR_FD_PH1_FD_SLICE_1_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (40/40)
BTR_FD_PH1_FD_SLICE_2_REG_COMP	100.0 % (18/18)	100.0 % (24/24)	100.0 % (36/36)	100.0 % (22/22)	N.A.	N.A.	100.0 % (100/100)
BTR_FD_PH2_FD_SLICE_1_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (30/30)	100.0 % (18/18)	N.A.	N.A.	100.0 % (80/80)
BTR_FD_PH2_FD_SLICE_2_REG_COMP	100.0 % (10/10)	100.0 % (12/12)	100.0 % (24/24)	100.0 % (14/14)	N.A.	N.A.	100.0 % (60/60)
BTR_FD_BRP_FD_SLICE_1_REG_COMP	100.0 % (22/22)	100.0 % (30/30)	100.0 % (42/42)	100.0 % (26/26)	N.A.	N.A.	100.0 % (120/120)
BTR_FD_BRP_FD_SLICE_2_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (30/30)	100.0 % (18/18)	N.A.	N.A.	100.0 % (80/80)
BTR_FD_SJW_FD_REG_COMP	100.0 % (22/22)	100.0 % (30/30)	100.0 % (42/42)	100.0 % (26/26)	N.A.	N.A.	100.0 % (120/120)
EWL_EW_LIMIT_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
ERP_ERP_LIMIT_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
CTR_PRES_CTPV_SLICE_1_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
CTR_PRES_CTPV_SLICE_2_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (18/18)	100.0 % (10/10)	N.A.	N.A.	100.0 % (40/40)
CTR_PRES_PTX_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
CTR_PRES_PRX_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
CTR_PRES_ENORM_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
CTR_PRES_EFD_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (8/8)	N.A.	N.A.	100.0 % (33/33)
FILTER_A_MASK_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_A_VAL_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_B_MASK_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_B_VAL_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_C_MASK_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_C_VAL_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_RAN_LOW_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_RAN_HIGH_PRESENT_GEN_T	100.0 % (124/124)	100.0 % (174/174)	100.0 % (214/214)	100.0 % (128/128)	N.A.	N.A.	100.0 % (640/640)
FILTER_CONTROL_FANB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FANE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FAFB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FAFE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FBNB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FBNE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FBFB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FBFE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FCNB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FCNE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FCFB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FCFE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FRNB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FRNE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FRFB_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
FILTER_CONTROL_FRFE_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
RX_SETTINGS_RTSOP_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
RX_DATA_ACCESS_SIGNALLER_COMP	100.0 % (3/3)	100.0 % (2/2)	100.0 % (18/18)	100.0 % (3/3)	N.A.	N.A.	100.0 % (26/26)
TX_COMMAND_TXCE_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
TX_COMMAND_TXCR_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
TX_COMMAND_TXCA_REG_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (16/16)	100.0 % (5/5)	N.A.	N.A.	100.0 % (28/28)
TX_COMMAND_TXB1_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB2_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB3_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB4_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB5_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB6_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB7_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_COMMAND_TXB8_REG_COMP	100.0 % (6/6)	100.0 % (6/6)	100.0 % (16/16)	100.0 % (7/7)	N.A.	N.A.	100.0 % (35/35)
TX_PRIORITY_TXT1P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT2P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT3P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT4P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT5P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT6P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT7P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
TX_PRIORITY_TXT8P_REG_COMP	100.0 % (14/14)	100.0 % (18/18)	100.0 % (28/28)	100.0 % (15/15)	N.A.	N.A.	100.0 % (75/75)
SSP_CFG_SSP_OFFSET_REG_COMP	100.0 % (34/34)	100.0 % (48/48)	100.0 % (60/60)	100.0 % (38/38)	N.A.	N.A.	100.0 % (180/180)
SSP_CFG_SSP_SRC_REG_COMP	100.0 % (10/10)	100.0 % (12/12)	100.0 % (24/24)	100.0 % (14/14)	N.A.	N.A.	100.0 % (60/60)
FILTER_B_MASK_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_B_VAL_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_C_MASK_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_C_VAL_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_RAN_LOW_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_RAN_HIGH_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_A_MASK_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)
FILTER_A_VAL_PRESENT_GEN_F	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP	100.0 % (50/50)	100.0 % (48/48)	100.0 % (3270/3270)	100.0 % (16/16)	N.A.	100.0 % (73/73)	100.0 % (3457/3457)

	Evaluated to	Count	Threshold
Bin	True	154795	1
Bin	False	93330423	1

	Choice of	Count	Threshold
Bin	`"000000"`	272343	1

	Choice of	Count	Threshold
Bin	`"000001"`	560950	1

	Choice of	Count	Threshold
Bin	`"000010"`	18936935	1

	Choice of	Count	Threshold
Bin	`"000011"`	300359	1

	Choice of	Count	Threshold
Bin	`"000100"`	113048	1

	Choice of	Count	Threshold
Bin	`"000101"`	69913	1

	Choice of	Count	Threshold
Bin	`"000110"`	59251	1

	Choice of	Count	Threshold
Bin	`"000111"`	57815	1

	Choice of	Count	Threshold
Bin	`"001000"`	56867	1

	Choice of	Count	Threshold
Bin	`"001001"`	73625	1

	Choice of	Count	Threshold
Bin	`"001010"`	72779	1

	Choice of	Count	Threshold
Bin	`"001011"`	287184	1

	Choice of	Count	Threshold
Bin	`"001100"`	83154	1

	Choice of	Count	Threshold
Bin	`"001101"`	59255	1

	Choice of	Count	Threshold
Bin	`"001110"`	158067	1

	Choice of	Count	Threshold
Bin	`"001111"`	61413	1

	Choice of	Count	Threshold
Bin	`"010000"`	58528	1

	Choice of	Count	Threshold
Bin	`"010001"`	56033	1

	Choice of	Count	Threshold
Bin	`"010010"`	56032	1

	Choice of	Count	Threshold
Bin	`"010011"`	56032	1

	Choice of	Count	Threshold
Bin	`"010100"`	53637	1

	Choice of	Count	Threshold
Bin	`"010101"`	140	1

	Choice of	Count	Threshold
Bin	`"010110"`	140	1

	Choice of	Count	Threshold
Bin	`"010111"`	40136	1

	Choice of	Count	Threshold
Bin	`"011000"`	25427	1

	Choice of	Count	Threshold
Bin	`"011001"`	25264	1

	Choice of	Count	Threshold
Bin	`"011010"`	26814	1

	Choice of	Count	Threshold
Bin	`"011011"`	219955	1

	Choice of	Count	Threshold
Bin	`"011100"`	35576	1

	Choice of	Count	Threshold
Bin	`"011101"`	86567	1

	Choice of	Count	Threshold
Bin	`"011110"`	8132	1

	Choice of	Count	Threshold
Bin	`"011111"`	3572	1

	Choice of	Count	Threshold
Bin	`"100000"`	11866	1

	Choice of	Count	Threshold
Bin	`"100001"`	2359	1

	Choice of	Count	Threshold
Bin	`"100010"`	2268	1

	Choice of	Count	Threshold
Bin	`"100011"`	33479780	1

	Choice of	Count	Threshold
Bin	`"100100"`	90	1

	Choice of	Count	Threshold
Bin	`"100101"`	7870	1

	Choice of	Count	Threshold
Bin	`"100110"`	7870	1

	Choice of	Count	Threshold
Bin	`others`	546717377	1

	Evaluated to	Count	Threshold
Bin	True	17945	1
Bin	False	62732167	1

	Evaluated to	Count	Threshold
Bin	True	31360647	1
Bin	False	31371520	1

	Evaluated to	Count	Threshold
Bin	True	19060625	1
Bin	False	12300022	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

W_DATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

READ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

LOCK_1

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

LOCK_2

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CONTROL_REGISTERS_IN

	Element	From	To	Threshold	Excluded due to
Bin	DEVICE_ID_DEVICE_ID(15)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(14)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(13)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(12)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(11)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(10)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(9)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(8)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(7)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(6)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(5)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(4)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(3)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(2)	1	0	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(1)	0	1	1	Exclude file
Bin	DEVICE_ID_DEVICE_ID(0)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MINOR(2)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MINOR(0)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(7)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(6)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(5)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(4)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(3)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(2)	0	1	1	Exclude file
Bin	VERSION_VER_MAJOR(1)	1	0	1	Exclude file
Bin	VERSION_VER_MAJOR(0)	0	1	1	Exclude file
Bin	STATUS_STRGS	1	0	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	0	1	1	Exclude file
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	0	1	1	Exclude file
Bin	TXTB_INFO_TXT_BUFFER_COUNT(0)	0	1	1	Exclude file
Bin	TS_INFO_TS_BITS(5)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(4)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(3)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(2)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(1)	1	0	1	Exclude file
Bin	TS_INFO_TS_BITS(0)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(31)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(30)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(29)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(28)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(27)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(26)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(25)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(24)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(23)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(22)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(21)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(20)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(19)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(18)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(17)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(16)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(15)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(14)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(13)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(12)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(11)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(10)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(9)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(8)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(7)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(6)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(5)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(4)	0	1	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(3)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(2)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(1)	1	0	1	Exclude file
Bin	YOLO_REG_YOLO_VAL(0)	1	0	1	Exclude file

Covered toggles:

Port:

R_DATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5426	1
Bin	(31)	1	0	7027	1
Bin	(30)	0	1	5757	1
Bin	(30)	1	0	7358	1
Bin	(29)	0	1	5598	1
Bin	(29)	1	0	7199	1
Bin	(28)	0	1	11395	1
Bin	(28)	1	0	12996	1
Bin	(27)	0	1	12765	1
Bin	(27)	1	0	14366	1
Bin	(26)	0	1	11909	1
Bin	(26)	1	0	13510	1
Bin	(25)	0	1	19582	1
Bin	(25)	1	0	21183	1
Bin	(24)	0	1	16278	1
Bin	(24)	1	0	17879	1
Bin	(23)	0	1	20501	1
Bin	(23)	1	0	22102	1
Bin	(22)	0	1	28980	1
Bin	(22)	1	0	30580	1
Bin	(21)	0	1	17139	1
Bin	(21)	1	0	18740	1
Bin	(20)	0	1	21326	1
Bin	(20)	1	0	22927	1
Bin	(19)	0	1	22881	1
Bin	(19)	1	0	24482	1
Bin	(18)	0	1	73786	1
Bin	(18)	1	0	75387	1
Bin	(17)	0	1	62996	1
Bin	(17)	1	0	64597	1
Bin	(16)	0	1	62083	1
Bin	(16)	1	0	63675	1
Bin	(15)	0	1	31129	1
Bin	(15)	1	0	32721	1
Bin	(14)	0	1	21815	1
Bin	(14)	1	0	23416	1
Bin	(13)	0	1	25181	1
Bin	(13)	1	0	26782	1
Bin	(12)	0	1	32210	1
Bin	(12)	1	0	33811	1
Bin	(11)	0	1	32316	1
Bin	(11)	1	0	33917	1
Bin	(10)	0	1	34174	1
Bin	(10)	1	0	35775	1
Bin	(9)	0	1	36095	1
Bin	(9)	1	0	37694	1
Bin	(8)	0	1	33742	1
Bin	(8)	1	0	35342	1
Bin	(7)	0	1	58072	1
Bin	(7)	1	0	59673	1
Bin	(6)	0	1	56476	1
Bin	(6)	1	0	58068	1
Bin	(5)	0	1	65188	1
Bin	(5)	1	0	66780	1
Bin	(4)	0	1	60882	1
Bin	(4)	1	0	62481	1
Bin	(3)	0	1	75407	1
Bin	(3)	1	0	77008	1
Bin	(2)	0	1	60839	1
Bin	(2)	1	0	62439	1
Bin	(1)	0	1	37608	1
Bin	(1)	1	0	39208	1
Bin	(0)	0	1	49521	1
Bin	(0)	1	0	51121	1

Port:

CONTROL_REGISTERS_OUT

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32879	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
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Bin	CTR_PRES_PTX	0	1	19125	1
Bin	CTR_PRES_PTX	1	0	44590	1
Bin	CTR_PRES_PRX	0	1	19522	1
Bin	CTR_PRES_PRX	1	0	44590	1
Bin	CTR_PRES_ENORM	0	1	6369	1
Bin	CTR_PRES_ENORM	1	0	44590	1
Bin	CTR_PRES_EFD	0	1	6369	1
Bin	CTR_PRES_EFD	1	0	44590	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	389	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	1990	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	349	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	1950	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	339	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	1940	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	1966	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	378	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	1979	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	395	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	1996	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	1967	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	383	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	1984	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	368	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	1969	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	411	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	2012	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	97	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1698	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	82	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1683	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	94	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	1695	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	118	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	1719	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	131	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	1732	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	1707	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	249	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	1850	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	250	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	1851	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	252	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	1853	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	281	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	1882	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	265	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	1866	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	278	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	1879	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	239	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	1840	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	267	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	1868	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	280	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	1881	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	242	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	1843	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	270	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	1871	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	816	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2417	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	793	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	803	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2404	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	791	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2392	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	805	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2406	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2365	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	772	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2373	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	763	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2364	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2433	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	836	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2437	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	1996	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	429	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	2030	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	2004	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2016	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	413	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	2014	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	1998	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	1999	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	2003	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	1995	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2006	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	2022	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	396	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	1997	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	423	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	2024	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	378	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	1979	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2011	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1697	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	80	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1681	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	102	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1703	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1692	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	82	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1683	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	105	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1706	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	89	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1690	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	15	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1616	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	33	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1634	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1623	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	36	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1637	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1636	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	34	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1635	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1664	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	66	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1667	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1672	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	65	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1666	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1663	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	68	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1669	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	59	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1660	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	186	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1787	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	191	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1792	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	195	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1796	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1801	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	204	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1805	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1799	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	202	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1803	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	213	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1814	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	212	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1813	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1693	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	111	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1712	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1692	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	1704	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1702	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	97	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1698	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1705	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	95	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1696	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	102	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1703	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1707	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1701	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1708	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	94	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	94	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1695	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	86	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1687	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1701	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	104	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1705	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	93	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1694	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	98	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1699	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	88	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1689	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	97	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1698	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1680	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	87	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1688	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1623	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	17	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1618	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	30	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1631	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	21	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1622	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	37	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1638	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1635	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1664	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1672	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1670	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1663	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1668	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1667	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	58	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1659	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1785	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	182	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1783	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	199	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1800	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1794	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1791	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	207	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1808	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	213	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1814	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1799	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	203	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1804	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	214	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1815	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	103	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1704	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1701	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1700	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	86	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1687	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	1705	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	102	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1703	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1696	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1697	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1706	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1711	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1699	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1709	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1696	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1602	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51790	1
Bin	RX_DATA_READ	1	0	53391	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25076	1
Bin	TX_COMMAND_TXCR	0	1	21387	1
Bin	TX_COMMAND_TXCR	1	0	25076	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25076	1
Bin	TX_COMMAND_TXB1	0	1	6553	1
Bin	TX_COMMAND_TXB1	1	0	8149	1
Bin	TX_COMMAND_TXB2	0	1	5587	1
Bin	TX_COMMAND_TXB2	1	0	7188	1
Bin	TX_COMMAND_TXB3	0	1	332	1
Bin	TX_COMMAND_TXB3	1	0	1933	1
Bin	TX_COMMAND_TXB4	0	1	345	1
Bin	TX_COMMAND_TXB4	1	0	1946	1
Bin	TX_COMMAND_TXB5	0	1	91	1
Bin	TX_COMMAND_TXB5	1	0	1692	1
Bin	TX_COMMAND_TXB6	0	1	73	1
Bin	TX_COMMAND_TXB6	1	0	1674	1
Bin	TX_COMMAND_TXB7	0	1	87	1
Bin	TX_COMMAND_TXB7	1	0	1688	1
Bin	TX_COMMAND_TXB8	0	1	74	1
Bin	TX_COMMAND_TXB8	1	0	1675	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	105	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1706	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1723	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	122	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	94	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1695	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	131	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1732	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	124	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1725	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	72	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1673	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	103	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1704	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	96	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1697	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	77	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1678	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	91	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1692	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	99	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1700	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	33	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1634	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1630	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	28	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1629	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	33	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1634	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	26	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1627	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	27	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1628	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	31	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	28	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1629	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	24	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1625	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	23	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1624	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	48	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1649	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	50	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1651	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4306	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2716	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	535	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2135	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2902	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1313	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3997	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	815	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2405	1

Port:

CONTROL_REGISTERS_IN

	Element	From	To	Count	Threshold
Bin	DEVICE_ID_DEVICE_ID(15)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(14)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(13)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(12)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(11)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(10)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(9)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(8)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(7)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(6)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(5)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(4)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(3)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(2)	0	1	1601	1
Bin	DEVICE_ID_DEVICE_ID(1)	1	0	1601	1
Bin	DEVICE_ID_DEVICE_ID(0)	0	1	1601	1
Bin	VERSION_VER_MINOR(7)	1	0	1601	1
Bin	VERSION_VER_MINOR(6)	1	0	1601	1
Bin	VERSION_VER_MINOR(5)	1	0	1601	1
Bin	VERSION_VER_MINOR(4)	1	0	1601	1
Bin	VERSION_VER_MINOR(3)	1	0	1601	1
Bin	VERSION_VER_MINOR(2)	0	1	1601	1
Bin	VERSION_VER_MINOR(1)	0	1	1601	1
Bin	VERSION_VER_MINOR(0)	0	1	1601	1
Bin	VERSION_VER_MAJOR(7)	1	0	1601	1
Bin	VERSION_VER_MAJOR(6)	1	0	1601	1
Bin	VERSION_VER_MAJOR(5)	1	0	1601	1
Bin	VERSION_VER_MAJOR(4)	1	0	1601	1
Bin	VERSION_VER_MAJOR(3)	1	0	1601	1
Bin	VERSION_VER_MAJOR(2)	1	0	1601	1
Bin	VERSION_VER_MAJOR(1)	0	1	1601	1
Bin	VERSION_VER_MAJOR(0)	1	0	1601	1
Bin	STATUS_RXNE	0	1	9001	1
Bin	STATUS_RXNE	1	0	8999	1
Bin	STATUS_DOR	0	1	31	1
Bin	STATUS_DOR	1	0	1632	1
Bin	STATUS_TXNF	0	1	2480	1
Bin	STATUS_TXNF	1	0	2480	1
Bin	STATUS_EFT	0	1	27135	1
Bin	STATUS_EFT	1	0	28729	1
Bin	STATUS_RXS	0	1	30908	1
Bin	STATUS_RXS	1	0	32502	1
Bin	STATUS_TXS	0	1	20317	1
Bin	STATUS_TXS	1	0	21917	1
Bin	STATUS_EWL	0	1	778	1
Bin	STATUS_EWL	1	0	2378	1
Bin	STATUS_IDLE	0	1	51454	1
Bin	STATUS_IDLE	1	0	51462	1
Bin	STATUS_PEXS	0	1	75	1
Bin	STATUS_PEXS	1	0	1676	1
Bin	STATUS_RXPE	0	1	9	1
Bin	STATUS_RXPE	1	0	1610	1
Bin	STATUS_TXPE	0	1	317	1
Bin	STATUS_TXPE	1	0	1918	1
Bin	STATUS_TXDPE	0	1	44	1
Bin	STATUS_TXDPE	1	0	1645	1
Bin	STATUS_STCNT	0	1	660	1
Bin	STATUS_STCNT	1	0	941	1
Bin	STATUS_STRGS	0	1	1601	1
Bin	STATUS_SPRT	0	1	660	1
Bin	STATUS_SPRT	1	0	941	1
Bin	INT_STAT_RXI	0	1	808	1
Bin	INT_STAT_RXI	1	0	2407	1
Bin	INT_STAT_TXI	0	1	1215	1
Bin	INT_STAT_TXI	1	0	2812	1
Bin	INT_STAT_EWLI	0	1	587	1
Bin	INT_STAT_EWLI	1	0	2187	1
Bin	INT_STAT_DOI	0	1	21	1
Bin	INT_STAT_DOI	1	0	1622	1
Bin	INT_STAT_FCSI	0	1	3304	1
Bin	INT_STAT_FCSI	1	0	4893	1
Bin	INT_STAT_ALI	0	1	99	1
Bin	INT_STAT_ALI	1	0	1698	1
Bin	INT_STAT_BEI	0	1	1417	1
Bin	INT_STAT_BEI	1	0	3010	1
Bin	INT_STAT_OFI	0	1	152	1
Bin	INT_STAT_OFI	1	0	1753	1
Bin	INT_STAT_RXFI	0	1	20	1
Bin	INT_STAT_RXFI	1	0	1621	1
Bin	INT_STAT_BSI	0	1	1299	1
Bin	INT_STAT_BSI	1	0	2894	1
Bin	INT_STAT_RBNEI	0	1	936	1
Bin	INT_STAT_RBNEI	1	0	2535	1
Bin	INT_STAT_TXBHCI	0	1	1680	1
Bin	INT_STAT_TXBHCI	1	0	3276	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	1667	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	1631	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	1651	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	1621	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	1616	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	1616	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	22	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	1623	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	20	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	1621	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	5	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	1606	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	1611	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	1611	1
Bin	FAULT_STATE_ERA	0	1	8426	1
Bin	FAULT_STATE_ERA	1	0	8415	1
Bin	FAULT_STATE_ERP	0	1	761	1
Bin	FAULT_STATE_ERP	1	0	2362	1
Bin	FAULT_STATE_BOF	0	1	8227	1
Bin	FAULT_STATE_BOF	1	0	8238	1
Bin	REC_REC_VAL(8)	0	1	126	1
Bin	REC_REC_VAL(8)	1	0	1727	1
Bin	REC_REC_VAL(7)	0	1	344	1
Bin	REC_REC_VAL(7)	1	0	1945	1
Bin	REC_REC_VAL(6)	0	1	262	1
Bin	REC_REC_VAL(6)	1	0	1860	1
Bin	REC_REC_VAL(5)	0	1	343	1
Bin	REC_REC_VAL(5)	1	0	1943	1
Bin	REC_REC_VAL(4)	0	1	501	1
Bin	REC_REC_VAL(4)	1	0	2101	1
Bin	REC_REC_VAL(3)	0	1	680	1
Bin	REC_REC_VAL(3)	1	0	2280	1
Bin	REC_REC_VAL(2)	0	1	639	1
Bin	REC_REC_VAL(2)	1	0	2240	1
Bin	REC_REC_VAL(1)	0	1	1198	1
Bin	REC_REC_VAL(1)	1	0	2799	1
Bin	REC_REC_VAL(0)	0	1	11242	1
Bin	REC_REC_VAL(0)	1	0	12836	1
Bin	TEC_TEC_VAL(8)	0	1	246	1
Bin	TEC_TEC_VAL(8)	1	0	1847	1
Bin	TEC_TEC_VAL(7)	0	1	506	1
Bin	TEC_TEC_VAL(7)	1	0	2107	1
Bin	TEC_TEC_VAL(6)	0	1	504	1
Bin	TEC_TEC_VAL(6)	1	0	2105	1
Bin	TEC_TEC_VAL(5)	0	1	787	1
Bin	TEC_TEC_VAL(5)	1	0	2388	1
Bin	TEC_TEC_VAL(4)	0	1	1957	1
Bin	TEC_TEC_VAL(4)	1	0	3557	1
Bin	TEC_TEC_VAL(3)	0	1	12521	1
Bin	TEC_TEC_VAL(3)	1	0	14122	1
Bin	TEC_TEC_VAL(2)	0	1	2978	1
Bin	TEC_TEC_VAL(2)	1	0	4579	1
Bin	TEC_TEC_VAL(1)	0	1	3314	1
Bin	TEC_TEC_VAL(1)	1	0	4915	1
Bin	TEC_TEC_VAL(0)	0	1	3548	1
Bin	TEC_TEC_VAL(0)	1	0	5149	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	0	1	67	1
Bin	ERR_NORM_ERR_NORM_VAL(15)	1	0	1665	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	0	1	65	1
Bin	ERR_NORM_ERR_NORM_VAL(14)	1	0	1663	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	0	1	66	1
Bin	ERR_NORM_ERR_NORM_VAL(13)	1	0	1662	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	0	1	61	1
Bin	ERR_NORM_ERR_NORM_VAL(12)	1	0	1659	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	0	1	71	1
Bin	ERR_NORM_ERR_NORM_VAL(11)	1	0	1670	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	0	1	67	1
Bin	ERR_NORM_ERR_NORM_VAL(10)	1	0	1665	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	0	1	54	1
Bin	ERR_NORM_ERR_NORM_VAL(9)	1	0	1654	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	0	1	71	1
Bin	ERR_NORM_ERR_NORM_VAL(8)	1	0	1668	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	0	1	83	1
Bin	ERR_NORM_ERR_NORM_VAL(7)	1	0	1682	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	0	1	97	1
Bin	ERR_NORM_ERR_NORM_VAL(6)	1	0	1695	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	0	1	150	1
Bin	ERR_NORM_ERR_NORM_VAL(5)	1	0	1747	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	0	1	271	1
Bin	ERR_NORM_ERR_NORM_VAL(4)	1	0	1869	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	0	1	605	1
Bin	ERR_NORM_ERR_NORM_VAL(3)	1	0	2200	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	0	1	1369	1
Bin	ERR_NORM_ERR_NORM_VAL(2)	1	0	2967	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	0	1	3083	1
Bin	ERR_NORM_ERR_NORM_VAL(1)	1	0	4677	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	0	1	11506	1
Bin	ERR_NORM_ERR_NORM_VAL(0)	1	0	13100	1
Bin	ERR_FD_ERR_FD_VAL(15)	0	1	59	1
Bin	ERR_FD_ERR_FD_VAL(15)	1	0	1657	1
Bin	ERR_FD_ERR_FD_VAL(14)	0	1	68	1
Bin	ERR_FD_ERR_FD_VAL(14)	1	0	1666	1
Bin	ERR_FD_ERR_FD_VAL(13)	0	1	70	1
Bin	ERR_FD_ERR_FD_VAL(13)	1	0	1669	1
Bin	ERR_FD_ERR_FD_VAL(12)	0	1	66	1
Bin	ERR_FD_ERR_FD_VAL(12)	1	0	1665	1
Bin	ERR_FD_ERR_FD_VAL(11)	0	1	63	1
Bin	ERR_FD_ERR_FD_VAL(11)	1	0	1663	1
Bin	ERR_FD_ERR_FD_VAL(10)	0	1	68	1
Bin	ERR_FD_ERR_FD_VAL(10)	1	0	1666	1
Bin	ERR_FD_ERR_FD_VAL(9)	0	1	77	1
Bin	ERR_FD_ERR_FD_VAL(9)	1	0	1674	1
Bin	ERR_FD_ERR_FD_VAL(8)	0	1	90	1
Bin	ERR_FD_ERR_FD_VAL(8)	1	0	1688	1
Bin	ERR_FD_ERR_FD_VAL(7)	0	1	99	1
Bin	ERR_FD_ERR_FD_VAL(7)	1	0	1698	1
Bin	ERR_FD_ERR_FD_VAL(6)	0	1	126	1
Bin	ERR_FD_ERR_FD_VAL(6)	1	0	1723	1
Bin	ERR_FD_ERR_FD_VAL(5)	0	1	212	1
Bin	ERR_FD_ERR_FD_VAL(5)	1	0	1809	1
Bin	ERR_FD_ERR_FD_VAL(4)	0	1	363	1
Bin	ERR_FD_ERR_FD_VAL(4)	1	0	1962	1
Bin	ERR_FD_ERR_FD_VAL(3)	0	1	679	1
Bin	ERR_FD_ERR_FD_VAL(3)	1	0	2278	1
Bin	ERR_FD_ERR_FD_VAL(2)	0	1	1288	1
Bin	ERR_FD_ERR_FD_VAL(2)	1	0	2888	1
Bin	ERR_FD_ERR_FD_VAL(1)	0	1	2512	1
Bin	ERR_FD_ERR_FD_VAL(1)	1	0	4112	1
Bin	ERR_FD_ERR_FD_VAL(0)	0	1	5598	1
Bin	ERR_FD_ERR_FD_VAL(0)	1	0	7196	1
Bin	FILTER_STATUS_SFA	0	1	660	1
Bin	FILTER_STATUS_SFA	1	0	941	1
Bin	FILTER_STATUS_SFB	0	1	165	1
Bin	FILTER_STATUS_SFB	1	0	1436	1
Bin	FILTER_STATUS_SFC	0	1	165	1
Bin	FILTER_STATUS_SFC	1	0	1436	1
Bin	FILTER_STATUS_SFR	0	1	165	1
Bin	FILTER_STATUS_SFR	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	0	1	165	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(12)	1	0	1436	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(11)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(10)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(9)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(8)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	0	1	495	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(7)	1	0	1106	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(6)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	0	1	941	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(5)	1	0	660	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(4)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(3)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(2)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(1)	1	0	1601	1
Bin	RX_MEM_INFO_RX_BUFF_SIZE(0)	1	0	1601	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	0	1	1239	1
Bin	RX_MEM_INFO_RX_MEM_FREE(12)	1	0	49652	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	0	1	1076	1
Bin	RX_MEM_INFO_RX_MEM_FREE(11)	1	0	49819	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	0	1	1083	1
Bin	RX_MEM_INFO_RX_MEM_FREE(10)	1	0	49826	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	0	1	1097	1
Bin	RX_MEM_INFO_RX_MEM_FREE(9)	1	0	49840	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	0	1	1125	1
Bin	RX_MEM_INFO_RX_MEM_FREE(8)	1	0	49868	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	0	1	4532	1
Bin	RX_MEM_INFO_RX_MEM_FREE(7)	1	0	30351	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	0	1	4159	1
Bin	RX_MEM_INFO_RX_MEM_FREE(6)	1	0	30968	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	0	1	8826	1
Bin	RX_MEM_INFO_RX_MEM_FREE(5)	1	0	8547	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	0	1	8414	1
Bin	RX_MEM_INFO_RX_MEM_FREE(4)	1	0	10013	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	0	1	10005	1
Bin	RX_MEM_INFO_RX_MEM_FREE(3)	1	0	11604	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	0	1	12209	1
Bin	RX_MEM_INFO_RX_MEM_FREE(2)	1	0	13808	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	0	1	16073	1
Bin	RX_MEM_INFO_RX_MEM_FREE(1)	1	0	17674	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	0	1	27447	1
Bin	RX_MEM_INFO_RX_MEM_FREE(0)	1	0	29048	1
Bin	RX_POINTERS_RX_WPP(11)	0	1	5	1
Bin	RX_POINTERS_RX_WPP(11)	1	0	11743	1
Bin	RX_POINTERS_RX_WPP(10)	0	1	11	1
Bin	RX_POINTERS_RX_WPP(10)	1	0	11749	1
Bin	RX_POINTERS_RX_WPP(9)	0	1	23	1
Bin	RX_POINTERS_RX_WPP(9)	1	0	11761	1
Bin	RX_POINTERS_RX_WPP(8)	0	1	45	1
Bin	RX_POINTERS_RX_WPP(8)	1	0	11783	1
Bin	RX_POINTERS_RX_WPP(7)	0	1	89	1
Bin	RX_POINTERS_RX_WPP(7)	1	0	11827	1
Bin	RX_POINTERS_RX_WPP(6)	0	1	311	1
Bin	RX_POINTERS_RX_WPP(6)	1	0	6965	1
Bin	RX_POINTERS_RX_WPP(5)	0	1	669	1
Bin	RX_POINTERS_RX_WPP(5)	1	0	7323	1
Bin	RX_POINTERS_RX_WPP(4)	0	1	1971	1
Bin	RX_POINTERS_RX_WPP(4)	1	0	3572	1
Bin	RX_POINTERS_RX_WPP(3)	0	1	3777	1
Bin	RX_POINTERS_RX_WPP(3)	1	0	5378	1
Bin	RX_POINTERS_RX_WPP(2)	0	1	6171	1
Bin	RX_POINTERS_RX_WPP(2)	1	0	7770	1
Bin	RX_POINTERS_RX_WPP(1)	0	1	1881	1
Bin	RX_POINTERS_RX_WPP(1)	1	0	3482	1
Bin	RX_POINTERS_RX_WPP(0)	0	1	1735	1
Bin	RX_POINTERS_RX_WPP(0)	1	0	3336	1
Bin	RX_POINTERS_RX_RPP(11)	0	1	2	1
Bin	RX_POINTERS_RX_RPP(11)	1	0	41393	1
Bin	RX_POINTERS_RX_RPP(10)	0	1	5	1
Bin	RX_POINTERS_RX_RPP(10)	1	0	41396	1
Bin	RX_POINTERS_RX_RPP(9)	0	1	11	1
Bin	RX_POINTERS_RX_RPP(9)	1	0	41402	1
Bin	RX_POINTERS_RX_RPP(8)	0	1	21	1
Bin	RX_POINTERS_RX_RPP(8)	1	0	41412	1
Bin	RX_POINTERS_RX_RPP(7)	0	1	41	1
Bin	RX_POINTERS_RX_RPP(7)	1	0	41432	1
Bin	RX_POINTERS_RX_RPP(6)	0	1	205	1
Bin	RX_POINTERS_RX_RPP(6)	1	0	23531	1
Bin	RX_POINTERS_RX_RPP(5)	0	1	443	1
Bin	RX_POINTERS_RX_RPP(5)	1	0	23769	1
Bin	RX_POINTERS_RX_RPP(4)	0	1	1578	1
Bin	RX_POINTERS_RX_RPP(4)	1	0	3179	1
Bin	RX_POINTERS_RX_RPP(3)	0	1	3184	1
Bin	RX_POINTERS_RX_RPP(3)	1	0	4785	1
Bin	RX_POINTERS_RX_RPP(2)	0	1	6633	1
Bin	RX_POINTERS_RX_RPP(2)	1	0	8234	1
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Bin	TXTB_INFO_TXT_BUFFER_COUNT(1)	1	0	660	1
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Bin	TRV_DELAY_TRV_DELAY_VALUE(0)	1	0	1657	1
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Bin	RX_FR_CTR_RX_FR_CTR_VAL(29)	0	1	51	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(29)	1	0	1650	1
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Bin	RX_FR_CTR_RX_FR_CTR_VAL(28)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(27)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(26)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(25)	1	0	1647	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(24)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(23)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	0	1	49	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(22)	1	0	1650	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(21)	1	0	1653	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(20)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(19)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(18)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	0	1	55	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(17)	1	0	1654	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(16)	1	0	1653	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(15)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	0	1	47	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(14)	1	0	1647	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	0	1	57	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(13)	1	0	1656	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	0	1	61	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(12)	1	0	1660	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	0	1	50	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(11)	1	0	1648	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	0	1	54	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(10)	1	0	1652	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	0	1	53	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(9)	1	0	1651	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	0	1	66	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(8)	1	0	1665	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	0	1	87	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(7)	1	0	1686	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	0	1	113	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(6)	1	0	1712	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	0	1	215	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(5)	1	0	1814	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	0	1	353	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(4)	1	0	1953	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	0	1	747	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(3)	1	0	2345	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	0	1	1493	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(2)	1	0	3092	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	0	1	2963	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(1)	1	0	4561	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	0	1	5921	1
Bin	RX_FR_CTR_RX_FR_CTR_VAL(0)	1	0	7521	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	0	1	101	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(31)	1	0	1702	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(30)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	0	1	110	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(29)	1	0	1711	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(28)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(27)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	0	1	101	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(26)	1	0	1702	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(25)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	0	1	97	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(24)	1	0	1698	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(23)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	0	1	100	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(22)	1	0	1701	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(21)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(20)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	0	1	97	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(19)	1	0	1698	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(18)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(17)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	0	1	111	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(16)	1	0	1712	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	0	1	102	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(15)	1	0	1703	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	0	1	105	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(14)	1	0	1706	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	0	1	91	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(13)	1	0	1692	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	0	1	99	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(12)	1	0	1700	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	0	1	98	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(11)	1	0	1699	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	0	1	96	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(10)	1	0	1697	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	0	1	106	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(9)	1	0	1707	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	0	1	104	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(8)	1	0	1705	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	0	1	103	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(7)	1	0	1704	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	0	1	108	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(6)	1	0	1709	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	0	1	109	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(5)	1	0	1710	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	0	1	152	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(4)	1	0	1753	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	0	1	258	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(3)	1	0	1859	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	0	1	619	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(2)	1	0	2220	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	0	1	1052	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(1)	1	0	2653	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	0	1	2203	1
Bin	TX_FR_CTR_TX_FR_CTR_VAL(0)	1	0	3804	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	0	1	33452	1
Bin	DEBUG_REGISTER_STUFF_COUNT(2)	1	0	35053	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	0	1	70940	1
Bin	DEBUG_REGISTER_STUFF_COUNT(1)	1	0	72538	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	0	1	141315	1
Bin	DEBUG_REGISTER_STUFF_COUNT(0)	1	0	142914	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	0	1	117682	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(2)	1	0	119283	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	0	1	242662	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(1)	1	0	244257	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	0	1	484884	1
Bin	DEBUG_REGISTER_DESTUFF_COUNT(0)	1	0	486480	1
Bin	DEBUG_REGISTER_PC_ARB	0	1	55723	1
Bin	DEBUG_REGISTER_PC_ARB	1	0	57324	1
Bin	DEBUG_REGISTER_PC_CON	0	1	50970	1
Bin	DEBUG_REGISTER_PC_CON	1	0	52571	1
Bin	DEBUG_REGISTER_PC_DAT	0	1	36820	1
Bin	DEBUG_REGISTER_PC_DAT	1	0	38421	1
Bin	DEBUG_REGISTER_PC_STC	0	1	13502	1
Bin	DEBUG_REGISTER_PC_STC	1	0	15103	1
Bin	DEBUG_REGISTER_PC_CRC	0	1	31213	1
Bin	DEBUG_REGISTER_PC_CRC	1	0	32814	1
Bin	DEBUG_REGISTER_PC_CRCD	0	1	29735	1
Bin	DEBUG_REGISTER_PC_CRCD	1	0	31336	1
Bin	DEBUG_REGISTER_PC_ACK	0	1	29588	1
Bin	DEBUG_REGISTER_PC_ACK	1	0	31189	1
Bin	DEBUG_REGISTER_PC_ACKD	0	1	28165	1
Bin	DEBUG_REGISTER_PC_ACKD	1	0	29766	1
Bin	DEBUG_REGISTER_PC_EOF	0	1	27273	1
Bin	DEBUG_REGISTER_PC_EOF	1	0	28874	1
Bin	DEBUG_REGISTER_PC_INT	0	1	51716	1
Bin	DEBUG_REGISTER_PC_INT	1	0	53316	1
Bin	DEBUG_REGISTER_PC_SUSP	0	1	2779	1
Bin	DEBUG_REGISTER_PC_SUSP	1	0	4380	1
Bin	DEBUG_REGISTER_PC_OVR	0	1	529	1
Bin	DEBUG_REGISTER_PC_OVR	1	0	2130	1
Bin	DEBUG_REGISTER_PC_SOF	0	1	24924	1
Bin	DEBUG_REGISTER_PC_SOF	1	0	26525	1
Bin	YOLO_REG_YOLO_VAL(31)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(30)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(29)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(28)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(27)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(26)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(25)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(24)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(23)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(22)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(21)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(20)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(19)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(18)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(17)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(16)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(15)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(14)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(13)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(12)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(11)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(10)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(9)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(8)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(7)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(6)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(5)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(4)	1	0	1601	1
Bin	YOLO_REG_YOLO_VAL(3)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(2)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(1)	0	1	1601	1
Bin	YOLO_REG_YOLO_VAL(0)	0	1	1601	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	0	1	43	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(31)	1	0	1643	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	0	1	68	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(30)	1	0	1657	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	0	1	60	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(29)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	0	1	56	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(28)	1	0	1650	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	0	1	60	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(27)	1	0	1653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	0	1	68	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(26)	1	0	1661	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	0	1	61	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(25)	1	0	1654	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	0	1	65	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(24)	1	0	1656	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	0	1	80	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(23)	1	0	1664	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	0	1	115	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(22)	1	0	1681	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	0	1	155	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(21)	1	0	1721	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	0	1	253	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(20)	1	0	1804	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	0	1	540	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(19)	1	0	1991	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	0	1	1001	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(18)	1	0	2479	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	0	1	2081	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(17)	1	0	3417	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	0	1	4185	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(16)	1	0	5438	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	0	1	8268	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(15)	1	0	9537	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	0	1	16605	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(14)	1	0	17754	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	0	1	33247	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(13)	1	0	34309	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	0	1	66551	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(12)	1	0	67500	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	0	1	133055	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(11)	1	0	133977	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	0	1	266193	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(10)	1	0	266979	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	0	1	532264	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(9)	1	0	533095	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	0	1	1064501	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(8)	1	0	1065312	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	0	1	2128946	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(7)	1	0	2129759	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	0	1	4257855	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(6)	1	0	4258653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	0	1	8515658	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(5)	1	0	8516449	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	0	1	17031259	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(4)	1	0	17032062	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	0	1	34062445	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(3)	1	0	34063255	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	0	1	68124856	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(2)	1	0	68125653	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	0	1	136249666	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(1)	1	0	136250439	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	0	1	272499261	1
Bin	TIMESTAMP_LOW_TIMESTAMP_LOW(0)	1	0	272500058	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	0	1	20	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)	1	0	1618	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	0	1	64	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	0	1	62	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)	1	0	1654	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	0	1	73	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)	1	0	1664	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	0	1	70	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)	1	0	1661	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)	1	0	1662	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	0	1	67	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)	1	0	1658	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	0	1	77	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)	1	0	1669	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	0	1	69	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	0	1	70	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)	1	0	1664	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	0	1	72	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)	1	0	1657	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	0	1	74	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	0	1	59	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)	1	0	1655	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	0	1	73	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)	1	0	1663	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	0	1	77	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)	1	0	1665	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)	1	0	1652	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	0	1	63	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	0	1	61	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)	1	0	1653	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	0	1	62	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)	1	0	1651	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	0	1	66	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)	1	0	1659	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	0	1	68	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)	1	0	1660	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	0	1	65	1
Bin	TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)	1	0	1658	1

Signal:

REG_SEL

	Element	From	To	Count	Threshold
Bin	(38)	0	1	3935	1
Bin	(38)	1	0	4326930	1
Bin	(37)	0	1	3935	1
Bin	(37)	1	0	4322988	1
Bin	(36)	0	1	45	1
Bin	(36)	1	0	4319278	1
Bin	(35)	0	1	9995742	1
Bin	(35)	1	0	28318027	1
Bin	(34)	0	1	1122	1
Bin	(34)	1	0	4402309	1
Bin	(33)	0	1	1122	1
Bin	(33)	1	0	4332425	1
Bin	(32)	0	1	3459	1
Bin	(32)	1	0	38429134	1
Bin	(31)	0	1	537	1
Bin	(31)	1	0	38432056	1
Bin	(30)	0	1	4066	1
Bin	(30)	1	0	38428527	1
Bin	(29)	0	1	27961	1
Bin	(29)	1	0	38404632	1
Bin	(28)	0	1	8416	1
Bin	(28)	1	0	38424177	1
Bin	(27)	0	1	51790	1
Bin	(27)	1	0	38380803	1
Bin	(26)	0	1	13208	1
Bin	(26)	1	0	38419385	1
Bin	(25)	0	1	12403	1
Bin	(25)	1	0	38395384	1
Bin	(24)	0	1	12403	1
Bin	(24)	1	0	23753874	1
Bin	(23)	0	1	20068	1
Bin	(23)	1	0	38412525	1
Bin	(22)	0	1	70	1
Bin	(22)	1	0	34800289	1
Bin	(21)	0	1	70	1
Bin	(21)	1	0	34770917	1
Bin	(20)	0	1	2835	1
Bin	(20)	1	0	38388044	1
Bin	(19)	0	1	2835	1
Bin	(19)	1	0	34770478	1
Bin	(18)	0	1	2835	1
Bin	(18)	1	0	34775306	1
Bin	(17)	0	1	2835	1
Bin	(17)	1	0	34770478	1
Bin	(16)	0	1	4082	1
Bin	(16)	1	0	38427169	1
Bin	(15)	0	1	4082	1
Bin	(15)	1	0	38427165	1
Bin	(14)	0	1	43199	1
Bin	(14)	1	0	38389394	1
Bin	(13)	0	1	2192	1
Bin	(13)	1	0	38368451	1
Bin	(12)	0	1	14080	1
Bin	(12)	1	0	36193291	1
Bin	(11)	0	1	112340	1
Bin	(11)	1	0	38320253	1
Bin	(10)	0	1	6712	1
Bin	(10)	1	0	38425881	1
Bin	(9)	0	1	6622	1
Bin	(9)	1	0	38425971	1
Bin	(8)	0	1	485	1
Bin	(8)	1	0	38432108	1
Bin	(7)	0	1	565	1
Bin	(7)	1	0	38432028	1
Bin	(6)	0	1	552	1
Bin	(6)	1	0	38432041	1
Bin	(5)	0	1	632	1
Bin	(5)	1	0	38431961	1
Bin	(4)	0	1	2154	1
Bin	(4)	1	0	38430439	1
Bin	(3)	0	1	1477	1
Bin	(3)	1	0	38431116	1
Bin	(2)	0	1	8769066	1
Bin	(2)	1	0	29663527	1
Bin	(1)	0	1	75539	1
Bin	(1)	1	0	38357054	1
Bin	(0)	0	1	25	1
Bin	(0)	1	0	38432568	1

Signal:

R_DATA_COMB

	Element	From	To	Count	Threshold
Bin	(31)	0	1	23276	1
Bin	(31)	1	0	24877	1
Bin	(30)	0	1	20357	1
Bin	(30)	1	0	21958	1
Bin	(29)	0	1	27373	1
Bin	(29)	1	0	28974	1
Bin	(28)	0	1	95232	1
Bin	(28)	1	0	96833	1
Bin	(27)	0	1	57438	1
Bin	(27)	1	0	59039	1
Bin	(26)	0	1	30833	1
Bin	(26)	1	0	32434	1
Bin	(25)	0	1	354004	1
Bin	(25)	1	0	354004	1
Bin	(24)	0	1	40930	1
Bin	(24)	1	0	42531	1
Bin	(23)	0	1	50771	1
Bin	(23)	1	0	52372	1
Bin	(22)	0	1	164633	1
Bin	(22)	1	0	166234	1
Bin	(21)	0	1	68980	1
Bin	(21)	1	0	70581	1
Bin	(20)	0	1	77435	1
Bin	(20)	1	0	79036	1
Bin	(19)	0	1	98472	1
Bin	(19)	1	0	100073	1
Bin	(18)	0	1	9077438	1
Bin	(18)	1	0	9077438	1
Bin	(17)	0	1	9607907	1
Bin	(17)	1	0	9607907	1
Bin	(16)	0	1	9046081	1
Bin	(16)	1	0	9046081	1
Bin	(15)	0	1	509644	1
Bin	(15)	1	0	509644	1
Bin	(14)	0	1	1078916	1
Bin	(14)	1	0	1078916	1
Bin	(13)	0	1	243172	1
Bin	(13)	1	0	244773	1
Bin	(12)	0	1	263188	1
Bin	(12)	1	0	264789	1
Bin	(11)	0	1	400055	1
Bin	(11)	1	0	400055	1
Bin	(10)	0	1	4195593	1
Bin	(10)	1	0	4197194	1
Bin	(9)	0	1	1129246	1
Bin	(9)	1	0	1129246	1
Bin	(8)	0	1	4358362	1
Bin	(8)	1	0	4359963	1
Bin	(7)	0	1	2578892	1
Bin	(7)	1	0	2578892	1
Bin	(6)	0	1	5767829	1
Bin	(6)	1	0	5767829	1
Bin	(5)	0	1	9887931	1
Bin	(5)	1	0	9887931	1
Bin	(4)	0	1	6421419	1
Bin	(4)	1	0	6421419	1
Bin	(3)	0	1	9761057	1
Bin	(3)	1	0	9761057	1
Bin	(2)	0	1	9906263	1
Bin	(2)	1	0	9906263	1
Bin	(1)	0	1	2452727	1
Bin	(1)	1	0	2454328	1
Bin	(0)	0	1	4181438	1
Bin	(0)	1	0	4181438	1

Signal:

READ_DATA_MASK_N

	Element	From	To	Count	Threshold
Bin	(31)	0	1	27488021	1
Bin	(31)	1	0	37491	1
Bin	(30)	0	1	27488021	1
Bin	(30)	1	0	37491	1
Bin	(29)	0	1	27488021	1
Bin	(29)	1	0	37491	1
Bin	(28)	0	1	27488021	1
Bin	(28)	1	0	37491	1
Bin	(27)	0	1	27488021	1
Bin	(27)	1	0	37491	1
Bin	(26)	0	1	27488021	1
Bin	(26)	1	0	37491	1
Bin	(25)	0	1	27488021	1
Bin	(25)	1	0	37491	1
Bin	(24)	0	1	27488021	1
Bin	(24)	1	0	37491	1
Bin	(23)	0	1	27488403	1
Bin	(23)	1	0	37109	1
Bin	(22)	0	1	27488403	1
Bin	(22)	1	0	37109	1
Bin	(21)	0	1	27488403	1
Bin	(21)	1	0	37109	1
Bin	(20)	0	1	27488403	1
Bin	(20)	1	0	37109	1
Bin	(19)	0	1	27488403	1
Bin	(19)	1	0	37109	1
Bin	(18)	0	1	27488403	1
Bin	(18)	1	0	37109	1
Bin	(17)	0	1	27488403	1
Bin	(17)	1	0	37109	1
Bin	(16)	0	1	27488403	1
Bin	(16)	1	0	37109	1
Bin	(15)	0	1	27389228	1
Bin	(15)	1	0	136284	1
Bin	(14)	0	1	27389228	1
Bin	(14)	1	0	136284	1
Bin	(13)	0	1	27389228	1
Bin	(13)	1	0	136284	1
Bin	(12)	0	1	27389228	1
Bin	(12)	1	0	136284	1
Bin	(11)	0	1	27389228	1
Bin	(11)	1	0	136284	1
Bin	(10)	0	1	27389228	1
Bin	(10)	1	0	136284	1
Bin	(9)	0	1	27389228	1
Bin	(9)	1	0	136284	1
Bin	(8)	0	1	27389228	1
Bin	(8)	1	0	136284	1
Bin	(7)	0	1	27390472	1
Bin	(7)	1	0	135040	1
Bin	(6)	0	1	27390472	1
Bin	(6)	1	0	135040	1
Bin	(5)	0	1	27390472	1
Bin	(5)	1	0	135040	1
Bin	(4)	0	1	27390472	1
Bin	(4)	1	0	135040	1
Bin	(3)	0	1	27390472	1
Bin	(3)	1	0	135040	1
Bin	(2)	0	1	27390472	1
Bin	(2)	1	0	135040	1
Bin	(1)	0	1	27390472	1
Bin	(1)	1	0	135040	1
Bin	(0)	0	1	27390472	1
Bin	(0)	1	0	135040	1

Signal:

CONTROL_REGISTERS_OUT_I

	Element	From	To	Count	Threshold
Bin	MODE_RST	0	1	868	1
Bin	MODE_RST	1	0	32879	1
Bin	MODE_BMM	0	1	15	1
Bin	MODE_BMM	1	0	1616	1
Bin	MODE_STM	0	1	160	1
Bin	MODE_STM	1	0	1761	1
Bin	MODE_AFM	0	1	68	1
Bin	MODE_AFM	1	0	1669	1
Bin	MODE_FDE	0	1	1801	1
Bin	MODE_FDE	1	0	200	1
Bin	MODE_TTTM	0	1	55	1
Bin	MODE_TTTM	1	0	1656	1
Bin	MODE_ROM	0	1	51	1
Bin	MODE_ROM	1	0	1652	1
Bin	MODE_ACF	0	1	19	1
Bin	MODE_ACF	1	0	1620	1
Bin	MODE_TSTM	0	1	1027	1
Bin	MODE_TSTM	1	0	2627	1
Bin	MODE_RXBAM	0	1	1731	1
Bin	MODE_RXBAM	1	0	130	1
Bin	MODE_TXBBM	0	1	33	1
Bin	MODE_TXBBM	1	0	1634	1
Bin	MODE_SAM	0	1	55	1
Bin	MODE_SAM	1	0	1656	1
Bin	MODE_ERFM	0	1	153	1
Bin	MODE_ERFM	1	0	1754	1
Bin	SETTINGS_RTRLE	0	1	2454	1
Bin	SETTINGS_RTRLE	1	0	4054	1
Bin	SETTINGS_RTRTH(3)	0	1	22	1
Bin	SETTINGS_RTRTH(3)	1	0	1623	1
Bin	SETTINGS_RTRTH(2)	0	1	54	1
Bin	SETTINGS_RTRTH(2)	1	0	1655	1
Bin	SETTINGS_RTRTH(1)	0	1	22	1
Bin	SETTINGS_RTRTH(1)	1	0	1623	1
Bin	SETTINGS_RTRTH(0)	0	1	59	1
Bin	SETTINGS_RTRTH(0)	1	0	1660	1
Bin	SETTINGS_ILBP	0	1	130	1
Bin	SETTINGS_ILBP	1	0	1731	1
Bin	SETTINGS_ENA	0	1	6483	1
Bin	SETTINGS_ENA	1	0	8072	1
Bin	SETTINGS_NISOFD	0	1	130	1
Bin	SETTINGS_NISOFD	1	0	1731	1
Bin	SETTINGS_PEX	0	1	72	1
Bin	SETTINGS_PEX	1	0	1673	1
Bin	SETTINGS_TBFBO	0	1	2534	1
Bin	SETTINGS_TBFBO	1	0	944	1
Bin	SETTINGS_FDRF	0	1	4	1
Bin	SETTINGS_FDRF	1	0	1605	1
Bin	SETTINGS_PCHKE	0	1	112	1
Bin	SETTINGS_PCHKE	1	0	1713	1
Bin	COMMAND_RXRPMV	0	1	25	1
Bin	COMMAND_RXRPMV	1	0	3068	1
Bin	COMMAND_RRB	0	1	460	1
Bin	COMMAND_RRB	1	0	3068	1
Bin	COMMAND_CDO	0	1	20	1
Bin	COMMAND_CDO	1	0	3068	1
Bin	COMMAND_ERCRST	0	1	170	1
Bin	COMMAND_ERCRST	1	0	3068	1
Bin	COMMAND_RXFCRST	0	1	124	1
Bin	COMMAND_RXFCRST	1	0	3068	1
Bin	COMMAND_TXFCRST	0	1	124	1
Bin	COMMAND_TXFCRST	1	0	3068	1
Bin	COMMAND_CPEXS	0	1	60	1
Bin	COMMAND_CPEXS	1	0	3068	1
Bin	COMMAND_CRXPE	0	1	40	1
Bin	COMMAND_CRXPE	1	0	3068	1
Bin	COMMAND_CTXPE	0	1	440	1
Bin	COMMAND_CTXPE	1	0	3068	1
Bin	COMMAND_CTXDPE	0	1	40	1
Bin	COMMAND_CTXDPE	1	0	3068	1
Bin	INT_STAT_RXI	0	1	40	1
Bin	INT_STAT_RXI	1	0	1748	1
Bin	INT_STAT_TXI	0	1	42	1
Bin	INT_STAT_TXI	1	0	1748	1
Bin	INT_STAT_EWLI	0	1	30	1
Bin	INT_STAT_EWLI	1	0	1748	1
Bin	INT_STAT_DOI	0	1	16	1
Bin	INT_STAT_DOI	1	0	1748	1
Bin	INT_STAT_FCSI	0	1	80	1
Bin	INT_STAT_FCSI	1	0	1748	1
Bin	INT_STAT_ALI	0	1	5	1
Bin	INT_STAT_ALI	1	0	1748	1
Bin	INT_STAT_BEI	0	1	15	1
Bin	INT_STAT_BEI	1	0	1748	1
Bin	INT_STAT_OFI	0	1	5	1
Bin	INT_STAT_OFI	1	0	1748	1
Bin	INT_STAT_RXFI	0	1	15	1
Bin	INT_STAT_RXFI	1	0	1748	1
Bin	INT_STAT_BSI	0	1	34	1
Bin	INT_STAT_BSI	1	0	1748	1
Bin	INT_STAT_RBNEI	0	1	50	1
Bin	INT_STAT_RBNEI	1	0	1748	1
Bin	INT_STAT_TXBHCI	0	1	52	1
Bin	INT_STAT_TXBHCI	1	0	1748	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	0	1	66	1
Bin	INT_ENA_SET_INT_ENA_SET(11)	1	0	2278	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	0	1	30	1
Bin	INT_ENA_SET_INT_ENA_SET(10)	1	0	2278	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	0	1	50	1
Bin	INT_ENA_SET_INT_ENA_SET(9)	1	0	2278	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(8)	1	0	2278	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(7)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(6)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(5)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(4)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	0	1	15	1
Bin	INT_ENA_SET_INT_ENA_SET(3)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(2)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(1)	1	0	2304	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	0	1	20	1
Bin	INT_ENA_SET_INT_ENA_SET(0)	1	0	2304	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	0	1	476	1
Bin	INT_ENA_CLR_INT_ENA_CLR(11)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	0	1	512	1
Bin	INT_ENA_CLR_INT_ENA_CLR(10)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	0	1	492	1
Bin	INT_ENA_CLR_INT_ENA_CLR(9)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(8)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(7)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(6)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(5)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(4)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	0	1	527	1
Bin	INT_ENA_CLR_INT_ENA_CLR(3)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(2)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(1)	1	0	2143	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	0	1	522	1
Bin	INT_ENA_CLR_INT_ENA_CLR(0)	1	0	2143	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	0	1	66	1
Bin	INT_MASK_SET_INT_MASK_SET(11)	1	0	2156	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	0	1	40	1
Bin	INT_MASK_SET_INT_MASK_SET(10)	1	0	2156	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	0	1	50	1
Bin	INT_MASK_SET_INT_MASK_SET(9)	1	0	2156	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	0	1	15	1
Bin	INT_MASK_SET_INT_MASK_SET(8)	1	0	2156	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(7)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(6)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(5)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(4)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(3)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(2)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(1)	1	0	2247	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	0	1	10	1
Bin	INT_MASK_SET_INT_MASK_SET(0)	1	0	2247	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	0	1	409	1
Bin	INT_MASK_CLR_INT_MASK_CLR(11)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	0	1	435	1
Bin	INT_MASK_CLR_INT_MASK_CLR(10)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	0	1	425	1
Bin	INT_MASK_CLR_INT_MASK_CLR(9)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	0	1	460	1
Bin	INT_MASK_CLR_INT_MASK_CLR(8)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(7)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(6)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(5)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(4)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(3)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(2)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(1)	1	0	2076	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	0	1	465	1
Bin	INT_MASK_CLR_INT_MASK_CLR(0)	1	0	2076	1
Bin	BTR_PROP(6)	0	1	200	1
Bin	BTR_PROP(6)	1	0	1799	1
Bin	BTR_PROP(5)	0	1	309	1
Bin	BTR_PROP(5)	1	0	1907	1
Bin	BTR_PROP(4)	0	1	225	1
Bin	BTR_PROP(4)	1	0	1823	1
Bin	BTR_PROP(3)	0	1	273	1
Bin	BTR_PROP(3)	1	0	1871	1
Bin	BTR_PROP(2)	0	1	3822	1
Bin	BTR_PROP(2)	1	0	2222	1
Bin	BTR_PROP(1)	0	1	262	1
Bin	BTR_PROP(1)	1	0	1860	1
Bin	BTR_PROP(0)	0	1	1793	1
Bin	BTR_PROP(0)	1	0	193	1
Bin	BTR_PH1(5)	0	1	327	1
Bin	BTR_PH1(5)	1	0	1965	1
Bin	BTR_PH1(4)	0	1	289	1
Bin	BTR_PH1(4)	1	0	1910	1
Bin	BTR_PH1(3)	0	1	316	1
Bin	BTR_PH1(3)	1	0	1954	1
Bin	BTR_PH1(2)	0	1	1412	1
Bin	BTR_PH1(2)	1	0	3042	1
Bin	BTR_PH1(1)	0	1	2174	1
Bin	BTR_PH1(1)	1	0	534	1
Bin	BTR_PH1(0)	0	1	4486	1
Bin	BTR_PH1(0)	1	0	491	1
Bin	BTR_PH2(5)	0	1	267	1
Bin	BTR_PH2(5)	1	0	7769	1
Bin	BTR_PH2(4)	0	1	508	1
Bin	BTR_PH2(4)	1	0	8140	1
Bin	BTR_PH2(3)	0	1	698	1
Bin	BTR_PH2(3)	1	0	8215	1
Bin	BTR_PH2(2)	0	1	3879	1
Bin	BTR_PH2(2)	1	0	2275	1
Bin	BTR_PH2(1)	0	1	3417	1
Bin	BTR_PH2(1)	1	0	5010	1
Bin	BTR_PH2(0)	0	1	2160	1
Bin	BTR_PH2(0)	1	0	559	1
Bin	BTR_BRP(7)	0	1	13	1
Bin	BTR_BRP(7)	1	0	8160	1
Bin	BTR_BRP(6)	0	1	14	1
Bin	BTR_BRP(6)	1	0	8161	1
Bin	BTR_BRP(5)	0	1	12	1
Bin	BTR_BRP(5)	1	0	8159	1
Bin	BTR_BRP(4)	0	1	16	1
Bin	BTR_BRP(4)	1	0	1627	1
Bin	BTR_BRP(3)	0	1	4842	1
Bin	BTR_BRP(3)	1	0	3242	1
Bin	BTR_BRP(2)	0	1	930	1
Bin	BTR_BRP(2)	1	0	2534	1
Bin	BTR_BRP(1)	0	1	4773	1
Bin	BTR_BRP(1)	1	0	3170	1
Bin	BTR_BRP(0)	0	1	2317	1
Bin	BTR_BRP(0)	1	0	3926	1
Bin	BTR_SJW(4)	0	1	204	1
Bin	BTR_SJW(4)	1	0	1802	1
Bin	BTR_SJW(3)	0	1	271	1
Bin	BTR_SJW(3)	1	0	1869	1
Bin	BTR_SJW(2)	0	1	971	1
Bin	BTR_SJW(2)	1	0	2568	1
Bin	BTR_SJW(1)	0	1	2624	1
Bin	BTR_SJW(1)	1	0	1032	1
Bin	BTR_SJW(0)	0	1	3116	1
Bin	BTR_SJW(0)	1	0	4713	1
Bin	BTR_FD_PROP_FD(5)	0	1	239	1
Bin	BTR_FD_PROP_FD(5)	1	0	1837	1
Bin	BTR_FD_PROP_FD(4)	0	1	292	1
Bin	BTR_FD_PROP_FD(4)	1	0	1890	1
Bin	BTR_FD_PROP_FD(3)	0	1	278	1
Bin	BTR_FD_PROP_FD(3)	1	0	1876	1
Bin	BTR_FD_PROP_FD(2)	0	1	1184	1
Bin	BTR_FD_PROP_FD(2)	1	0	2773	1
Bin	BTR_FD_PROP_FD(1)	0	1	4706	1
Bin	BTR_FD_PROP_FD(1)	1	0	3114	1
Bin	BTR_FD_PROP_FD(0)	0	1	3888	1
Bin	BTR_FD_PROP_FD(0)	1	0	2287	1
Bin	BTR_FD_PH1_FD(4)	0	1	248	1
Bin	BTR_FD_PH1_FD(4)	1	0	5977	1
Bin	BTR_FD_PH1_FD(3)	0	1	297	1
Bin	BTR_FD_PH1_FD(3)	1	0	6035	1
Bin	BTR_FD_PH1_FD(2)	0	1	1183	1
Bin	BTR_FD_PH1_FD(2)	1	0	6912	1
Bin	BTR_FD_PH1_FD(1)	0	1	5839	1
Bin	BTR_FD_PH1_FD(1)	1	0	124	1
Bin	BTR_FD_PH1_FD(0)	0	1	6023	1
Bin	BTR_FD_PH1_FD(0)	1	0	2286	1
Bin	BTR_FD_PH2_FD(4)	0	1	328	1
Bin	BTR_FD_PH2_FD(4)	1	0	7904	1
Bin	BTR_FD_PH2_FD(3)	0	1	403	1
Bin	BTR_FD_PH2_FD(3)	1	0	7927	1
Bin	BTR_FD_PH2_FD(2)	0	1	1216	1
Bin	BTR_FD_PH2_FD(2)	1	0	2819	1
Bin	BTR_FD_PH2_FD(1)	0	1	1736	1
Bin	BTR_FD_PH2_FD(1)	1	0	134	1
Bin	BTR_FD_PH2_FD(0)	0	1	3883	1
Bin	BTR_FD_PH2_FD(0)	1	0	2288	1
Bin	BTR_FD_BRP_FD(7)	0	1	18	1
Bin	BTR_FD_BRP_FD(7)	1	0	8136	1
Bin	BTR_FD_BRP_FD(6)	0	1	29	1
Bin	BTR_FD_BRP_FD(6)	1	0	8147	1
Bin	BTR_FD_BRP_FD(5)	0	1	17	1
Bin	BTR_FD_BRP_FD(5)	1	0	8135	1
Bin	BTR_FD_BRP_FD(4)	0	1	30	1
Bin	BTR_FD_BRP_FD(4)	1	0	1641	1
Bin	BTR_FD_BRP_FD(3)	0	1	27	1
Bin	BTR_FD_BRP_FD(3)	1	0	1628	1
Bin	BTR_FD_BRP_FD(2)	0	1	4843	1
Bin	BTR_FD_BRP_FD(2)	1	0	3264	1
Bin	BTR_FD_BRP_FD(1)	0	1	757	1
Bin	BTR_FD_BRP_FD(1)	1	0	2355	1
Bin	BTR_FD_BRP_FD(0)	0	1	2600	1
Bin	BTR_FD_BRP_FD(0)	1	0	4202	1
Bin	BTR_FD_SJW_FD(4)	0	1	247	1
Bin	BTR_FD_SJW_FD(4)	1	0	1845	1
Bin	BTR_FD_SJW_FD(3)	0	1	289	1
Bin	BTR_FD_SJW_FD(3)	1	0	1887	1
Bin	BTR_FD_SJW_FD(2)	0	1	916	1
Bin	BTR_FD_SJW_FD(2)	1	0	2513	1
Bin	BTR_FD_SJW_FD(1)	0	1	2568	1
Bin	BTR_FD_SJW_FD(1)	1	0	976	1
Bin	BTR_FD_SJW_FD(0)	0	1	953	1
Bin	BTR_FD_SJW_FD(0)	1	0	2550	1
Bin	EWL_EW_LIMIT(7)	0	1	78	1
Bin	EWL_EW_LIMIT(7)	1	0	1679	1
Bin	EWL_EW_LIMIT(6)	0	1	1686	1
Bin	EWL_EW_LIMIT(6)	1	0	85	1
Bin	EWL_EW_LIMIT(5)	0	1	1672	1
Bin	EWL_EW_LIMIT(5)	1	0	71	1
Bin	EWL_EW_LIMIT(4)	0	1	72	1
Bin	EWL_EW_LIMIT(4)	1	0	1673	1
Bin	EWL_EW_LIMIT(3)	0	1	75	1
Bin	EWL_EW_LIMIT(3)	1	0	1676	1
Bin	EWL_EW_LIMIT(2)	0	1	85	1
Bin	EWL_EW_LIMIT(2)	1	0	1686	1
Bin	EWL_EW_LIMIT(1)	0	1	88	1
Bin	EWL_EW_LIMIT(1)	1	0	1689	1
Bin	EWL_EW_LIMIT(0)	0	1	81	1
Bin	EWL_EW_LIMIT(0)	1	0	1682	1
Bin	ERP_ERP_LIMIT(7)	0	1	1732	1
Bin	ERP_ERP_LIMIT(7)	1	0	131	1
Bin	ERP_ERP_LIMIT(6)	0	1	25	1
Bin	ERP_ERP_LIMIT(6)	1	0	1626	1
Bin	ERP_ERP_LIMIT(5)	0	1	21	1
Bin	ERP_ERP_LIMIT(5)	1	0	1622	1
Bin	ERP_ERP_LIMIT(4)	0	1	26	1
Bin	ERP_ERP_LIMIT(4)	1	0	1627	1
Bin	ERP_ERP_LIMIT(3)	0	1	21	1
Bin	ERP_ERP_LIMIT(3)	1	0	1622	1
Bin	ERP_ERP_LIMIT(2)	0	1	26	1
Bin	ERP_ERP_LIMIT(2)	1	0	1627	1
Bin	ERP_ERP_LIMIT(1)	0	1	28	1
Bin	ERP_ERP_LIMIT(1)	1	0	1629	1
Bin	ERP_ERP_LIMIT(0)	0	1	30	1
Bin	ERP_ERP_LIMIT(0)	1	0	1631	1
Bin	CTR_PRES_CTPV(8)	0	1	359	1
Bin	CTR_PRES_CTPV(8)	1	0	8620	1
Bin	CTR_PRES_CTPV(7)	0	1	2608	1
Bin	CTR_PRES_CTPV(7)	1	0	4239	1
Bin	CTR_PRES_CTPV(6)	0	1	733	1
Bin	CTR_PRES_CTPV(6)	1	0	2364	1
Bin	CTR_PRES_CTPV(5)	0	1	2611	1
Bin	CTR_PRES_CTPV(5)	1	0	4232	1
Bin	CTR_PRES_CTPV(4)	0	1	2774	1
Bin	CTR_PRES_CTPV(4)	1	0	4395	1
Bin	CTR_PRES_CTPV(3)	0	1	894	1
Bin	CTR_PRES_CTPV(3)	1	0	2515	1
Bin	CTR_PRES_CTPV(2)	0	1	2887	1
Bin	CTR_PRES_CTPV(2)	1	0	4519	1
Bin	CTR_PRES_CTPV(1)	0	1	1016	1
Bin	CTR_PRES_CTPV(1)	1	0	2637	1
Bin	CTR_PRES_CTPV(0)	0	1	804	1
Bin	CTR_PRES_CTPV(0)	1	0	2425	1
Bin	CTR_PRES_PTX	0	1	19125	1
Bin	CTR_PRES_PTX	1	0	44590	1
Bin	CTR_PRES_PRX	0	1	19522	1
Bin	CTR_PRES_PRX	1	0	44590	1
Bin	CTR_PRES_ENORM	0	1	6369	1
Bin	CTR_PRES_ENORM	1	0	44590	1
Bin	CTR_PRES_EFD	0	1	6369	1
Bin	CTR_PRES_EFD	1	0	44590	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	0	1	389	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(28)	1	0	2418	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	0	1	349	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(27)	1	0	2306	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	0	1	339	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(26)	1	0	2225	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	0	1	365	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(25)	1	0	2357	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(24)	1	0	2344	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	0	1	378	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(23)	1	0	2161	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	0	1	395	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(22)	1	0	2211	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	0	1	366	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(21)	1	0	2162	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	0	1	383	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(20)	1	0	2206	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	0	1	368	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(19)	1	0	2140	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	0	1	411	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(18)	1	0	2235	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	0	1	97	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(17)	1	0	1809	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	0	1	82	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(16)	1	0	1738	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	0	1	94	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(15)	1	0	2057	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(14)	1	0	2247	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	0	1	118	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(13)	1	0	2133	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	0	1	131	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(12)	1	0	2142	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	0	1	106	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(11)	1	0	2217	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	0	1	249	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(10)	1	0	2346	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	0	1	250	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(9)	1	0	2291	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	0	1	252	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(8)	1	0	2639	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	0	1	281	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(7)	1	0	2396	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	0	1	265	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(6)	1	0	2534	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	0	1	278	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(5)	1	0	2405	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	0	1	239	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(4)	1	0	2206	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	0	1	267	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(3)	1	0	2474	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	0	1	280	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(2)	1	0	2443	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	0	1	242	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(1)	1	0	2299	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	0	1	270	1
Bin	FILTER_A_MASK_BIT_MASK_A_VAL(0)	1	0	2289	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	0	1	816	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(28)	1	0	2462	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	0	1	793	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(27)	1	0	2455	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	0	1	803	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(26)	1	0	2457	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	0	1	791	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(25)	1	0	2435	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	0	1	805	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(24)	1	0	2463	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	0	1	764	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(23)	1	0	2390	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(22)	1	0	2449	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	0	1	772	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(21)	1	0	2391	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	0	1	763	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(20)	1	0	2390	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	0	1	832	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(19)	1	0	2459	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	0	1	836	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(18)	1	0	2469	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	0	1	395	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(17)	1	0	2010	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	0	1	429	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(16)	1	0	2044	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	0	1	403	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(15)	1	0	2525	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(14)	1	0	2591	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(13)	1	0	2569	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(12)	1	0	2749	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	0	1	415	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(11)	1	0	2727	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	0	1	413	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(10)	1	0	2823	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	0	1	397	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(9)	1	0	2805	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	0	1	398	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(8)	1	0	2614	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	0	1	402	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(7)	1	0	2714	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	0	1	394	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(6)	1	0	2706	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	0	1	405	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(5)	1	0	2845	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	0	1	421	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(4)	1	0	3031	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	0	1	396	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(3)	1	0	2772	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	0	1	423	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(2)	1	0	3033	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	0	1	378	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(1)	1	0	2700	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	0	1	410	1
Bin	FILTER_A_VAL_BIT_VAL_A_VAL(0)	1	0	2668	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(28)	1	0	1788	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	0	1	96	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(27)	1	0	1789	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	0	1	80	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(26)	1	0	1763	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(25)	1	0	1782	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	0	1	102	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(24)	1	0	1819	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(23)	1	0	1736	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	0	1	91	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(22)	1	0	1738	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	0	1	82	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(21)	1	0	1729	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	0	1	105	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(20)	1	0	1760	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	0	1	93	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(19)	1	0	1736	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	0	1	89	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(18)	1	0	1730	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(17)	1	0	1637	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	0	1	15	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(16)	1	0	1634	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	0	1	33	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(15)	1	0	1791	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	0	1	22	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(14)	1	0	1694	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	0	1	36	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(13)	1	0	1736	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	0	1	35	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(12)	1	0	1743	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	0	1	34	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(11)	1	0	1858	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	0	1	63	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(10)	1	0	1723	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	0	1	66	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(9)	1	0	1722	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(8)	1	0	1804	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(7)	1	0	1903	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(6)	1	0	1742	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	0	1	71	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(5)	1	0	1795	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	0	1	65	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(4)	1	0	1753	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	0	1	62	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(3)	1	0	1864	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	0	1	68	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(2)	1	0	1756	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	0	1	67	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(1)	1	0	1757	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	0	1	59	1
Bin	FILTER_B_MASK_BIT_MASK_B_VAL(0)	1	0	1765	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	0	1	186	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(28)	1	0	1807	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	0	1	191	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(27)	1	0	1814	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	0	1	195	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(26)	1	0	1816	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	0	1	200	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(25)	1	0	1825	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(24)	1	0	1825	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	0	1	204	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(23)	1	0	1812	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	0	1	206	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(22)	1	0	1810	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	0	1	198	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(21)	1	0	1802	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	0	1	202	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(20)	1	0	1809	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	0	1	213	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(19)	1	0	1819	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	0	1	212	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(18)	1	0	1818	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(17)	1	0	1706	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(16)	1	0	1712	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(15)	1	0	1875	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	0	1	92	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(14)	1	0	1830	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	0	1	111	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(13)	1	0	1881	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(12)	1	0	1839	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	0	1	91	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(11)	1	0	1893	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	0	1	103	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(10)	1	0	2033	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	0	1	101	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(9)	1	0	1967	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	0	1	97	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(8)	1	0	1867	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	0	1	104	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(7)	1	0	1874	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	0	1	95	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(6)	1	0	1865	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	0	1	102	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(5)	1	0	1776	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	0	1	106	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(4)	1	0	1876	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	0	1	105	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(3)	1	0	1939	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	0	1	100	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(2)	1	0	1902	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	0	1	107	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(1)	1	0	1909	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	0	1	94	1
Bin	FILTER_B_VAL_BIT_VAL_B_VAL(0)	1	0	1832	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	0	1	94	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(28)	1	0	1777	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(27)	1	0	1784	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	0	1	86	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(26)	1	0	1755	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	0	1	100	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(25)	1	0	1787	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	0	1	104	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(24)	1	0	1805	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	0	1	93	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(23)	1	0	1750	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	0	1	98	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(22)	1	0	1748	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	0	1	88	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(21)	1	0	1756	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	0	1	97	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(20)	1	0	1764	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	0	1	79	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(19)	1	0	1726	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	0	1	87	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(18)	1	0	1734	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	0	1	22	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(17)	1	0	1641	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	0	1	17	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(16)	1	0	1644	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	0	1	30	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(15)	1	0	1757	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	0	1	21	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(14)	1	0	1694	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	0	1	37	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(13)	1	0	1712	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(12)	1	0	1717	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	0	1	34	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(11)	1	0	1827	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(10)	1	0	1755	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(9)	1	0	1730	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	0	1	63	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(8)	1	0	1810	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(7)	1	0	1932	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(6)	1	0	1749	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	0	1	71	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(5)	1	0	1772	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	0	1	69	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(4)	1	0	1762	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	0	1	62	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(3)	1	0	1835	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	0	1	67	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(2)	1	0	1756	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	0	1	66	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(1)	1	0	1761	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	0	1	58	1
Bin	FILTER_C_MASK_BIT_MASK_C_VAL(0)	1	0	1769	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	0	1	184	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(28)	1	0	1811	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	0	1	182	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(27)	1	0	1805	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	0	1	199	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(26)	1	0	1825	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	0	1	193	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(25)	1	0	1826	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	0	1	190	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(24)	1	0	1821	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	0	1	207	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(23)	1	0	1811	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	0	1	213	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(22)	1	0	1818	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(21)	1	0	1804	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	0	1	198	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(20)	1	0	1802	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	0	1	203	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(19)	1	0	1807	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	0	1	214	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(18)	1	0	1818	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(17)	1	0	1704	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	0	1	103	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(16)	1	0	1707	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	0	1	100	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(15)	1	0	1933	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	0	1	99	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(14)	1	0	1804	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(13)	1	0	1941	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(12)	1	0	1874	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	0	1	86	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(11)	1	0	1855	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(10)	1	0	1995	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	0	1	104	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(9)	1	0	2033	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	0	1	102	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(8)	1	0	1871	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(7)	1	0	1866	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	0	1	96	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(6)	1	0	1899	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(5)	1	0	1783	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	0	1	105	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(4)	1	0	1876	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	0	1	110	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(3)	1	0	1977	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	0	1	98	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(2)	1	0	1901	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	0	1	108	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(1)	1	0	1911	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	0	1	95	1
Bin	FILTER_C_VAL_BIT_VAL_C_VAL(0)	1	0	1770	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	0	1	2	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)	1	0	1603	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)	1	0	1604	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	0	1	1	1
Bin	FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	0	1	2	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)	1	0	1603	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)	1	0	1602	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)	1	0	1604	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	0	1	1	1
Bin	FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)	1	0	1604	1
Bin	FILTER_CONTROL_FANB	0	1	2052	1
Bin	FILTER_CONTROL_FANB	1	0	451	1
Bin	FILTER_CONTROL_FANE	0	1	2029	1
Bin	FILTER_CONTROL_FANE	1	0	428	1
Bin	FILTER_CONTROL_FAFB	0	1	2060	1
Bin	FILTER_CONTROL_FAFB	1	0	459	1
Bin	FILTER_CONTROL_FAFE	0	1	2029	1
Bin	FILTER_CONTROL_FAFE	1	0	428	1
Bin	FILTER_CONTROL_FBNB	0	1	106	1
Bin	FILTER_CONTROL_FBNB	1	0	1707	1
Bin	FILTER_CONTROL_FBNE	0	1	105	1
Bin	FILTER_CONTROL_FBNE	1	0	1706	1
Bin	FILTER_CONTROL_FBFB	0	1	107	1
Bin	FILTER_CONTROL_FBFB	1	0	1708	1
Bin	FILTER_CONTROL_FBFE	0	1	105	1
Bin	FILTER_CONTROL_FBFE	1	0	1706	1
Bin	FILTER_CONTROL_FCNB	0	1	106	1
Bin	FILTER_CONTROL_FCNB	1	0	1707	1
Bin	FILTER_CONTROL_FCNE	0	1	105	1
Bin	FILTER_CONTROL_FCNE	1	0	1706	1
Bin	FILTER_CONTROL_FCFB	0	1	107	1
Bin	FILTER_CONTROL_FCFB	1	0	1708	1
Bin	FILTER_CONTROL_FCFE	0	1	105	1
Bin	FILTER_CONTROL_FCFE	1	0	1706	1
Bin	FILTER_CONTROL_FRNB	0	1	6	1
Bin	FILTER_CONTROL_FRNB	1	0	1607	1
Bin	FILTER_CONTROL_FRNE	0	1	5	1
Bin	FILTER_CONTROL_FRNE	1	0	1606	1
Bin	FILTER_CONTROL_FRFB	0	1	6	1
Bin	FILTER_CONTROL_FRFB	1	0	1607	1
Bin	FILTER_CONTROL_FRFE	0	1	5	1
Bin	FILTER_CONTROL_FRFE	1	0	1606	1
Bin	RX_SETTINGS_RTSOP	0	1	5	1
Bin	RX_SETTINGS_RTSOP	1	0	1606	1
Bin	RX_DATA_READ	0	1	51790	1
Bin	RX_DATA_READ	1	0	53391	1
Bin	TX_COMMAND_TXCE	0	1	354	1
Bin	TX_COMMAND_TXCE	1	0	25076	1
Bin	TX_COMMAND_TXCR	0	1	21387	1
Bin	TX_COMMAND_TXCR	1	0	25076	1
Bin	TX_COMMAND_TXCA	0	1	1734	1
Bin	TX_COMMAND_TXCA	1	0	25076	1
Bin	TX_COMMAND_TXB1	0	1	6553	1
Bin	TX_COMMAND_TXB1	1	0	8149	1
Bin	TX_COMMAND_TXB2	0	1	5587	1
Bin	TX_COMMAND_TXB2	1	0	7188	1
Bin	TX_COMMAND_TXB3	0	1	332	1
Bin	TX_COMMAND_TXB3	1	0	1933	1
Bin	TX_COMMAND_TXB4	0	1	345	1
Bin	TX_COMMAND_TXB4	1	0	1946	1
Bin	TX_COMMAND_TXB5	0	1	91	1
Bin	TX_COMMAND_TXB5	1	0	1692	1
Bin	TX_COMMAND_TXB6	0	1	73	1
Bin	TX_COMMAND_TXB6	1	0	1674	1
Bin	TX_COMMAND_TXB7	0	1	87	1
Bin	TX_COMMAND_TXB7	1	0	1688	1
Bin	TX_COMMAND_TXB8	0	1	74	1
Bin	TX_COMMAND_TXB8	1	0	1675	1
Bin	TX_PRIORITY_TXT1P(2)	0	1	105	1
Bin	TX_PRIORITY_TXT1P(2)	1	0	1706	1
Bin	TX_PRIORITY_TXT1P(1)	0	1	111	1
Bin	TX_PRIORITY_TXT1P(1)	1	0	1712	1
Bin	TX_PRIORITY_TXT1P(0)	0	1	1723	1
Bin	TX_PRIORITY_TXT1P(0)	1	0	122	1
Bin	TX_PRIORITY_TXT2P(2)	0	1	94	1
Bin	TX_PRIORITY_TXT2P(2)	1	0	1695	1
Bin	TX_PRIORITY_TXT2P(1)	0	1	131	1
Bin	TX_PRIORITY_TXT2P(1)	1	0	1732	1
Bin	TX_PRIORITY_TXT2P(0)	0	1	124	1
Bin	TX_PRIORITY_TXT2P(0)	1	0	1725	1
Bin	TX_PRIORITY_TXT3P(2)	0	1	72	1
Bin	TX_PRIORITY_TXT3P(2)	1	0	1673	1
Bin	TX_PRIORITY_TXT3P(1)	0	1	103	1
Bin	TX_PRIORITY_TXT3P(1)	1	0	1704	1
Bin	TX_PRIORITY_TXT3P(0)	0	1	96	1
Bin	TX_PRIORITY_TXT3P(0)	1	0	1697	1
Bin	TX_PRIORITY_TXT4P(2)	0	1	77	1
Bin	TX_PRIORITY_TXT4P(2)	1	0	1678	1
Bin	TX_PRIORITY_TXT4P(1)	0	1	91	1
Bin	TX_PRIORITY_TXT4P(1)	1	0	1692	1
Bin	TX_PRIORITY_TXT4P(0)	0	1	99	1
Bin	TX_PRIORITY_TXT4P(0)	1	0	1700	1
Bin	TX_PRIORITY_TXT5P(2)	0	1	23	1
Bin	TX_PRIORITY_TXT5P(2)	1	0	1624	1
Bin	TX_PRIORITY_TXT5P(1)	0	1	33	1
Bin	TX_PRIORITY_TXT5P(1)	1	0	1634	1
Bin	TX_PRIORITY_TXT5P(0)	0	1	29	1
Bin	TX_PRIORITY_TXT5P(0)	1	0	1630	1
Bin	TX_PRIORITY_TXT6P(2)	0	1	28	1
Bin	TX_PRIORITY_TXT6P(2)	1	0	1629	1
Bin	TX_PRIORITY_TXT6P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT6P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT6P(0)	0	1	33	1
Bin	TX_PRIORITY_TXT6P(0)	1	0	1634	1
Bin	TX_PRIORITY_TXT7P(2)	0	1	26	1
Bin	TX_PRIORITY_TXT7P(2)	1	0	1627	1
Bin	TX_PRIORITY_TXT7P(1)	0	1	27	1
Bin	TX_PRIORITY_TXT7P(1)	1	0	1628	1
Bin	TX_PRIORITY_TXT7P(0)	0	1	31	1
Bin	TX_PRIORITY_TXT7P(0)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(2)	0	1	27	1
Bin	TX_PRIORITY_TXT8P(2)	1	0	1628	1
Bin	TX_PRIORITY_TXT8P(1)	0	1	31	1
Bin	TX_PRIORITY_TXT8P(1)	1	0	1632	1
Bin	TX_PRIORITY_TXT8P(0)	0	1	28	1
Bin	TX_PRIORITY_TXT8P(0)	1	0	1629	1
Bin	SSP_CFG_SSP_OFFSET(7)	0	1	24	1
Bin	SSP_CFG_SSP_OFFSET(7)	1	0	1625	1
Bin	SSP_CFG_SSP_OFFSET(6)	0	1	23	1
Bin	SSP_CFG_SSP_OFFSET(6)	1	0	1624	1
Bin	SSP_CFG_SSP_OFFSET(5)	0	1	48	1
Bin	SSP_CFG_SSP_OFFSET(5)	1	0	1649	1
Bin	SSP_CFG_SSP_OFFSET(4)	0	1	50	1
Bin	SSP_CFG_SSP_OFFSET(4)	1	0	1651	1
Bin	SSP_CFG_SSP_OFFSET(3)	0	1	4306	1
Bin	SSP_CFG_SSP_OFFSET(3)	1	0	2716	1
Bin	SSP_CFG_SSP_OFFSET(2)	0	1	535	1
Bin	SSP_CFG_SSP_OFFSET(2)	1	0	2135	1
Bin	SSP_CFG_SSP_OFFSET(1)	0	1	2902	1
Bin	SSP_CFG_SSP_OFFSET(1)	1	0	1313	1
Bin	SSP_CFG_SSP_OFFSET(0)	0	1	2397	1
Bin	SSP_CFG_SSP_OFFSET(0)	1	0	3997	1
Bin	SSP_CFG_SSP_SRC(1)	0	1	45	1
Bin	SSP_CFG_SSP_SRC(1)	1	0	1646	1
Bin	SSP_CFG_SSP_SRC(0)	0	1	815	1
Bin	SSP_CFG_SSP_SRC(0)	1	0	2405	1

Signal:

WRITE_EN

	Element	From	To	Count	Threshold
Bin	(3)	0	1	126204	1
Bin	(3)	1	0	184987	1
Bin	(2)	0	1	126224	1
Bin	(2)	1	0	184967	1
Bin	(1)	0	1	146672	1
Bin	(1)	1	0	164519	1
Bin	(0)	0	1	146672	1
Bin	(0)	1	0	164519	1

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point on lines 3111 to 3112:

3111:    -- psl device_id_read_access_cov : cover 
3112:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 15
Threshold: 1

PSL cover point on lines 3114 to 3115:

3114:    -- psl version_read_access_cov : cover 
3115:    -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 15
Threshold: 1

PSL cover point on lines 3117 to 3118:

3117:    -- psl mode_write_access_cov : cover 
3118:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 31278
Threshold: 1

PSL cover point on lines 3120 to 3121:

3120:    -- psl mode_read_access_cov : cover 
3121:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 33513
Threshold: 1

PSL cover point on lines 3123 to 3124:

3123:    -- psl settings_write_access_cov : cover 
3124:    -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 34202
Threshold: 1

PSL cover point on lines 3126 to 3127:

3126:    -- psl settings_read_access_cov : cover 
3127:    -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 38872
Threshold: 1

PSL cover point on lines 3129 to 3130:

3129:    -- psl status_read_access_cov : cover 
3130:    -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 8769066
Threshold: 1

PSL cover point on lines 3132 to 3133:

3132:    -- psl command_write_access_cov : cover 
3133:    -- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 1467
Threshold: 1

PSL cover point on lines 3135 to 3136:

3135:    -- psl int_stat_write_access_cov : cover 
3136:    -- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 147
Threshold: 1

PSL cover point on lines 3138 to 3139:

3138:    -- psl int_stat_read_access_cov : cover 
3139:    -- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 2007
Threshold: 1

PSL cover point on lines 3141 to 3142:

3141:    -- psl int_ena_set_write_access_cov : cover 
3142:    -- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 542
Threshold: 1

PSL cover point on lines 3144 to 3145:

3144:    -- psl int_ena_set_read_access_cov : cover 
3145:    -- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 90
Threshold: 1

PSL cover point on lines 3147 to 3148:

3147:    -- psl int_ena_clr_write_access_cov : cover 
3148:    -- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 542
Threshold: 1

PSL cover point on lines 3150 to 3151:

3150:    -- psl int_mask_set_write_access_cov : cover 
3151:    -- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 475
Threshold: 1

PSL cover point on lines 3153 to 3154:

3153:    -- psl int_mask_set_read_access_cov : cover 
3154:    -- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 90
Threshold: 1

PSL cover point on lines 3156 to 3157:

3156:    -- psl int_mask_clr_write_access_cov : cover 
3157:    -- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 475
Threshold: 1

PSL cover point on lines 3159 to 3160:

3159:    -- psl btr_write_access_cov : cover 
3160:    -- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 6312
Threshold: 1

PSL cover point on lines 3162 to 3163:

3162:    -- psl btr_read_access_cov : cover 
3163:    -- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 310
Threshold: 1

PSL cover point on lines 3165 to 3166:

3165:    -- psl btr_fd_write_access_cov : cover 
3166:    -- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 6372
Threshold: 1

PSL cover point on lines 3168 to 3169:

3168:    -- psl btr_fd_read_access_cov : cover 
3169:    -- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 340
Threshold: 1

PSL cover point on lines 3171 to 3172:

3171:    -- psl ewl_write_access_cov : cover 
3172:    -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))};

Count: 210
Threshold: 1

PSL cover point on lines 3174 to 3175:

3174:    -- psl ewl_read_access_cov : cover 
3175:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))};

Count: 13875
Threshold: 1

PSL cover point on lines 3177 to 3178:

3177:    -- psl erp_write_access_cov : cover 
3178:    -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))};

Count: 210
Threshold: 1

PSL cover point on lines 3180 to 3181:

3180:    -- psl erp_read_access_cov : cover 
3181:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))};

Count: 13875
Threshold: 1

PSL cover point on lines 3183 to 3184:

3183:    -- psl fault_state_read_access_cov : cover 
3184:    -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 111580
Threshold: 1

PSL cover point on lines 3186 to 3187:

3186:    -- psl rec_read_access_cov : cover 
3187:    -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 13109
Threshold: 1

PSL cover point on lines 3189 to 3190:

3189:    -- psl tec_read_access_cov : cover 
3190:    -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 13109
Threshold: 1

PSL cover point on lines 3192 to 3193:

3192:    -- psl err_norm_read_access_cov : cover 
3193:    -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))};

Count: 1221
Threshold: 1

PSL cover point on lines 3195 to 3196:

3195:    -- psl err_fd_read_access_cov : cover 
3196:    -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))};

Count: 1221
Threshold: 1

PSL cover point on lines 3198 to 3199:

3198:    -- psl ctr_pres_write_access_cov : cover 
3199:    -- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 43189
Threshold: 1

PSL cover point on lines 3201 to 3202:

3201:    -- psl filter_a_mask_write_access_cov : cover 
3202:    -- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 4064
Threshold: 1

PSL cover point on lines 3204 to 3205:

3204:    -- psl filter_a_mask_read_access_cov : cover 
3205:    -- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 18
Threshold: 1

PSL cover point on lines 3207 to 3208:

3207:    -- psl filter_a_val_write_access_cov : cover 
3208:    -- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 4064
Threshold: 1

PSL cover point on lines 3210 to 3211:

3210:    -- psl filter_a_val_read_access_cov : cover 
3211:    -- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 18
Threshold: 1

PSL cover point on lines 3213 to 3214:

3213:    -- psl filter_b_mask_write_access_cov : cover 
3214:    -- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};

Count: 2823
Threshold: 1