| Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| ADDRESS_DECODER_CONTROL_REGISTERS_COMP | 100.0 % (120/120) | 100.0 % (80/80) | 100.0 % (252/252) | 100.0 % (2/2) | N.A. | N.A. | 100.0 % (454/454) |
| MODE_RST_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| MODE_BMM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_STM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_AFM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_FDE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_TTTM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_ROM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_ACF_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_TSTM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_RXBAM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_TXBBM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_SAM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| MODE_ERFM_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_RTRLE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_RTRTH_REG_COMP | 100.0 % (17/17) | 100.0 % (24/24) | 100.0 % (34/34) | 100.0 % (19/19) | N.A. | N.A. | 100.0 % (94/94) |
| SETTINGS_ILBP_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_ENA_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_NISOFD_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_PEX_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_TBFBO_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_FDRF_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| SETTINGS_PCHKE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| COMMAND_RXRPMV_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_RRB_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_CDO_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_ERCRST_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_RXFCRST_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_TXFCRST_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_CPEXS_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_CRXPE_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_CTXPE_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| COMMAND_CTXDPE_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_RXI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_TXI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_EWLI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_DOI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_FCSI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_ALI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_BEI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_OFI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_RXFI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_BSI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_RBNEI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_STAT_TXBHCI_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| INT_ENA_SET_INT_ENA_SET_SLICE_1_REG_COMP | 100.0 % (25/25) | 100.0 % (16/16) | 100.0 % (58/58) | 100.0 % (19/19) | N.A. | N.A. | 100.0 % (118/118) |
| INT_ENA_SET_INT_ENA_SET_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (8/8) | 100.0 % (34/34) | 100.0 % (11/11) | N.A. | N.A. | 100.0 % (66/66) |
| INT_ENA_CLR_INT_ENA_CLR_SLICE_1_REG_COMP | 100.0 % (25/25) | 100.0 % (16/16) | 100.0 % (58/58) | 100.0 % (19/19) | N.A. | N.A. | 100.0 % (118/118) |
| INT_ENA_CLR_INT_ENA_CLR_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (8/8) | 100.0 % (34/34) | 100.0 % (11/11) | N.A. | N.A. | 100.0 % (66/66) |
| INT_MASK_SET_INT_MASK_SET_SLICE_1_REG_COMP | 100.0 % (25/25) | 100.0 % (16/16) | 100.0 % (58/58) | 100.0 % (19/19) | N.A. | N.A. | 100.0 % (118/118) |
| INT_MASK_SET_INT_MASK_SET_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (8/8) | 100.0 % (34/34) | 100.0 % (11/11) | N.A. | N.A. | 100.0 % (66/66) |
| INT_MASK_CLR_INT_MASK_CLR_SLICE_1_REG_COMP | 100.0 % (25/25) | 100.0 % (16/16) | 100.0 % (58/58) | 100.0 % (19/19) | N.A. | N.A. | 100.0 % (118/118) |
| INT_MASK_CLR_INT_MASK_CLR_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (8/8) | 100.0 % (34/34) | 100.0 % (11/11) | N.A. | N.A. | 100.0 % (66/66) |
| BTR_PROP_REG_COMP | 100.0 % (29/29) | 100.0 % (42/42) | 100.0 % (54/54) | 100.0 % (34/34) | N.A. | N.A. | 100.0 % (159/159) |
| BTR_PH1_SLICE_1_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (18/18) | 100.0 % (10/10) | N.A. | N.A. | 100.0 % (39/39) |
| BTR_PH1_SLICE_2_REG_COMP | 100.0 % (21/21) | 100.0 % (30/30) | 100.0 % (42/42) | 100.0 % (26/26) | N.A. | N.A. | 100.0 % (119/119) |
| BTR_PH2_SLICE_1_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (30/30) | 100.0 % (18/18) | N.A. | N.A. | 100.0 % (79/79) |
| BTR_PH2_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (30/30) | 100.0 % (18/18) | N.A. | N.A. | 100.0 % (79/79) |
| BTR_BRP_SLICE_1_REG_COMP | 100.0 % (21/21) | 100.0 % (30/30) | 100.0 % (42/42) | 100.0 % (26/26) | N.A. | N.A. | 100.0 % (119/119) |
| BTR_BRP_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (30/30) | 100.0 % (18/18) | N.A. | N.A. | 100.0 % (79/79) |
| BTR_SJW_REG_COMP | 100.0 % (21/21) | 100.0 % (30/30) | 100.0 % (42/42) | 100.0 % (26/26) | N.A. | N.A. | 100.0 % (119/119) |
| BTR_FD_PROP_FD_REG_COMP | 100.0 % (25/25) | 100.0 % (36/36) | 100.0 % (48/48) | 100.0 % (30/30) | N.A. | N.A. | 100.0 % (139/139) |
| BTR_FD_PH1_FD_SLICE_1_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (18/18) | 100.0 % (10/10) | N.A. | N.A. | 100.0 % (39/39) |
| BTR_FD_PH1_FD_SLICE_2_REG_COMP | 100.0 % (17/17) | 100.0 % (24/24) | 100.0 % (36/36) | 100.0 % (22/22) | N.A. | N.A. | 100.0 % (99/99) |
| BTR_FD_PH2_FD_SLICE_1_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (30/30) | 100.0 % (18/18) | N.A. | N.A. | 100.0 % (79/79) |
| BTR_FD_PH2_FD_SLICE_2_REG_COMP | 100.0 % (9/9) | 100.0 % (12/12) | 100.0 % (24/24) | 100.0 % (14/14) | N.A. | N.A. | 100.0 % (59/59) |
| BTR_FD_BRP_FD_SLICE_1_REG_COMP | 100.0 % (21/21) | 100.0 % (30/30) | 100.0 % (42/42) | 100.0 % (26/26) | N.A. | N.A. | 100.0 % (119/119) |
| BTR_FD_BRP_FD_SLICE_2_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (30/30) | 100.0 % (18/18) | N.A. | N.A. | 100.0 % (79/79) |
| BTR_FD_SJW_FD_REG_COMP | 100.0 % (21/21) | 100.0 % (30/30) | 100.0 % (42/42) | 100.0 % (26/26) | N.A. | N.A. | 100.0 % (119/119) |
| EWL_EW_LIMIT_REG_COMP | 100.0 % (33/33) | 100.0 % (48/48) | 100.0 % (60/60) | 100.0 % (38/38) | N.A. | N.A. | 100.0 % (179/179) |
| ERP_ERP_LIMIT_REG_COMP | 100.0 % (33/33) | 100.0 % (48/48) | 100.0 % (60/60) | 100.0 % (38/38) | N.A. | N.A. | 100.0 % (179/179) |
| CTR_PRES_CTPV_SLICE_1_REG_COMP | 100.0 % (33/33) | 100.0 % (48/48) | 100.0 % (60/60) | 100.0 % (38/38) | N.A. | N.A. | 100.0 % (179/179) |
| CTR_PRES_CTPV_SLICE_2_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (18/18) | 100.0 % (10/10) | N.A. | N.A. | 100.0 % (39/39) |
| CTR_PRES_PTX_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (18/18) | 100.0 % (8/8) | N.A. | N.A. | 100.0 % (32/32) |
| CTR_PRES_PRX_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (18/18) | 100.0 % (8/8) | N.A. | N.A. | 100.0 % (32/32) |
| CTR_PRES_ENORM_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (18/18) | 100.0 % (8/8) | N.A. | N.A. | 100.0 % (32/32) |
| CTR_PRES_EFD_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (18/18) | 100.0 % (8/8) | N.A. | N.A. | 100.0 % (32/32) |
| FILTER_A_MASK_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_A_VAL_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_B_MASK_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_B_VAL_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_C_MASK_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_C_VAL_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_RAN_LOW_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_RAN_HIGH_PRESENT_GEN_T | 100.0 % (120/120) | 100.0 % (174/174) | 100.0 % (214/214) | 100.0 % (128/128) | N.A. | N.A. | 100.0 % (636/636) |
| FILTER_CONTROL_FANB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FANE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FAFB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FAFE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FBNB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FBNE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FBFB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FBFE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FCNB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FCNE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FCFB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FCFE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FRNB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FRNE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FRFB_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| FILTER_CONTROL_FRFE_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| RX_SETTINGS_RTSOP_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| RX_DATA_ACCESS_SIGNALLER_COMP | 100.0 % (3/3) | 100.0 % (2/2) | 100.0 % (18/18) | 100.0 % (3/3) | N.A. | N.A. | 100.0 % (26/26) |
| TX_COMMAND_TXCE_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| TX_COMMAND_TXCR_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| TX_COMMAND_TXCA_REG_COMP | 100.0 % (4/4) | 100.0 % (2/2) | 100.0 % (16/16) | 100.0 % (5/5) | N.A. | N.A. | 100.0 % (27/27) |
| TX_COMMAND_TXB1_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB2_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB3_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB4_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB5_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB6_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB7_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_COMMAND_TXB8_REG_COMP | 100.0 % (5/5) | 100.0 % (6/6) | 100.0 % (16/16) | 100.0 % (7/7) | N.A. | N.A. | 100.0 % (34/34) |
| TX_PRIORITY_TXT1P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT2P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT3P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT4P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT5P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT6P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT7P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| TX_PRIORITY_TXT8P_REG_COMP | 100.0 % (13/13) | 100.0 % (18/18) | 100.0 % (28/28) | 100.0 % (15/15) | N.A. | N.A. | 100.0 % (74/74) |
| SSP_CFG_SSP_OFFSET_REG_COMP | 100.0 % (33/33) | 100.0 % (48/48) | 100.0 % (60/60) | 100.0 % (38/38) | N.A. | N.A. | 100.0 % (179/179) |
| SSP_CFG_SSP_SRC_REG_COMP | 100.0 % (9/9) | 100.0 % (12/12) | 100.0 % (24/24) | 100.0 % (14/14) | N.A. | N.A. | 100.0 % (59/59) |
| FILTER_B_MASK_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_B_VAL_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_C_MASK_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_C_VAL_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_RAN_LOW_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_RAN_HIGH_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_A_MASK_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| FILTER_A_VAL_PRESENT_GEN_F | 100.0 % (1/1) | N.A. | N.A. | N.A. | N.A. | N.A. | 100.0 % (1/1) |
| Instance | Statement | Branch | Toggle | Expression | FSM state | Functional | Average |
|---|---|---|---|---|---|---|---|
| CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP | 100.0 % (50/50) | 100.0 % (48/48) | 100.0 % (3270/3270) | 100.0 % (16/16) | N.A. | 100.0 % (73/73) | 100.0 % (3457/3457) |
121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); 121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); 121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); 2872: with address(7 downto 2) select r_data_comb <=
2873: control_registers_in.version_ver_major &
...
3078: control_registers_in.timestamp_high_timestamp_high when "100110",
3079: (others => '0') when others; 2873: control_registers_in.version_ver_major &
2874: control_registers_in.version_ver_minor &
2875: control_registers_in.device_id_device_id when "000000", 2876: '0' & '0' & '0' & '0' &
2877: control_registers_out_i.settings_pchke &
...
2898: control_registers_out_i.mode_bmm &
2899: control_registers_out_i.mode_rst when "000001", 2900: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2901: control_registers_in.status_sprt &
...
2915: control_registers_in.status_dor &
2916: control_registers_in.status_rxne when "000010", 2917: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011", 2918: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2919: control_registers_in.int_stat_txbhci &
...
2929: control_registers_in.int_stat_txi &
2930: control_registers_in.int_stat_rxi when "000100", 2931: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2932: control_registers_in.int_ena_set_int_ena_set when "000101", 2933: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110", 2934: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2935: control_registers_in.int_mask_set_int_mask_set when "000111", 2936: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000", 2937: control_registers_out_i.btr_sjw &
2938: control_registers_out_i.btr_brp &
2939: control_registers_out_i.btr_ph2 &
2940: control_registers_out_i.btr_ph1 &
2941: control_registers_out_i.btr_prop when "001001", 2942: control_registers_out_i.btr_fd_sjw_fd &
2943: control_registers_out_i.btr_fd_brp_fd &
...
2948: '0' &
2949: control_registers_out_i.btr_fd_prop_fd when "001010", 2950: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2951: control_registers_in.fault_state_bof &
2952: control_registers_in.fault_state_erp &
2953: control_registers_in.fault_state_era &
2954: control_registers_out_i.erp_erp_limit &
2955: control_registers_out_i.ewl_ew_limit when "001011", 2956: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2957: control_registers_in.tec_tec_val &
2958: '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2959: control_registers_in.rec_rec_val when "001100", 2960: control_registers_in.err_fd_err_fd_val &
2961: control_registers_in.err_norm_err_norm_val when "001101", 2962: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110", 2963: '0' & '0' & '0' &
2964: control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111", 2965: '0' & '0' & '0' &
2966: control_registers_out_i.filter_a_val_bit_val_a_val when "010000", 2967: '0' & '0' & '0' &
2968: control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001", 2969: '0' & '0' & '0' &
2970: control_registers_out_i.filter_b_val_bit_val_b_val when "010010", 2971: '0' & '0' & '0' &
2972: control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011", 2973: '0' & '0' & '0' &
2974: control_registers_out_i.filter_c_val_bit_val_c_val when "010100", 2975: '0' & '0' & '0' &
2976: control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101", 2977: '0' & '0' & '0' &
2978: control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110", 2979: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
2980: control_registers_in.filter_status_sfr &
...
2998: control_registers_out_i.filter_control_fane &
2999: control_registers_out_i.filter_control_fanb when "010111", 3000: '0' & '0' & '0' &
3001: control_registers_in.rx_mem_info_rx_mem_free &
3002: '0' & '0' & '0' &
3003: control_registers_in.rx_mem_info_rx_buff_size when "011000", 3004: '0' & '0' & '0' & '0' &
3005: control_registers_in.rx_pointers_rx_rpp &
3006: '0' & '0' & '0' & '0' &
3007: control_registers_in.rx_pointers_rx_wpp when "011001", 3008: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3009: control_registers_out_i.rx_settings_rtsop &
...
3014: control_registers_in.rx_status_rxf &
3015: control_registers_in.rx_status_rxe when "011010", 3016: control_registers_in.rx_data_rx_data when "011011", 3017: control_registers_in.tx_status_tx8s &
3018: control_registers_in.tx_status_tx7s &
...
3023: control_registers_in.tx_status_tx2s &
3024: control_registers_in.tx_status_tx1s when "011100", 3025: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3026: control_registers_in.txtb_info_txt_buffer_count &
3027: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101", 3028: '0' &
3029: control_registers_out_i.tx_priority_txt8p &
...
3042: '0' &
3043: control_registers_out_i.tx_priority_txt1p when "011110", 3044: '0' & '0' &
3045: control_registers_in.ts_info_ts_bits &
...
3051: control_registers_in.err_capt_err_erp &
3052: control_registers_in.err_capt_err_pos when "011111", 3053: '0' & '0' & '0' & '0' & '0' & '0' &
3054: control_registers_out_i.ssp_cfg_ssp_src &
3055: control_registers_out_i.ssp_cfg_ssp_offset &
3056: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3057: control_registers_in.trv_delay_trv_delay_value when "100000", 3058: control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001", 3059: control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010", 3060: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
3061: control_registers_in.debug_register_pc_sof &
...
3074: control_registers_in.debug_register_destuff_count &
3075: control_registers_in.debug_register_stuff_count when "100011", 3076: control_registers_in.yolo_reg_yolo_val when "100100", 3077: control_registers_in.timestamp_low_timestamp_low when "100101", 3078: control_registers_in.timestamp_high_timestamp_high when "100110", 3079: (others => '0') when others; 3086: if (res_n = '0') then
3087: r_data <= (others => '0');
...
3091: end if;
3092: end if; 3087: r_data <= (others => '0'); 3089: if (cs = '1' and read = '1') then
3090: r_data <= r_data_comb and read_data_mask_n;
3091: end if; 3090: r_data <= r_data_comb and read_data_mask_n; 3099: be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &
3100: be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &
3101: be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &
3102: be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ; 3104: Control_registers_out <= Control_registers_out_i; 121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 152620 | 1 |
| Bin | False | 94769796 | 1 |
2875: control_registers_in.device_id_device_id when "000000", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000000" | 270762 | 1 |
2899: control_registers_out_i.mode_rst when "000001", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000001" | 559867 | 1 |
2916: control_registers_in.status_rxne when "000010", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000010" | 19364193 | 1 |
2917: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000011", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000011" | 299370 | 1 |
2930: control_registers_in.int_stat_rxi when "000100", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000100" | 112149 | 1 |
2932: control_registers_in.int_ena_set_int_ena_set when "000101", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000101" | 69004 | 1 |
2933: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "000110", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000110" | 56496 | 1 |
2935: control_registers_in.int_mask_set_int_mask_set when "000111", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "000111" | 55317 | 1 |
2936: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001000", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001000" | 54429 | 1 |
2941: control_registers_out_i.btr_prop when "001001", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001001" | 70944 | 1 |
2949: control_registers_out_i.btr_fd_prop_fd when "001010", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001010" | 69995 | 1 |
2955: control_registers_out_i.ewl_ew_limit when "001011", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001011" | 283628 | 1 |
2959: control_registers_in.rec_rec_val when "001100", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001100" | 80916 | 1 |
2961: control_registers_in.err_norm_err_norm_val when "001101", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001101" | 57033 | 1 |
2962: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "001110", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001110" | 151737 | 1 |
2964: control_registers_out_i.filter_a_mask_bit_mask_a_val when "001111", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "001111" | 59202 | 1 |
2966: control_registers_out_i.filter_a_val_bit_val_a_val when "010000", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010000" | 58584 | 1 |
2968: control_registers_out_i.filter_b_mask_bit_mask_b_val when "010001", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010001" | 56088 | 1 |
2970: control_registers_out_i.filter_b_val_bit_val_b_val when "010010", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010010" | 56088 | 1 |
2972: control_registers_out_i.filter_c_mask_bit_mask_c_val when "010011", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010011" | 56089 | 1 |
2974: control_registers_out_i.filter_c_val_bit_val_c_val when "010100", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010100" | 53625 | 1 |
2976: control_registers_out_i.filter_ran_low_bit_ran_low_val when "010101", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010101" | 140 | 1 |
2978: control_registers_out_i.filter_ran_high_bit_ran_high_val when "010110", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010110" | 140 | 1 |
2999: control_registers_out_i.filter_control_fanb when "010111", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "010111" | 40136 | 1 |
3003: control_registers_in.rx_mem_info_rx_buff_size when "011000", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011000" | 25454 | 1 |
3007: control_registers_in.rx_pointers_rx_wpp when "011001", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011001" | 25316 | 1 |
3015: control_registers_in.rx_status_rxe when "011010", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011010" | 26856 | 1 |
3016: control_registers_in.rx_data_rx_data when "011011", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011011" | 219341 | 1 |
3024: control_registers_in.tx_status_tx1s when "011100", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011100" | 36320 | 1 |
3027: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' when "011101", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011101" | 85677 | 1 |
3043: control_registers_out_i.tx_priority_txt1p when "011110", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011110" | 8132 | 1 |
3052: control_registers_in.err_capt_err_pos when "011111", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "011111" | 3564 | 1 |
3057: control_registers_in.trv_delay_trv_delay_value when "100000", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100000" | 11864 | 1 |
3058: control_registers_in.rx_fr_ctr_rx_fr_ctr_val when "100001", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100001" | 2346 | 1 |
3059: control_registers_in.tx_fr_ctr_tx_fr_ctr_val when "100010", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100010" | 2268 | 1 |
3075: control_registers_in.debug_register_stuff_count when "100011", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100011" | 33611875 | 1 |
3076: control_registers_in.yolo_reg_yolo_val when "100100", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100100" | 90 | 1 |
3077: control_registers_in.timestamp_low_timestamp_low when "100101", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100101" | 7870 | 1 |
3078: control_registers_in.timestamp_high_timestamp_high when "100110", | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | "100110" | 7870 | 1 |
3079: (others => '0') when others; | Choice of | Count | Threshold | |
|---|---|---|---|
| Bin | others | 529299040 | 1 |
3086: if (res_n = '0') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 17943 | 1 |
| Bin | False | 62060461 | 1 |
3088: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 31024796 | 1 |
| Bin | False | 31035665 | 1 |
3089: if (cs = '1' and read = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | True | 19512879 | 1 |
| Bin | False | 11511917 | 1 |
ADDRESS(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
ADDRESS(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(15)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(14)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(13)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(12)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(11)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(10)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(9)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(8)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(7)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(6)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(5)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(7)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(6)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(5)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(7)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(6)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(5)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.STATUS_STRGS| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(11)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(10)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(9)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(8)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(6)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TXTB_INFO_TXT_BUFFER_COUNT(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(5)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(31)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(30)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(29)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(28)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(27)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(26)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(25)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(24)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(23)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(22)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(21)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(20)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(19)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(18)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(17)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(16)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(15)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(14)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(13)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(12)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(11)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(10)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(9)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(8)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(7)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(6)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(5)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(4)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 0 | 1 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(3)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(2)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(1)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(0)| From | To | Count | Threshold | Excluded due to | |
|---|---|---|---|---|---|
| Bin | 1 | 0 | 0 | 1 | Exclude file |
CLK_SYS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31028760 | 1 |
| Bin | 1 | 0 | 31030360 | 1 |
RES_N| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9642 | 1 |
| Bin | 1 | 0 | 8042 | 1 |
ADDRESS(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16744778 | 1 |
| Bin | 1 | 0 | 11049255 | 1 |
ADDRESS(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27465473 | 1 |
ADDRESS(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27217934 | 1 |
ADDRESS(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27357954 | 1 |
ADDRESS(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 778796 | 1 |
ADDRESS(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10138784 | 1 |
ADDRESS(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 27794033 | 1 |
ADDRESS(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 27794033 | 1 |
W_DATA(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61362 | 1 |
| Bin | 1 | 0 | 1028483 | 1 |
W_DATA(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67108 | 1 |
| Bin | 1 | 0 | 1022737 | 1 |
W_DATA(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63097 | 1 |
| Bin | 1 | 0 | 1026748 | 1 |
W_DATA(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 91439 | 1 |
| Bin | 1 | 0 | 998406 | 1 |
W_DATA(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79643 | 1 |
| Bin | 1 | 0 | 1010202 | 1 |
W_DATA(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76527 | 1 |
| Bin | 1 | 0 | 1013318 | 1 |
W_DATA(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88276 | 1 |
| Bin | 1 | 0 | 1001569 | 1 |
W_DATA(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 78188 | 1 |
| Bin | 1 | 0 | 1011657 | 1 |
W_DATA(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70931 | 1 |
| Bin | 1 | 0 | 1018914 | 1 |
W_DATA(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 108138 | 1 |
| Bin | 1 | 0 | 981707 | 1 |
W_DATA(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 74867 | 1 |
| Bin | 1 | 0 | 1014978 | 1 |
W_DATA(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80468 | 1 |
| Bin | 1 | 0 | 1009377 | 1 |
W_DATA(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 110009 | 1 |
| Bin | 1 | 0 | 979836 | 1 |
W_DATA(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 131558 | 1 |
| Bin | 1 | 0 | 958287 | 1 |
W_DATA(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 123951 | 1 |
| Bin | 1 | 0 | 965894 | 1 |
W_DATA(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 193513 | 1 |
| Bin | 1 | 0 | 896332 | 1 |
W_DATA(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72382 | 1 |
| Bin | 1 | 0 | 1017463 | 1 |
W_DATA(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 86120 | 1 |
| Bin | 1 | 0 | 1003725 | 1 |
W_DATA(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76572 | 1 |
| Bin | 1 | 0 | 1013273 | 1 |
W_DATA(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80428 | 1 |
| Bin | 1 | 0 | 1009417 | 1 |
W_DATA(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 97296 | 1 |
| Bin | 1 | 0 | 992549 | 1 |
W_DATA(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116973 | 1 |
| Bin | 1 | 0 | 972872 | 1 |
W_DATA(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 170870 | 1 |
| Bin | 1 | 0 | 918975 | 1 |
W_DATA(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 150526 | 1 |
| Bin | 1 | 0 | 939319 | 1 |
W_DATA(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 126416 | 1 |
| Bin | 1 | 0 | 963429 | 1 |
W_DATA(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109550 | 1 |
| Bin | 1 | 0 | 980295 | 1 |
W_DATA(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103929 | 1 |
| Bin | 1 | 0 | 985916 | 1 |
W_DATA(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 162358 | 1 |
| Bin | 1 | 0 | 927487 | 1 |
W_DATA(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 135873 | 1 |
| Bin | 1 | 0 | 953972 | 1 |
W_DATA(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 159944 | 1 |
| Bin | 1 | 0 | 929901 | 1 |
W_DATA(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 236123 | 1 |
| Bin | 1 | 0 | 853722 | 1 |
W_DATA(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 198401 | 1 |
| Bin | 1 | 0 | 891444 | 1 |
R_DATA(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5224 | 1 |
| Bin | 1 | 0 | 6824 | 1 |
R_DATA(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6100 | 1 |
| Bin | 1 | 0 | 7700 | 1 |
R_DATA(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5423 | 1 |
| Bin | 1 | 0 | 7023 | 1 |
R_DATA(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11482 | 1 |
| Bin | 1 | 0 | 13082 | 1 |
R_DATA(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13643 | 1 |
| Bin | 1 | 0 | 15243 | 1 |
R_DATA(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11543 | 1 |
| Bin | 1 | 0 | 13143 | 1 |
R_DATA(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19041 | 1 |
| Bin | 1 | 0 | 20641 | 1 |
R_DATA(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16781 | 1 |
| Bin | 1 | 0 | 18381 | 1 |
R_DATA(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20480 | 1 |
| Bin | 1 | 0 | 22080 | 1 |
R_DATA(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29175 | 1 |
| Bin | 1 | 0 | 30774 | 1 |
R_DATA(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 17455 | 1 |
| Bin | 1 | 0 | 19055 | 1 |
R_DATA(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21355 | 1 |
| Bin | 1 | 0 | 22955 | 1 |
R_DATA(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22707 | 1 |
| Bin | 1 | 0 | 24307 | 1 |
R_DATA(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77800 | 1 |
| Bin | 1 | 0 | 79400 | 1 |
R_DATA(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66021 | 1 |
| Bin | 1 | 0 | 67621 | 1 |
R_DATA(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66382 | 1 |
| Bin | 1 | 0 | 67974 | 1 |
R_DATA(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30606 | 1 |
| Bin | 1 | 0 | 32198 | 1 |
R_DATA(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22060 | 1 |
| Bin | 1 | 0 | 23660 | 1 |
R_DATA(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25536 | 1 |
| Bin | 1 | 0 | 27136 | 1 |
R_DATA(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31879 | 1 |
| Bin | 1 | 0 | 33479 | 1 |
R_DATA(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33086 | 1 |
| Bin | 1 | 0 | 34686 | 1 |
R_DATA(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 34023 | 1 |
| Bin | 1 | 0 | 35623 | 1 |
R_DATA(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 34788 | 1 |
| Bin | 1 | 0 | 36386 | 1 |
R_DATA(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 35789 | 1 |
| Bin | 1 | 0 | 37388 | 1 |
R_DATA(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 57263 | 1 |
| Bin | 1 | 0 | 58863 | 1 |
R_DATA(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55124 | 1 |
| Bin | 1 | 0 | 56716 | 1 |
R_DATA(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 69445 | 1 |
| Bin | 1 | 0 | 71037 | 1 |
R_DATA(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66460 | 1 |
| Bin | 1 | 0 | 68058 | 1 |
R_DATA(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75973 | 1 |
| Bin | 1 | 0 | 77573 | 1 |
R_DATA(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 64541 | 1 |
| Bin | 1 | 0 | 66141 | 1 |
R_DATA(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42139 | 1 |
| Bin | 1 | 0 | 43739 | 1 |
R_DATA(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 45262 | 1 |
| Bin | 1 | 0 | 46862 | 1 |
CS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19665575 | 1 |
| Bin | 1 | 0 | 19667175 | 1 |
READ| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26704188 | 1 |
| Bin | 1 | 0 | 1089845 | 1 |
WRITE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1089845 | 1 |
| Bin | 1 | 0 | 26704188 | 1 |
BE(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
BE(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
BE(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
BE(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
LOCK_1| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2626 | 1 |
| Bin | 1 | 0 | 1027 | 1 |
LOCK_2| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
CONTROL_REGISTERS_OUT.MODE_RST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 867 | 1 |
| Bin | 1 | 0 | 32865 | 1 |
CONTROL_REGISTERS_OUT.MODE_BMM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_OUT.MODE_STM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
CONTROL_REGISTERS_OUT.MODE_AFM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
CONTROL_REGISTERS_OUT.MODE_FDE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1800 | 1 |
| Bin | 1 | 0 | 200 | 1 |
CONTROL_REGISTERS_OUT.MODE_TTTM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_OUT.MODE_ROM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
CONTROL_REGISTERS_OUT.MODE_ACF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
CONTROL_REGISTERS_OUT.MODE_TSTM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 2626 | 1 |
CONTROL_REGISTERS_OUT.MODE_RXBAM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1730 | 1 |
| Bin | 1 | 0 | 130 | 1 |
CONTROL_REGISTERS_OUT.MODE_TXBBM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
CONTROL_REGISTERS_OUT.MODE_SAM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_OUT.MODE_ERFM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 153 | 1 |
| Bin | 1 | 0 | 1753 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_RTRLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2454 | 1 |
| Bin | 1 | 0 | 4054 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_RTRTH(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_RTRTH(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_RTRTH(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_RTRTH(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_ILBP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_ENA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_NISOFD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_PEX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1672 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_TBFBO| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2533 | 1 |
| Bin | 1 | 0 | 943 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_FDRF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 1604 | 1 |
CONTROL_REGISTERS_OUT.SETTINGS_PCHKE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_RXRPMV| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_RRB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 460 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_CDO| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_ERCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_RXFCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_TXFCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_CPEXS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_CRXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_CTXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 440 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.COMMAND_CTXDPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_RXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_TXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_EWLI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_DOI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_FCSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_ALI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_BEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_OFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_RXFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_BSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_RBNEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_STAT_TXBHCI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_SET_INT_ENA_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 476 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 512 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 492 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_ENA_CLR_INT_ENA_CLR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_SET_INT_MASK_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 435 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 425 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 460 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.INT_MASK_CLR_INT_MASK_CLR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 312 | 1 |
| Bin | 1 | 0 | 1909 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 223 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 273 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3820 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 261 | 1 |
| Bin | 1 | 0 | 1858 | 1 |
CONTROL_REGISTERS_OUT.BTR_PROP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1793 | 1 |
| Bin | 1 | 0 | 194 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 316 | 1 |
| Bin | 1 | 0 | 1914 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 250 | 1 |
| Bin | 1 | 0 | 1848 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 259 | 1 |
| Bin | 1 | 0 | 1857 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1304 | 1 |
| Bin | 1 | 0 | 2896 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1927 | 1 |
| Bin | 1 | 0 | 328 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH1(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2088 | 1 |
| Bin | 1 | 0 | 490 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 204 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 347 | 1 |
| Bin | 1 | 0 | 1944 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 314 | 1 |
| Bin | 1 | 0 | 1912 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3872 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3411 | 1 |
| Bin | 1 | 0 | 5003 | 1 |
CONTROL_REGISTERS_OUT.BTR_PH2(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2161 | 1 |
| Bin | 1 | 0 | 561 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 1612 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 1613 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1617 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4831 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 928 | 1 |
| Bin | 1 | 0 | 2523 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4762 | 1 |
| Bin | 1 | 0 | 3169 | 1 |
CONTROL_REGISTERS_OUT.BTR_BRP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2315 | 1 |
| Bin | 1 | 0 | 3912 | 1 |
CONTROL_REGISTERS_OUT.BTR_SJW(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT.BTR_SJW(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 269 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
CONTROL_REGISTERS_OUT.BTR_SJW(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 966 | 1 |
| Bin | 1 | 0 | 2563 | 1 |
CONTROL_REGISTERS_OUT.BTR_SJW(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2625 | 1 |
| Bin | 1 | 0 | 1032 | 1 |
CONTROL_REGISTERS_OUT.BTR_SJW(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3116 | 1 |
| Bin | 1 | 0 | 4713 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 1840 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 286 | 1 |
| Bin | 1 | 0 | 1883 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1185 | 1 |
| Bin | 1 | 0 | 2775 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4706 | 1 |
| Bin | 1 | 0 | 3113 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PROP_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3890 | 1 |
| Bin | 1 | 0 | 2290 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH1_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 253 | 1 |
| Bin | 1 | 0 | 1851 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH1_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 284 | 1 |
| Bin | 1 | 0 | 1882 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH1_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1179 | 1 |
| Bin | 1 | 0 | 2770 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH1_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1697 | 1 |
| Bin | 1 | 0 | 98 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH1_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3840 | 1 |
| Bin | 1 | 0 | 2241 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH2_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 281 | 1 |
| Bin | 1 | 0 | 1879 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH2_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 321 | 1 |
| Bin | 1 | 0 | 1919 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH2_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1212 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH2_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1732 | 1 |
| Bin | 1 | 0 | 133 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_PH2_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3871 | 1 |
| Bin | 1 | 0 | 2271 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4843 | 1 |
| Bin | 1 | 0 | 3253 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 758 | 1 |
| Bin | 1 | 0 | 2356 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_BRP_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2600 | 1 |
| Bin | 1 | 0 | 4192 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_SJW_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 236 | 1 |
| Bin | 1 | 0 | 1833 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_SJW_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_SJW_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 929 | 1 |
| Bin | 1 | 0 | 2526 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_SJW_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2558 | 1 |
| Bin | 1 | 0 | 965 | 1 |
CONTROL_REGISTERS_OUT.BTR_FD_SJW_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 949 | 1 |
| Bin | 1 | 0 | 2546 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 78 | 1 |
| Bin | 1 | 0 | 1678 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1686 | 1 |
| Bin | 1 | 0 | 86 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 70 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
CONTROL_REGISTERS_OUT.EWL_EW_LIMIT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1736 | 1 |
| Bin | 1 | 0 | 136 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT.ERP_ERP_LIMIT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 264 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2166 | 1 |
| Bin | 1 | 0 | 3766 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 683 | 1 |
| Bin | 1 | 0 | 2283 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2181 | 1 |
| Bin | 1 | 0 | 3781 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2332 | 1 |
| Bin | 1 | 0 | 3932 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 919 | 1 |
| Bin | 1 | 0 | 2519 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2414 | 1 |
| Bin | 1 | 0 | 4014 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1008 | 1 |
| Bin | 1 | 0 | 2608 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_CTPV(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_PTX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18698 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_PRX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19085 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_ENORM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT.CTR_PRES_EFD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2012 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 334 | 1 |
| Bin | 1 | 0 | 1934 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 358 | 1 |
| Bin | 1 | 0 | 1958 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 362 | 1 |
| Bin | 1 | 0 | 1962 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 1990 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 387 | 1 |
| Bin | 1 | 0 | 1987 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 344 | 1 |
| Bin | 1 | 0 | 1944 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 376 | 1 |
| Bin | 1 | 0 | 1976 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2012 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 123 | 1 |
| Bin | 1 | 0 | 1723 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 1856 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 1867 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 1867 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 1882 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 1843 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 276 | 1 |
| Bin | 1 | 0 | 1876 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 265 | 1 |
| Bin | 1 | 0 | 1865 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 274 | 1 |
| Bin | 1 | 0 | 1874 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 234 | 1 |
| Bin | 1 | 0 | 1834 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_MASK_BIT_MASK_A_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1896 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 786 | 1 |
| Bin | 1 | 0 | 2386 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 850 | 1 |
| Bin | 1 | 0 | 2450 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 738 | 1 |
| Bin | 1 | 0 | 2338 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 782 | 1 |
| Bin | 1 | 0 | 2382 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 837 | 1 |
| Bin | 1 | 0 | 2437 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 822 | 1 |
| Bin | 1 | 0 | 2422 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 781 | 1 |
| Bin | 1 | 0 | 2381 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 816 | 1 |
| Bin | 1 | 0 | 2416 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 814 | 1 |
| Bin | 1 | 0 | 2414 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 1997 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 1997 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 433 | 1 |
| Bin | 1 | 0 | 2033 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2009 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 375 | 1 |
| Bin | 1 | 0 | 1975 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 458 | 1 |
| Bin | 1 | 0 | 2058 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2005 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 385 | 1 |
| Bin | 1 | 0 | 1985 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 381 | 1 |
| Bin | 1 | 0 | 1981 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 399 | 1 |
| Bin | 1 | 0 | 1999 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2005 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 415 | 1 |
| Bin | 1 | 0 | 2015 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2017 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2007 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 416 | 1 |
| Bin | 1 | 0 | 2016 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 378 | 1 |
| Bin | 1 | 0 | 1978 | 1 |
CONTROL_REGISTERS_OUT.FILTER_A_VAL_BIT_VAL_A_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2017 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1689 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1688 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 113 | 1 |
| Bin | 1 | 0 | 1713 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1692 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1671 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 39 | 1 |
| Bin | 1 | 0 | 1639 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1666 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_MASK_BIT_MASK_B_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 81 | 1 |
| Bin | 1 | 0 | 1681 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 188 | 1 |
| Bin | 1 | 0 | 1788 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 193 | 1 |
| Bin | 1 | 0 | 1793 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 1784 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 225 | 1 |
| Bin | 1 | 0 | 1825 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 190 | 1 |
| Bin | 1 | 0 | 1790 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 215 | 1 |
| Bin | 1 | 0 | 1815 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 210 | 1 |
| Bin | 1 | 0 | 1810 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 200 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1805 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 218 | 1 |
| Bin | 1 | 0 | 1818 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 118 | 1 |
| Bin | 1 | 0 | 1718 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1692 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 121 | 1 |
| Bin | 1 | 0 | 1721 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1689 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 90 | 1 |
| Bin | 1 | 0 | 1690 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 113 | 1 |
| Bin | 1 | 0 | 1713 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_B_VAL_BIT_VAL_B_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 93 | 1 |
| Bin | 1 | 0 | 1693 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1688 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 90 | 1 |
| Bin | 1 | 0 | 1690 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1692 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 122 | 1 |
| Bin | 1 | 0 | 1722 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 36 | 1 |
| Bin | 1 | 0 | 1636 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 1643 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1659 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1671 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_MASK_BIT_MASK_C_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1816 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 189 | 1 |
| Bin | 1 | 0 | 1789 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1805 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1799 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1816 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1799 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 196 | 1 |
| Bin | 1 | 0 | 1796 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 1715 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 1716 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 117 | 1 |
| Bin | 1 | 0 | 1717 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1680 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1685 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 112 | 1 |
| Bin | 1 | 0 | 1712 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_C_VAL_BIT_VAL_C_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 128 | 1 |
| Bin | 1 | 0 | 1728 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FANB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2051 | 1 |
| Bin | 1 | 0 | 451 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FANE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2028 | 1 |
| Bin | 1 | 0 | 428 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FAFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2059 | 1 |
| Bin | 1 | 0 | 459 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FAFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2028 | 1 |
| Bin | 1 | 0 | 428 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FBNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FBNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FBFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FBFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FCNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FCNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FCFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FCFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FRNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6 | 1 |
| Bin | 1 | 0 | 1606 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FRNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FRFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6 | 1 |
| Bin | 1 | 0 | 1606 | 1 |
CONTROL_REGISTERS_OUT.FILTER_CONTROL_FRFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT.RX_SETTINGS_RTSOP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT.RX_DATA_READ| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51733 | 1 |
| Bin | 1 | 0 | 53333 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXCE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXCR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20943 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXCA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB1| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6540 | 1 |
| Bin | 1 | 0 | 8136 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB2| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5586 | 1 |
| Bin | 1 | 0 | 7186 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB3| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 333 | 1 |
| Bin | 1 | 0 | 1933 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB4| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 345 | 1 |
| Bin | 1 | 0 | 1945 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB5| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1689 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB6| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB7| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 84 | 1 |
| Bin | 1 | 0 | 1684 | 1 |
CONTROL_REGISTERS_OUT.TX_COMMAND_TXB8| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT1P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT1P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 1716 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT1P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1726 | 1 |
| Bin | 1 | 0 | 126 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT2P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT2P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 127 | 1 |
| Bin | 1 | 0 | 1727 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT2P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 1724 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT3P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT3P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT3P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT4P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT4P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT4P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 93 | 1 |
| Bin | 1 | 0 | 1693 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT5P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT5P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 24 | 1 |
| Bin | 1 | 0 | 1624 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT5P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT6P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 23 | 1 |
| Bin | 1 | 0 | 1623 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT6P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT6P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT7P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT7P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT7P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT8P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT8P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT.TX_PRIORITY_TXT8P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4305 | 1 |
| Bin | 1 | 0 | 2715 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2127 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2899 | 1 |
| Bin | 1 | 0 | 1309 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_OFFSET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2397 | 1 |
| Bin | 1 | 0 | 3997 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_SRC(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
CONTROL_REGISTERS_OUT.SSP_CFG_SSP_SRC(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 817 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.DEVICE_ID_DEVICE_ID(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MINOR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.VERSION_VER_MAJOR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.STATUS_RXNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8950 | 1 |
| Bin | 1 | 0 | 8948 | 1 |
CONTROL_REGISTERS_IN.STATUS_DOR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
CONTROL_REGISTERS_IN.STATUS_TXNF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2469 | 1 |
| Bin | 1 | 0 | 2469 | 1 |
CONTROL_REGISTERS_IN.STATUS_EFT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26658 | 1 |
| Bin | 1 | 0 | 28253 | 1 |
CONTROL_REGISTERS_IN.STATUS_RXS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30888 | 1 |
| Bin | 1 | 0 | 32482 | 1 |
CONTROL_REGISTERS_IN.STATUS_TXS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19892 | 1 |
| Bin | 1 | 0 | 21492 | 1 |
CONTROL_REGISTERS_IN.STATUS_EWL| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
CONTROL_REGISTERS_IN.STATUS_IDLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51012 | 1 |
| Bin | 1 | 0 | 51018 | 1 |
CONTROL_REGISTERS_IN.STATUS_PEXS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
CONTROL_REGISTERS_IN.STATUS_RXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.STATUS_TXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 309 | 1 |
| Bin | 1 | 0 | 1909 | 1 |
CONTROL_REGISTERS_IN.STATUS_TXDPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
CONTROL_REGISTERS_IN.STATUS_STCNT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 660 | 1 |
| Bin | 1 | 0 | 940 | 1 |
CONTROL_REGISTERS_IN.STATUS_STRGS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.STATUS_SPRT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 660 | 1 |
| Bin | 1 | 0 | 940 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_RXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 809 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_TXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1214 | 1 |
| Bin | 1 | 0 | 2810 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_EWLI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 597 | 1 |
| Bin | 1 | 0 | 2196 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_DOI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_FCSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3303 | 1 |
| Bin | 1 | 0 | 4893 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_ALI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_BEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1413 | 1 |
| Bin | 1 | 0 | 3007 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_OFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_RXFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_BSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1326 | 1 |
| Bin | 1 | 0 | 2921 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_RBNEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 937 | 1 |
| Bin | 1 | 0 | 2535 | 1 |
CONTROL_REGISTERS_IN.INT_STAT_TXBHCI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1679 | 1 |
| Bin | 1 | 0 | 3275 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1666 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_ENA_SET_INT_ENA_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1610 | 1 |
CONTROL_REGISTERS_IN.INT_MASK_SET_INT_MASK_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 1610 | 1 |
CONTROL_REGISTERS_IN.FAULT_STATE_ERA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8424 | 1 |
| Bin | 1 | 0 | 8415 | 1 |
CONTROL_REGISTERS_IN.FAULT_STATE_ERP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2368 | 1 |
CONTROL_REGISTERS_IN.FAULT_STATE_BOF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 1736 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 360 | 1 |
| Bin | 1 | 0 | 1960 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 1864 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 332 | 1 |
| Bin | 1 | 0 | 1931 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 519 | 1 |
| Bin | 1 | 0 | 2119 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 686 | 1 |
| Bin | 1 | 0 | 2285 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 627 | 1 |
| Bin | 1 | 0 | 2227 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1208 | 1 |
| Bin | 1 | 0 | 2808 | 1 |
CONTROL_REGISTERS_IN.REC_REC_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11221 | 1 |
| Bin | 1 | 0 | 12815 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 249 | 1 |
| Bin | 1 | 0 | 1849 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 521 | 1 |
| Bin | 1 | 0 | 2121 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 488 | 1 |
| Bin | 1 | 0 | 2088 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 811 | 1 |
| Bin | 1 | 0 | 2411 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1931 | 1 |
| Bin | 1 | 0 | 3531 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12094 | 1 |
| Bin | 1 | 0 | 13694 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2980 | 1 |
| Bin | 1 | 0 | 4580 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3318 | 1 |
| Bin | 1 | 0 | 4918 | 1 |
CONTROL_REGISTERS_IN.TEC_TEC_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3517 | 1 |
| Bin | 1 | 0 | 5117 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1759 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 1878 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 600 | 1 |
| Bin | 1 | 0 | 2194 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1361 | 1 |
| Bin | 1 | 0 | 2956 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3048 | 1 |
| Bin | 1 | 0 | 4645 | 1 |
CONTROL_REGISTERS_IN.ERR_NORM_ERR_NORM_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11189 | 1 |
| Bin | 1 | 0 | 12783 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 74 | 1 |
| Bin | 1 | 0 | 1670 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 138 | 1 |
| Bin | 1 | 0 | 1735 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 359 | 1 |
| Bin | 1 | 0 | 1956 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 679 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1295 | 1 |
| Bin | 1 | 0 | 2892 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2524 | 1 |
| Bin | 1 | 0 | 4120 | 1 |
CONTROL_REGISTERS_IN.ERR_FD_ERR_FD_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5478 | 1 |
| Bin | 1 | 0 | 7073 | 1 |
CONTROL_REGISTERS_IN.FILTER_STATUS_SFA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 660 | 1 |
| Bin | 1 | 0 | 940 | 1 |
CONTROL_REGISTERS_IN.FILTER_STATUS_SFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165 | 1 |
| Bin | 1 | 0 | 1435 | 1 |
CONTROL_REGISTERS_IN.FILTER_STATUS_SFC| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165 | 1 |
| Bin | 1 | 0 | 1435 | 1 |
CONTROL_REGISTERS_IN.FILTER_STATUS_SFR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165 | 1 |
| Bin | 1 | 0 | 1435 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165 | 1 |
| Bin | 1 | 0 | 1435 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 495 | 1 |
| Bin | 1 | 0 | 1105 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 940 | 1 |
| Bin | 1 | 0 | 660 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_BUFF_SIZE(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1204 | 1 |
| Bin | 1 | 0 | 49325 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1041 | 1 |
| Bin | 1 | 0 | 49492 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1048 | 1 |
| Bin | 1 | 0 | 49499 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1062 | 1 |
| Bin | 1 | 0 | 49513 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1090 | 1 |
| Bin | 1 | 0 | 49541 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4483 | 1 |
| Bin | 1 | 0 | 30563 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4110 | 1 |
| Bin | 1 | 0 | 31180 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8773 | 1 |
| Bin | 1 | 0 | 8495 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8368 | 1 |
| Bin | 1 | 0 | 9966 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9899 | 1 |
| Bin | 1 | 0 | 11497 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12195 | 1 |
| Bin | 1 | 0 | 13793 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15908 | 1 |
| Bin | 1 | 0 | 17508 | 1 |
CONTROL_REGISTERS_IN.RX_MEM_INFO_RX_MEM_FREE(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27214 | 1 |
| Bin | 1 | 0 | 28814 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6 | 1 |
| Bin | 1 | 0 | 11733 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11 | 1 |
| Bin | 1 | 0 | 11738 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 23 | 1 |
| Bin | 1 | 0 | 11750 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 11773 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 11818 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 308 | 1 |
| Bin | 1 | 0 | 6958 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 659 | 1 |
| Bin | 1 | 0 | 7309 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1974 | 1 |
| Bin | 1 | 0 | 3574 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3743 | 1 |
| Bin | 1 | 0 | 5343 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6142 | 1 |
| Bin | 1 | 0 | 7740 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1871 | 1 |
| Bin | 1 | 0 | 3471 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_WPP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1547 | 1 |
| Bin | 1 | 0 | 3147 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3 | 1 |
| Bin | 1 | 0 | 41105 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 41107 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11 | 1 |
| Bin | 1 | 0 | 41113 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 41124 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 41145 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 23792 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 426 | 1 |
| Bin | 1 | 0 | 24016 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1582 | 1 |
| Bin | 1 | 0 | 3182 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3172 | 1 |
| Bin | 1 | 0 | 4772 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6629 | 1 |
| Bin | 1 | 0 | 8229 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12979 | 1 |
| Bin | 1 | 0 | 14579 | 1 |
CONTROL_REGISTERS_IN.RX_POINTERS_RX_RPP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25949 | 1 |
| Bin | 1 | 0 | 27549 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8948 | 1 |
| Bin | 1 | 0 | 8950 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXMOF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10885 | 1 |
| Bin | 1 | 0 | 10885 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 18003 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 18004 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 18009 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 18020 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 18042 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 9989 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 195 | 1 |
| Bin | 1 | 0 | 10086 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 404 | 1 |
| Bin | 1 | 0 | 2004 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 852 | 1 |
| Bin | 1 | 0 | 2452 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2540 | 1 |
| Bin | 1 | 0 | 4140 | 1 |
CONTROL_REGISTERS_IN.RX_STATUS_RXFRC(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11426 | 1 |
| Bin | 1 | 0 | 13024 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3391 | 1 |
| Bin | 1 | 0 | 6591 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3619 | 1 |
| Bin | 1 | 0 | 6819 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3230 | 1 |
| Bin | 1 | 0 | 6430 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6963 | 1 |
| Bin | 1 | 0 | 10163 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7260 | 1 |
| Bin | 1 | 0 | 10460 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6878 | 1 |
| Bin | 1 | 0 | 10078 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7290 | 1 |
| Bin | 1 | 0 | 10490 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13033 | 1 |
| Bin | 1 | 0 | 16231 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7331 | 1 |
| Bin | 1 | 0 | 10531 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7512 | 1 |
| Bin | 1 | 0 | 10712 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7716 | 1 |
| Bin | 1 | 0 | 10916 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 7057 | 1 |
| Bin | 1 | 0 | 10257 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9009 | 1 |
| Bin | 1 | 0 | 12209 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9566 | 1 |
| Bin | 1 | 0 | 12766 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8283 | 1 |
| Bin | 1 | 0 | 11483 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8210 | 1 |
| Bin | 1 | 0 | 11410 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8482 | 1 |
| Bin | 1 | 0 | 11682 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9663 | 1 |
| Bin | 1 | 0 | 12863 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12737 | 1 |
| Bin | 1 | 0 | 15937 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13575 | 1 |
| Bin | 1 | 0 | 16773 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15223 | 1 |
| Bin | 1 | 0 | 18421 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10430 | 1 |
| Bin | 1 | 0 | 13630 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11266 | 1 |
| Bin | 1 | 0 | 14466 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9997 | 1 |
| Bin | 1 | 0 | 13197 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12549 | 1 |
| Bin | 1 | 0 | 15749 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11752 | 1 |
| Bin | 1 | 0 | 14952 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11705 | 1 |
| Bin | 1 | 0 | 14905 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10094 | 1 |
| Bin | 1 | 0 | 13294 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11213 | 1 |
| Bin | 1 | 0 | 14413 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11421 | 1 |
| Bin | 1 | 0 | 14621 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 11800 | 1 |
| Bin | 1 | 0 | 15000 | 1 |
CONTROL_REGISTERS_IN.RX_DATA_RX_DATA(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12268 | 1 |
| Bin | 1 | 0 | 15468 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX1S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4860 | 1 |
| Bin | 1 | 0 | 3263 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX1S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12196 | 1 |
| Bin | 1 | 0 | 13793 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX1S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 14267 | 1 |
| Bin | 1 | 0 | 15867 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX1S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 14780 | 1 |
| Bin | 1 | 0 | 16380 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX2S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4053 | 1 |
| Bin | 1 | 0 | 2453 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX2S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6449 | 1 |
| Bin | 1 | 0 | 8049 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX2S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8525 | 1 |
| Bin | 1 | 0 | 10125 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX2S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8417 | 1 |
| Bin | 1 | 0 | 10017 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX3S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1086 | 1 |
| Bin | 1 | 0 | 1366 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX3S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 823 | 1 |
| Bin | 1 | 0 | 2423 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX3S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1022 | 1 |
| Bin | 1 | 0 | 2622 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX3S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1017 | 1 |
| Bin | 1 | 0 | 2617 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX4S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1118 | 1 |
| Bin | 1 | 0 | 1398 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX4S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 852 | 1 |
| Bin | 1 | 0 | 2452 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX4S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 2627 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX4S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 958 | 1 |
| Bin | 1 | 0 | 2558 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX5S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 274 | 1 |
| Bin | 1 | 0 | 1544 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX5S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 189 | 1 |
| Bin | 1 | 0 | 1789 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX5S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 245 | 1 |
| Bin | 1 | 0 | 1845 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX5S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 242 | 1 |
| Bin | 1 | 0 | 1842 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX6S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 268 | 1 |
| Bin | 1 | 0 | 1538 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX6S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 206 | 1 |
| Bin | 1 | 0 | 1806 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX6S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 247 | 1 |
| Bin | 1 | 0 | 1847 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX6S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 228 | 1 |
| Bin | 1 | 0 | 1828 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX7S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 1537 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX7S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 1784 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX7S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 237 | 1 |
| Bin | 1 | 0 | 1837 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX7S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 232 | 1 |
| Bin | 1 | 0 | 1832 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX8S(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 1533 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX8S(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 195 | 1 |
| Bin | 1 | 0 | 1795 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX8S(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 239 | 1 |
| Bin | 1 | 0 | 1839 | 1 |
CONTROL_REGISTERS_IN.TX_STATUS_TX8S(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 221 | 1 |
| Bin | 1 | 0 | 1821 | 1 |
CONTROL_REGISTERS_IN.TXTB_INFO_TXT_BUFFER_COUNT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165 | 1 |
| Bin | 1 | 0 | 1435 | 1 |
CONTROL_REGISTERS_IN.TXTB_INFO_TXT_BUFFER_COUNT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 495 | 1 |
| Bin | 1 | 0 | 1105 | 1 |
CONTROL_REGISTERS_IN.TXTB_INFO_TXT_BUFFER_COUNT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 940 | 1 |
| Bin | 1 | 0 | 660 | 1 |
CONTROL_REGISTERS_IN.TXTB_INFO_TXT_BUFFER_COUNT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_POS(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4185 | 1 |
| Bin | 1 | 0 | 2591 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_POS(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4402 | 1 |
| Bin | 1 | 0 | 2803 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_POS(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3666 | 1 |
| Bin | 1 | 0 | 2070 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_POS(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 1361 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_ERP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 290 | 1 |
| Bin | 1 | 0 | 1890 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_TYPE(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 793 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_TYPE(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1252 | 1 |
| Bin | 1 | 0 | 2850 | 1 |
CONTROL_REGISTERS_IN.ERR_CAPT_ERR_TYPE(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 336 | 1 |
| Bin | 1 | 0 | 1935 | 1 |
CONTROL_REGISTERS_IN.RETR_CTR_RETR_CTR_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.RETR_CTR_RETR_CTR_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 132 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
CONTROL_REGISTERS_IN.RETR_CTR_RETR_CTR_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 255 | 1 |
| Bin | 1 | 0 | 1855 | 1 |
CONTROL_REGISTERS_IN.RETR_CTR_RETR_CTR_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_BIT(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_BIT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1686 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_BIT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_BIT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 171 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_BIT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 1894 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_ID_FIELD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_ID_FIELD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
CONTROL_REGISTERS_IN.ALC_ALC_ID_FIELD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TS_INFO_TS_BITS(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1642 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 81 | 1 |
| Bin | 1 | 0 | 1681 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2154 | 1 |
| Bin | 1 | 0 | 3754 | 1 |
CONTROL_REGISTERS_IN.TRV_DELAY_TRV_DELAY_VALUE(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1650 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1648 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1645 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1649 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1676 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 222 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 355 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 746 | 1 |
| Bin | 1 | 0 | 2344 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1495 | 1 |
| Bin | 1 | 0 | 3093 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 4557 | 1 |
CONTROL_REGISTERS_IN.RX_FR_CTR_RX_FR_CTR_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5919 | 1 |
| Bin | 1 | 0 | 7518 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 1708 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 1691 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1695 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1702 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 1710 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1700 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1694 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 1729 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 1863 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 593 | 1 |
| Bin | 1 | 0 | 2193 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1072 | 1 |
| Bin | 1 | 0 | 2672 | 1 |
CONTROL_REGISTERS_IN.TX_FR_CTR_TX_FR_CTR_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2211 | 1 |
| Bin | 1 | 0 | 3811 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_STUFF_COUNT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33334 | 1 |
| Bin | 1 | 0 | 34934 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_STUFF_COUNT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70225 | 1 |
| Bin | 1 | 0 | 71823 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_STUFF_COUNT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 140700 | 1 |
| Bin | 1 | 0 | 142298 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_DESTUFF_COUNT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116920 | 1 |
| Bin | 1 | 0 | 118520 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_DESTUFF_COUNT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 241878 | 1 |
| Bin | 1 | 0 | 243473 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_DESTUFF_COUNT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 483649 | 1 |
| Bin | 1 | 0 | 485246 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_ARB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55248 | 1 |
| Bin | 1 | 0 | 56848 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_CON| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50561 | 1 |
| Bin | 1 | 0 | 52161 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_DAT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 36048 | 1 |
| Bin | 1 | 0 | 37648 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_STC| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13456 | 1 |
| Bin | 1 | 0 | 15056 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_CRC| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31170 | 1 |
| Bin | 1 | 0 | 32770 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_CRCD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29717 | 1 |
| Bin | 1 | 0 | 31317 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_ACK| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29563 | 1 |
| Bin | 1 | 0 | 31163 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_ACKD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28146 | 1 |
| Bin | 1 | 0 | 29746 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_EOF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27259 | 1 |
| Bin | 1 | 0 | 28859 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_INT| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51238 | 1 |
| Bin | 1 | 0 | 52837 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_SUSP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2324 | 1 |
| Bin | 1 | 0 | 3924 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_OVR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 2129 | 1 |
CONTROL_REGISTERS_IN.DEBUG_REGISTER_PC_SOF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 24462 | 1 |
| Bin | 1 | 0 | 26062 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 1 | 0 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.YOLO_REG_YOLO_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1600 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 41 | 1 |
| Bin | 1 | 0 | 1636 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 64 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1658 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1678 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 144 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 245 | 1 |
| Bin | 1 | 0 | 1790 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 519 | 1 |
| Bin | 1 | 0 | 1971 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 961 | 1 |
| Bin | 1 | 0 | 2433 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2011 | 1 |
| Bin | 1 | 0 | 3342 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4028 | 1 |
| Bin | 1 | 0 | 5290 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8016 | 1 |
| Bin | 1 | 0 | 9246 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16074 | 1 |
| Bin | 1 | 0 | 17210 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 32196 | 1 |
| Bin | 1 | 0 | 33246 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 64405 | 1 |
| Bin | 1 | 0 | 65386 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 128814 | 1 |
| Bin | 1 | 0 | 129727 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 257669 | 1 |
| Bin | 1 | 0 | 258468 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 515264 | 1 |
| Bin | 1 | 0 | 516075 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1030498 | 1 |
| Bin | 1 | 0 | 1031282 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2060912 | 1 |
| Bin | 1 | 0 | 2061710 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4121754 | 1 |
| Bin | 1 | 0 | 4122555 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8243451 | 1 |
| Bin | 1 | 0 | 8244267 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16486854 | 1 |
| Bin | 1 | 0 | 16487672 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 32973670 | 1 |
| Bin | 1 | 0 | 32974464 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65947279 | 1 |
| Bin | 1 | 0 | 65948086 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 131894504 | 1 |
| Bin | 1 | 0 | 131895310 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_LOW_TIMESTAMP_LOW(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 263788978 | 1 |
| Bin | 1 | 0 | 263789775 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1618 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1659 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 78 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1656 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 64 | 1 |
| Bin | 1 | 0 | 1659 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1659 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 64 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 69 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 67 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1658 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1653 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65 | 1 |
| Bin | 1 | 0 | 1657 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1663 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1660 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1664 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_IN.TIMESTAMP_HIGH_TIMESTAMP_HIGH(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
REG_SEL(38)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5777977 | 1 |
REG_SEL(37)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3935 | 1 |
| Bin | 1 | 0 | 5774035 | 1 |
REG_SEL(36)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 5770325 | 1 |
REG_SEL(35)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10219898 | 1 |
| Bin | 1 | 0 | 28993992 | 1 |
REG_SEL(34)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 5853392 | 1 |
REG_SEL(33)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1122 | 1 |
| Bin | 1 | 0 | 5783472 | 1 |
REG_SEL(32)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3458 | 1 |
| Bin | 1 | 0 | 39329292 | 1 |
REG_SEL(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 537 | 1 |
| Bin | 1 | 0 | 39332213 | 1 |
REG_SEL(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4066 | 1 |
| Bin | 1 | 0 | 39328684 | 1 |
REG_SEL(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27527 | 1 |
| Bin | 1 | 0 | 39305223 | 1 |
REG_SEL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8805 | 1 |
| Bin | 1 | 0 | 39323945 | 1 |
REG_SEL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51733 | 1 |
| Bin | 1 | 0 | 39281017 | 1 |
REG_SEL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13223 | 1 |
| Bin | 1 | 0 | 39319527 | 1 |
REG_SEL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 39295496 | 1 |
REG_SEL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12418 | 1 |
| Bin | 1 | 0 | 24036342 | 1 |
REG_SEL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20068 | 1 |
| Bin | 1 | 0 | 39312682 | 1 |
REG_SEL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 35485410 | 1 |
REG_SEL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 35438380 | 1 |
REG_SEL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 39270543 | 1 |
REG_SEL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35437941 | 1 |
REG_SEL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35442769 | 1 |
REG_SEL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2835 | 1 |
| Bin | 1 | 0 | 35437941 | 1 |
REG_SEL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 39327326 | 1 |
REG_SEL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4082 | 1 |
| Bin | 1 | 0 | 39327322 | 1 |
REG_SEL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 41481 | 1 |
| Bin | 1 | 0 | 39291269 | 1 |
REG_SEL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2192 | 1 |
| Bin | 1 | 0 | 39268302 | 1 |
REG_SEL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 14068 | 1 |
| Bin | 1 | 0 | 37086924 | 1 |
REG_SEL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 111952 | 1 |
| Bin | 1 | 0 | 39220798 | 1 |
REG_SEL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6713 | 1 |
| Bin | 1 | 0 | 39326037 | 1 |
REG_SEL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6623 | 1 |
| Bin | 1 | 0 | 39326127 | 1 |
REG_SEL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 485 | 1 |
| Bin | 1 | 0 | 39332265 | 1 |
REG_SEL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 565 | 1 |
| Bin | 1 | 0 | 39332185 | 1 |
REG_SEL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 552 | 1 |
| Bin | 1 | 0 | 39332198 | 1 |
REG_SEL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 39332118 | 1 |
REG_SEL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2154 | 1 |
| Bin | 1 | 0 | 39330596 | 1 |
REG_SEL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1480 | 1 |
| Bin | 1 | 0 | 39331270 | 1 |
REG_SEL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8997186 | 1 |
| Bin | 1 | 0 | 30335564 | 1 |
REG_SEL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75513 | 1 |
| Bin | 1 | 0 | 39257237 | 1 |
REG_SEL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 39332725 | 1 |
R_DATA_COMB(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22624 | 1 |
| Bin | 1 | 0 | 24224 | 1 |
R_DATA_COMB(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21320 | 1 |
| Bin | 1 | 0 | 22920 | 1 |
R_DATA_COMB(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26759 | 1 |
| Bin | 1 | 0 | 28359 | 1 |
R_DATA_COMB(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92016 | 1 |
| Bin | 1 | 0 | 93616 | 1 |
R_DATA_COMB(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 57710 | 1 |
| Bin | 1 | 0 | 59310 | 1 |
R_DATA_COMB(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30047 | 1 |
| Bin | 1 | 0 | 31647 | 1 |
R_DATA_COMB(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 352565 | 1 |
| Bin | 1 | 0 | 352565 | 1 |
R_DATA_COMB(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40969 | 1 |
| Bin | 1 | 0 | 42569 | 1 |
R_DATA_COMB(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 49848 | 1 |
| Bin | 1 | 0 | 51448 | 1 |
R_DATA_COMB(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 165584 | 1 |
| Bin | 1 | 0 | 167184 | 1 |
R_DATA_COMB(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70301 | 1 |
| Bin | 1 | 0 | 71901 | 1 |
R_DATA_COMB(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77349 | 1 |
| Bin | 1 | 0 | 78949 | 1 |
R_DATA_COMB(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96455 | 1 |
| Bin | 1 | 0 | 98055 | 1 |
R_DATA_COMB(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8867290 | 1 |
| Bin | 1 | 0 | 8867290 | 1 |
R_DATA_COMB(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 9821936 | 1 |
| Bin | 1 | 0 | 9821936 | 1 |
R_DATA_COMB(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 8836693 | 1 |
| Bin | 1 | 0 | 8836693 | 1 |
R_DATA_COMB(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 508667 | 1 |
| Bin | 1 | 0 | 508667 | 1 |
R_DATA_COMB(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1066991 | 1 |
| Bin | 1 | 0 | 1066991 | 1 |
R_DATA_COMB(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 240197 | 1 |
| Bin | 1 | 0 | 241797 | 1 |
R_DATA_COMB(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 257358 | 1 |
| Bin | 1 | 0 | 258958 | 1 |
R_DATA_COMB(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 398634 | 1 |
| Bin | 1 | 0 | 398634 | 1 |
R_DATA_COMB(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4179248 | 1 |
| Bin | 1 | 0 | 4180848 | 1 |
R_DATA_COMB(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1105922 | 1 |
| Bin | 1 | 0 | 1105922 | 1 |
R_DATA_COMB(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4591130 | 1 |
| Bin | 1 | 0 | 4592730 | 1 |
R_DATA_COMB(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2495715 | 1 |
| Bin | 1 | 0 | 2495715 | 1 |
R_DATA_COMB(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5705003 | 1 |
| Bin | 1 | 0 | 5705003 | 1 |
R_DATA_COMB(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10550887 | 1 |
| Bin | 1 | 0 | 10550887 | 1 |
R_DATA_COMB(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6878989 | 1 |
| Bin | 1 | 0 | 6878989 | 1 |
R_DATA_COMB(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10047748 | 1 |
| Bin | 1 | 0 | 10047748 | 1 |
R_DATA_COMB(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10273489 | 1 |
| Bin | 1 | 0 | 10273489 | 1 |
R_DATA_COMB(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2888076 | 1 |
| Bin | 1 | 0 | 2889676 | 1 |
R_DATA_COMB(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4660779 | 1 |
| Bin | 1 | 0 | 4660779 | 1 |
READ_DATA_MASK_N(31)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(30)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(29)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
READ_DATA_MASK_N(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
READ_DATA_MASK_N(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
READ_DATA_MASK_N(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
READ_DATA_MASK_N(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_RST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 867 | 1 |
| Bin | 1 | 0 | 32865 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_BMM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_STM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 160 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_AFM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 68 | 1 |
| Bin | 1 | 0 | 1668 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_FDE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1800 | 1 |
| Bin | 1 | 0 | 200 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_TTTM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_ROM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_ACF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_TSTM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 2626 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_RXBAM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1730 | 1 |
| Bin | 1 | 0 | 130 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_TXBBM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_SAM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 1655 | 1 |
CONTROL_REGISTERS_OUT_I.MODE_ERFM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 153 | 1 |
| Bin | 1 | 0 | 1753 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_RTRLE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2454 | 1 |
| Bin | 1 | 0 | 4054 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_RTRTH(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_RTRTH(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_RTRTH(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_RTRTH(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_ILBP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_ENA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6482 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_NISOFD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 1730 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_PEX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 72 | 1 |
| Bin | 1 | 0 | 1672 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_TBFBO| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2533 | 1 |
| Bin | 1 | 0 | 943 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_FDRF| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 1604 | 1 |
CONTROL_REGISTERS_OUT_I.SETTINGS_PCHKE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_RXRPMV| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_RRB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 460 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_CDO| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_ERCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 170 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_RXFCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_TXFCRST| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_CPEXS| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_CRXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_CTXPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 440 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.COMMAND_CTXDPE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 3070 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_RXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_TXI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_EWLI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_DOI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 16 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_FCSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_ALI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_BEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_OFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_RXFI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_BSI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 42 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_RBNEI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_STAT_TXBHCI| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2277 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 2277 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2277 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2277 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_SET_INT_ENA_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 476 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 512 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 492 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_ENA_CLR_INT_ENA_CLR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 2142 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 2155 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 40 | 1 |
| Bin | 1 | 0 | 2155 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 2155 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 2155 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_SET_INT_MASK_SET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 10 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 435 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 425 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 460 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.INT_MASK_CLR_INT_MASK_CLR(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 2075 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 312 | 1 |
| Bin | 1 | 0 | 1909 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 223 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 273 | 1 |
| Bin | 1 | 0 | 1870 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3820 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 261 | 1 |
| Bin | 1 | 0 | 1858 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PROP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1793 | 1 |
| Bin | 1 | 0 | 194 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 325 | 1 |
| Bin | 1 | 0 | 1962 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 285 | 1 |
| Bin | 1 | 0 | 1905 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 312 | 1 |
| Bin | 1 | 0 | 1949 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1410 | 1 |
| Bin | 1 | 0 | 3042 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2177 | 1 |
| Bin | 1 | 0 | 538 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH1(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4486 | 1 |
| Bin | 1 | 0 | 490 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 7770 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 506 | 1 |
| Bin | 1 | 0 | 8139 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 699 | 1 |
| Bin | 1 | 0 | 8217 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3878 | 1 |
| Bin | 1 | 0 | 2274 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3416 | 1 |
| Bin | 1 | 0 | 5010 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_PH2(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2161 | 1 |
| Bin | 1 | 0 | 561 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 8160 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 8159 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 13 | 1 |
| Bin | 1 | 0 | 8160 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4842 | 1 |
| Bin | 1 | 0 | 3242 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 928 | 1 |
| Bin | 1 | 0 | 2534 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4773 | 1 |
| Bin | 1 | 0 | 3170 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_BRP(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2316 | 1 |
| Bin | 1 | 0 | 3922 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_SJW(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_SJW(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 269 | 1 |
| Bin | 1 | 0 | 1866 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_SJW(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 966 | 1 |
| Bin | 1 | 0 | 2563 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_SJW(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2625 | 1 |
| Bin | 1 | 0 | 1032 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_SJW(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3116 | 1 |
| Bin | 1 | 0 | 4713 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 1840 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 286 | 1 |
| Bin | 1 | 0 | 1883 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1185 | 1 |
| Bin | 1 | 0 | 2775 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4706 | 1 |
| Bin | 1 | 0 | 3113 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PROP_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3890 | 1 |
| Bin | 1 | 0 | 2290 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH1_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 5990 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH1_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 288 | 1 |
| Bin | 1 | 0 | 6015 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH1_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1187 | 1 |
| Bin | 1 | 0 | 6919 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH1_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5842 | 1 |
| Bin | 1 | 0 | 127 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH1_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6022 | 1 |
| Bin | 1 | 0 | 2286 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH2_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 321 | 1 |
| Bin | 1 | 0 | 7886 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH2_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 7939 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH2_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1215 | 1 |
| Bin | 1 | 0 | 2819 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH2_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 133 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_PH2_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 3884 | 1 |
| Bin | 1 | 0 | 2293 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19 | 1 |
| Bin | 1 | 0 | 8137 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 8145 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 8136 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1638 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4843 | 1 |
| Bin | 1 | 0 | 3263 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 758 | 1 |
| Bin | 1 | 0 | 2356 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_BRP_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2600 | 1 |
| Bin | 1 | 0 | 4202 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_SJW_FD(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 236 | 1 |
| Bin | 1 | 0 | 1833 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_SJW_FD(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 275 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_SJW_FD(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 929 | 1 |
| Bin | 1 | 0 | 2526 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_SJW_FD(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2558 | 1 |
| Bin | 1 | 0 | 965 | 1 |
CONTROL_REGISTERS_OUT_I.BTR_FD_SJW_FD(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 949 | 1 |
| Bin | 1 | 0 | 2546 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 78 | 1 |
| Bin | 1 | 0 | 1678 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1686 | 1 |
| Bin | 1 | 0 | 86 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 70 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1683 | 1 |
CONTROL_REGISTERS_OUT_I.EWL_EW_LIMIT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1679 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1736 | 1 |
| Bin | 1 | 0 | 136 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20 | 1 |
| Bin | 1 | 0 | 1620 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1626 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT_I.ERP_ERP_LIMIT(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 373 | 1 |
| Bin | 1 | 0 | 7689 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2166 | 1 |
| Bin | 1 | 0 | 3796 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 683 | 1 |
| Bin | 1 | 0 | 2314 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2182 | 1 |
| Bin | 1 | 0 | 3802 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2332 | 1 |
| Bin | 1 | 0 | 3955 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 919 | 1 |
| Bin | 1 | 0 | 2543 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2415 | 1 |
| Bin | 1 | 0 | 4048 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1008 | 1 |
| Bin | 1 | 0 | 2632 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_CTPV(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 769 | 1 |
| Bin | 1 | 0 | 2388 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_PTX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18698 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_PRX| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 19085 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_ENORM| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT_I.CTR_PRES_EFD| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5942 | 1 |
| Bin | 1 | 0 | 42871 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2508 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 334 | 1 |
| Bin | 1 | 0 | 2250 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 358 | 1 |
| Bin | 1 | 0 | 2293 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 362 | 1 |
| Bin | 1 | 0 | 2326 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 2390 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2177 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 387 | 1 |
| Bin | 1 | 0 | 2265 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 344 | 1 |
| Bin | 1 | 0 | 2106 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 376 | 1 |
| Bin | 1 | 0 | 2137 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 2179 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 412 | 1 |
| Bin | 1 | 0 | 2294 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1833 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1733 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 2246 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 2207 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 2222 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1988 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 123 | 1 |
| Bin | 1 | 0 | 2170 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 2321 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 2164 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 267 | 1 |
| Bin | 1 | 0 | 2488 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 2169 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 2302 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 276 | 1 |
| Bin | 1 | 0 | 2337 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 2415 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 265 | 1 |
| Bin | 1 | 0 | 2412 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 274 | 1 |
| Bin | 1 | 0 | 2301 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 234 | 1 |
| Bin | 1 | 0 | 2351 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_MASK_BIT_MASK_A_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 296 | 1 |
| Bin | 1 | 0 | 2427 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 786 | 1 |
| Bin | 1 | 0 | 2457 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 850 | 1 |
| Bin | 1 | 0 | 2530 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 768 | 1 |
| Bin | 1 | 0 | 2447 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 738 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 2469 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 782 | 1 |
| Bin | 1 | 0 | 2395 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 837 | 1 |
| Bin | 1 | 0 | 2444 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 822 | 1 |
| Bin | 1 | 0 | 2429 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 781 | 1 |
| Bin | 1 | 0 | 2392 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 816 | 1 |
| Bin | 1 | 0 | 2432 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 814 | 1 |
| Bin | 1 | 0 | 2433 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 2002 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 397 | 1 |
| Bin | 1 | 0 | 2002 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2713 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 433 | 1 |
| Bin | 1 | 0 | 2899 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 409 | 1 |
| Bin | 1 | 0 | 2875 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 375 | 1 |
| Bin | 1 | 0 | 3065 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 458 | 1 |
| Bin | 1 | 0 | 2860 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2999 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 385 | 1 |
| Bin | 1 | 0 | 2563 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 381 | 1 |
| Bin | 1 | 0 | 2719 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 399 | 1 |
| Bin | 1 | 0 | 2865 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 405 | 1 |
| Bin | 1 | 0 | 2775 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 415 | 1 |
| Bin | 1 | 0 | 2689 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2795 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 407 | 1 |
| Bin | 1 | 0 | 2489 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 416 | 1 |
| Bin | 1 | 0 | 2890 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 378 | 1 |
| Bin | 1 | 0 | 2692 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_A_VAL_BIT_VAL_A_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 417 | 1 |
| Bin | 1 | 0 | 2667 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1719 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1727 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1760 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 113 | 1 |
| Bin | 1 | 0 | 1843 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1773 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1744 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1781 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1801 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 1804 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1743 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1661 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1662 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1665 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 39 | 1 |
| Bin | 1 | 0 | 1699 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1887 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1888 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 70 | 1 |
| Bin | 1 | 0 | 1750 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1738 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1989 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1958 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 63 | 1 |
| Bin | 1 | 0 | 1769 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 66 | 1 |
| Bin | 1 | 0 | 1930 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 1758 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 65 | 1 |
| Bin | 1 | 0 | 2025 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1926 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_MASK_BIT_MASK_B_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 81 | 1 |
| Bin | 1 | 0 | 1755 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1788 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 188 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 193 | 1 |
| Bin | 1 | 0 | 1795 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 1798 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 225 | 1 |
| Bin | 1 | 0 | 1831 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 190 | 1 |
| Bin | 1 | 0 | 1792 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 215 | 1 |
| Bin | 1 | 0 | 1817 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 210 | 1 |
| Bin | 1 | 0 | 1812 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 200 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1809 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 218 | 1 |
| Bin | 1 | 0 | 1820 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1697 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 118 | 1 |
| Bin | 1 | 0 | 1720 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 2028 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1989 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1755 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1991 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 121 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 1724 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1832 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1794 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 1752 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1842 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 90 | 1 |
| Bin | 1 | 0 | 1989 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 113 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1811 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1802 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_B_VAL_BIT_VAL_B_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 93 | 1 |
| Bin | 1 | 0 | 1800 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1828 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1819 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 88 | 1 |
| Bin | 1 | 0 | 1855 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 82 | 1 |
| Bin | 1 | 0 | 1782 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 90 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 92 | 1 |
| Bin | 1 | 0 | 1725 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 122 | 1 |
| Bin | 1 | 0 | 1812 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1725 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 99 | 1 |
| Bin | 1 | 0 | 1787 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1783 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1724 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 26 | 1 |
| Bin | 1 | 0 | 1642 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 36 | 1 |
| Bin | 1 | 0 | 1672 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1713 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1701 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 1909 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1871 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 1852 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1950 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 1735 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1779 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1766 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 1696 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 76 | 1 |
| Bin | 1 | 0 | 1736 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 71 | 1 |
| Bin | 1 | 0 | 1741 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 1948 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1787 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 61 | 1 |
| Bin | 1 | 0 | 1731 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_MASK_BIT_MASK_C_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 1898 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1832 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 189 | 1 |
| Bin | 1 | 0 | 1803 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 205 | 1 |
| Bin | 1 | 0 | 1824 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 186 | 1 |
| Bin | 1 | 0 | 1786 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1799 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 1818 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1826 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 224 | 1 |
| Bin | 1 | 0 | 1826 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 1801 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 202 | 1 |
| Bin | 1 | 0 | 1804 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 196 | 1 |
| Bin | 1 | 0 | 1798 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 1717 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 1718 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 101 | 1 |
| Bin | 1 | 0 | 1803 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 117 | 1 |
| Bin | 1 | 0 | 2043 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 79 | 1 |
| Bin | 1 | 0 | 2005 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1998 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 1988 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 80 | 1 |
| Bin | 1 | 0 | 1750 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 85 | 1 |
| Bin | 1 | 0 | 1915 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1838 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1768 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 1957 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 1994 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 112 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 1766 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1966 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 2031 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_C_VAL_BIT_VAL_C_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 128 | 1 |
| Bin | 1 | 0 | 2022 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_LOW_BIT_RAN_LOW_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(28)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(27)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(26)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(25)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(24)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(23)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(22)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(21)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(20)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(19)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(18)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2 | 1 |
| Bin | 1 | 0 | 1602 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(17)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(16)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(15)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(14)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(13)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(12)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(11)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(10)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(9)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(8)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_RAN_HIGH_BIT_RAN_HIGH_VAL(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 1603 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FANB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2051 | 1 |
| Bin | 1 | 0 | 451 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FANE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2028 | 1 |
| Bin | 1 | 0 | 428 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FAFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2059 | 1 |
| Bin | 1 | 0 | 459 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FAFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2028 | 1 |
| Bin | 1 | 0 | 428 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FBNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FBNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FBFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FBFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FCNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 1706 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FCNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FCFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 1707 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FCFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 1705 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FRNB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6 | 1 |
| Bin | 1 | 0 | 1606 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FRNE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FRFB| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6 | 1 |
| Bin | 1 | 0 | 1606 | 1 |
CONTROL_REGISTERS_OUT_I.FILTER_CONTROL_FRFE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT_I.RX_SETTINGS_RTSOP| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
CONTROL_REGISTERS_OUT_I.RX_DATA_READ| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 51733 | 1 |
| Bin | 1 | 0 | 53333 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXCE| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXCR| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 20943 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXCA| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB1| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 6540 | 1 |
| Bin | 1 | 0 | 8136 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB2| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 5586 | 1 |
| Bin | 1 | 0 | 7186 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB3| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 333 | 1 |
| Bin | 1 | 0 | 1933 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB4| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 345 | 1 |
| Bin | 1 | 0 | 1945 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB5| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 89 | 1 |
| Bin | 1 | 0 | 1689 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB6| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB7| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 84 | 1 |
| Bin | 1 | 0 | 1684 | 1 |
CONTROL_REGISTERS_OUT_I.TX_COMMAND_TXB8| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 1675 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT1P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 1709 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT1P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 1716 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT1P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 1726 | 1 |
| Bin | 1 | 0 | 126 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT2P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 1698 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT2P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 127 | 1 |
| Bin | 1 | 0 | 1727 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT2P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 1724 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT3P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 73 | 1 |
| Bin | 1 | 0 | 1673 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT3P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT3P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 1703 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT4P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT4P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT4P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 93 | 1 |
| Bin | 1 | 0 | 1693 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT5P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT5P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 24 | 1 |
| Bin | 1 | 0 | 1624 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT5P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT6P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 23 | 1 |
| Bin | 1 | 0 | 1623 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT6P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 1628 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT6P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 31 | 1 |
| Bin | 1 | 0 | 1631 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT7P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT7P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 30 | 1 |
| Bin | 1 | 0 | 1630 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT7P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 27 | 1 |
| Bin | 1 | 0 | 1627 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT8P(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 21 | 1 |
| Bin | 1 | 0 | 1621 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT8P(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 22 | 1 |
| Bin | 1 | 0 | 1622 | 1 |
CONTROL_REGISTERS_OUT_I.TX_PRIORITY_TXT8P(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 29 | 1 |
| Bin | 1 | 0 | 1629 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(7)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(6)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 25 | 1 |
| Bin | 1 | 0 | 1625 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(5)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 1644 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(4)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 1652 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 4305 | 1 |
| Bin | 1 | 0 | 2715 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 527 | 1 |
| Bin | 1 | 0 | 2127 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2899 | 1 |
| Bin | 1 | 0 | 1309 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_OFFSET(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 2397 | 1 |
| Bin | 1 | 0 | 3997 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_SRC(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 1647 | 1 |
CONTROL_REGISTERS_OUT_I.SSP_CFG_SSP_SRC(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 817 | 1 |
| Bin | 1 | 0 | 2407 | 1 |
WRITE_EN(3)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 125737 | 1 |
| Bin | 1 | 0 | 181103 | 1 |
WRITE_EN(2)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 125757 | 1 |
| Bin | 1 | 0 | 181083 | 1 |
WRITE_EN(1)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 144497 | 1 |
| Bin | 1 | 0 | 162343 | 1 |
WRITE_EN(0)| From | To | Count | Threshold | |
|---|---|---|---|---|
| Bin | 0 | 1 | 144497 | 1 |
| Bin | 1 | 0 | 162343 | 1 |
121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 93679951 | 1 |
| Bin | True | 1242465 | 1 |
121: write_en <= be when (write = '1' and cs = '1') else (others => '0'); | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 55591266 | 1 |
| Bin | True | 39331150 | 1 |
121: write_en <= be when (write = '1' and cs = '1') else (others => '0');
<---LHS---> <-RHS--> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 39178530 | 1 |
| Bin | True | False | 1089845 | 1 |
| Bin | True | True | 152620 | 1 |
3086: if (res_n = '0') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 62060461 | 1 |
| Bin | True | 17943 | 1 |
3089: if (cs = '1' and read = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 11359297 | 1 |
| Bin | True | 19665499 | 1 |
3089: if (cs = '1' and read = '1') then | Evaluated to | Count | Threshold | |
|---|---|---|---|
| Bin | False | 10567142 | 1 |
| Bin | True | 20457654 | 1 |
3089: if (cs = '1' and read = '1') then
<-LHS--> <--RHS---> | LHS | RHS | Count | Threshold | |
|---|---|---|---|---|
| Bin | False | True | 944775 | 1 |
| Bin | True | False | 152620 | 1 |
| Bin | True | True | 19512879 | 1 |
3111: -- psl device_id_read_access_cov : cover
3112: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1')))}; 3114: -- psl version_read_access_cov : cover
3115: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(2)='1') or (be(3)='1')))}; 3117: -- psl mode_write_access_cov : cover
3118: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))}; 3120: -- psl mode_read_access_cov : cover
3121: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1')))}; 3123: -- psl settings_write_access_cov : cover
3124: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))}; 3126: -- psl settings_read_access_cov : cover
3127: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(2)='1') or (be(3)='1')))}; 3129: -- psl status_read_access_cov : cover
3130: -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3132: -- psl command_write_access_cov : cover
3133: -- {((cs='1') and (write='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3135: -- psl int_stat_write_access_cov : cover
3136: -- {((cs='1') and (write='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))}; 3138: -- psl int_stat_read_access_cov : cover
3139: -- {((cs='1') and (read='1') and (reg_sel(4)='1') and ((be(0)='1') or (be(1)='1')))}; 3141: -- psl int_ena_set_write_access_cov : cover
3142: -- {((cs='1') and (write='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))}; 3144: -- psl int_ena_set_read_access_cov : cover
3145: -- {((cs='1') and (read='1') and (reg_sel(5)='1') and ((be(0)='1') or (be(1)='1')))}; 3147: -- psl int_ena_clr_write_access_cov : cover
3148: -- {((cs='1') and (write='1') and (reg_sel(6)='1') and ((be(0)='1') or (be(1)='1')))}; 3150: -- psl int_mask_set_write_access_cov : cover
3151: -- {((cs='1') and (write='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))}; 3153: -- psl int_mask_set_read_access_cov : cover
3154: -- {((cs='1') and (read='1') and (reg_sel(7)='1') and ((be(0)='1') or (be(1)='1')))}; 3156: -- psl int_mask_clr_write_access_cov : cover
3157: -- {((cs='1') and (write='1') and (reg_sel(8)='1') and ((be(0)='1') or (be(1)='1')))}; 3159: -- psl btr_write_access_cov : cover
3160: -- {((cs='1') and (write='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3162: -- psl btr_read_access_cov : cover
3163: -- {((cs='1') and (read='1') and (reg_sel(9)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3165: -- psl btr_fd_write_access_cov : cover
3166: -- {((cs='1') and (write='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3168: -- psl btr_fd_read_access_cov : cover
3169: -- {((cs='1') and (read='1') and (reg_sel(10)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3171: -- psl ewl_write_access_cov : cover
3172: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(0)='1')))}; 3174: -- psl ewl_read_access_cov : cover
3175: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(0)='1')))}; 3177: -- psl erp_write_access_cov : cover
3178: -- {((cs='1') and (write='1') and (reg_sel(11)='1') and ((be(1)='1')))}; 3180: -- psl erp_read_access_cov : cover
3181: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(1)='1')))}; 3183: -- psl fault_state_read_access_cov : cover
3184: -- {((cs='1') and (read='1') and (reg_sel(11)='1') and ((be(2)='1') or (be(3)='1')))}; 3186: -- psl rec_read_access_cov : cover
3187: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(0)='1') or (be(1)='1')))}; 3189: -- psl tec_read_access_cov : cover
3190: -- {((cs='1') and (read='1') and (reg_sel(12)='1') and ((be(2)='1') or (be(3)='1')))}; 3192: -- psl err_norm_read_access_cov : cover
3193: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(0)='1') or (be(1)='1')))}; 3195: -- psl err_fd_read_access_cov : cover
3196: -- {((cs='1') and (read='1') and (reg_sel(13)='1') and ((be(2)='1') or (be(3)='1')))}; 3198: -- psl ctr_pres_write_access_cov : cover
3199: -- {((cs='1') and (write='1') and (reg_sel(14)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3201: -- psl filter_a_mask_write_access_cov : cover
3202: -- {((cs='1') and (write='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3204: -- psl filter_a_mask_read_access_cov : cover
3205: -- {((cs='1') and (read='1') and (reg_sel(15)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3207: -- psl filter_a_val_write_access_cov : cover
3208: -- {((cs='1') and (write='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3210: -- psl filter_a_val_read_access_cov : cover
3211: -- {((cs='1') and (read='1') and (reg_sel(16)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3213: -- psl filter_b_mask_write_access_cov : cover
3214: -- {((cs='1') and (write='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3216: -- psl filter_b_mask_read_access_cov : cover
3217: -- {((cs='1') and (read='1') and (reg_sel(17)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3219: -- psl filter_b_val_write_access_cov : cover
3220: -- {((cs='1') and (write='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3222: -- psl filter_b_val_read_access_cov : cover
3223: -- {((cs='1') and (read='1') and (reg_sel(18)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3225: -- psl filter_c_mask_write_access_cov : cover
3226: -- {((cs='1') and (write='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3228: -- psl filter_c_mask_read_access_cov : cover
3229: -- {((cs='1') and (read='1') and (reg_sel(19)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3231: -- psl filter_c_val_write_access_cov : cover
3232: -- {((cs='1') and (write='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3234: -- psl filter_c_val_read_access_cov : cover
3235: -- {((cs='1') and (read='1') and (reg_sel(20)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3237: -- psl filter_ran_low_write_access_cov : cover
3238: -- {((cs='1') and (write='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3240: -- psl filter_ran_low_read_access_cov : cover
3241: -- {((cs='1') and (read='1') and (reg_sel(21)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3243: -- psl filter_ran_high_write_access_cov : cover
3244: -- {((cs='1') and (write='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3246: -- psl filter_ran_high_read_access_cov : cover
3247: -- {((cs='1') and (read='1') and (reg_sel(22)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3249: -- psl filter_control_write_access_cov : cover
3250: -- {((cs='1') and (write='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))}; 3252: -- psl filter_control_read_access_cov : cover
3253: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(0)='1') or (be(1)='1')))}; 3255: -- psl filter_status_read_access_cov : cover
3256: -- {((cs='1') and (read='1') and (reg_sel(23)='1') and ((be(2)='1') or (be(3)='1')))}; 3258: -- psl rx_mem_info_read_access_cov : cover
3259: -- {((cs='1') and (read='1') and (reg_sel(24)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3261: -- psl rx_pointers_read_access_cov : cover
3262: -- {((cs='1') and (read='1') and (reg_sel(25)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3264: -- psl rx_status_read_access_cov : cover
3265: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(0)='1') or (be(1)='1')))}; 3267: -- psl rx_settings_write_access_cov : cover
3268: -- {((cs='1') and (write='1') and (reg_sel(26)='1') and ((be(2)='1')))}; 3270: -- psl rx_settings_read_access_cov : cover
3271: -- {((cs='1') and (read='1') and (reg_sel(26)='1') and ((be(2)='1')))}; 3273: -- psl rx_data_read_access_cov : cover
3274: -- {((cs='1') and (read='1') and (reg_sel(27)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3276: -- psl tx_status_read_access_cov : cover
3277: -- {((cs='1') and (read='1') and (reg_sel(28)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3279: -- psl tx_command_write_access_cov : cover
3280: -- {((cs='1') and (write='1') and (reg_sel(29)='1') and ((be(0)='1') or (be(1)='1')))}; 3282: -- psl txtb_info_read_access_cov : cover
3283: -- {((cs='1') and (read='1') and (reg_sel(29)='1') and ((be(2)='1') or (be(3)='1')))}; 3285: -- psl tx_priority_write_access_cov : cover
3286: -- {((cs='1') and (write='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3288: -- psl tx_priority_read_access_cov : cover
3289: -- {((cs='1') and (read='1') and (reg_sel(30)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3291: -- psl err_capt_read_access_cov : cover
3292: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(0)='1')))}; 3294: -- psl retr_ctr_read_access_cov : cover
3295: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(1)='1')))}; 3297: -- psl alc_read_access_cov : cover
3298: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(2)='1')))}; 3300: -- psl ts_info_read_access_cov : cover
3301: -- {((cs='1') and (read='1') and (reg_sel(31)='1') and ((be(3)='1')))}; 3303: -- psl trv_delay_read_access_cov : cover
3304: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(0)='1') or (be(1)='1')))}; 3306: -- psl ssp_cfg_write_access_cov : cover
3307: -- {((cs='1') and (write='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))}; 3309: -- psl ssp_cfg_read_access_cov : cover
3310: -- {((cs='1') and (read='1') and (reg_sel(32)='1') and ((be(2)='1') or (be(3)='1')))}; 3312: -- psl rx_fr_ctr_read_access_cov : cover
3313: -- {((cs='1') and (read='1') and (reg_sel(33)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3315: -- psl tx_fr_ctr_read_access_cov : cover
3316: -- {((cs='1') and (read='1') and (reg_sel(34)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3318: -- psl debug_register_read_access_cov : cover
3319: -- {((cs='1') and (read='1') and (reg_sel(35)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3321: -- psl yolo_reg_read_access_cov : cover
3322: -- {((cs='1') and (read='1') and (reg_sel(36)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3324: -- psl timestamp_low_read_access_cov : cover
3325: -- {((cs='1') and (read='1') and (reg_sel(37)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))}; 3327: -- psl timestamp_high_read_access_cov : cover
3328: -- {((cs='1') and (read='1') and (reg_sel(38)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};