NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
DP_INF_RAM_BE_INST	100.0 % (19/19)	100.0 % (14/14)	100.0 % (1578/1578)	90.0 % (27/30)	N.A.	N.A.	99.8 % (1638/1641)
PARITY_TRUE_GEN	100.0 % (14/14)	100.0 % (12/12)	100.0 % (66/66)	100.0 % (13/13)	N.A.	N.A.	100.0 % (105/105)
PARITY_FALSE_GEN	100.0 % (4/4)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (4/4)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST	100.0 % (19/19)	100.0 % (12/12)	100.0 % (516/516)	93.3 % (14/15)	N.A.	N.A.	99.8 % (561/562)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

208: txtb_port_b_data_out <= txtb_port_b_data_out_i;
Count: 104525
Threshold: 1

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0';

Count: 6708
Threshold: 1

Signal assignment statement on line 277:

277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
Count: 277
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 6431
Threshold: 1

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 55148111
Threshold: 1

Signal assignment statement on line 283:

283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
Count: 55090618
Threshold: 1

Signal assignment statement on line 285:

285: mr_tst_dest_tst_addr(4 downto 0);
Count: 57493
Threshold: 1

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb;

Count: 360482
Threshold: 1

Signal assignment statement on line 287:

287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
Count: 355003
Threshold: 1

Signal assignment statement on line 289:

289: mr_tst_control_twrstb;
Count: 5479
Threshold: 1

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata;

Count: 2228016
Threshold: 1

Signal assignment statement on line 291:

291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
Count: 2191339
Threshold: 1

Signal assignment statement on line 293:

293: mr_tst_wdata_tst_wdata;
Count: 36677
Threshold: 1

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0);

Count: 357714
Threshold: 1

Signal assignment statement on line 296:

296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
Count: 352550
Threshold: 1

Signal assignment statement on line 298:

298: mr_tst_dest_tst_addr(4 downto 0);
Count: 5164
Threshold: 1

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0');

Count: 106680
Threshold: 1

Signal assignment statement on line 300:

300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
Count: 2606
Threshold: 1

Signal assignment statement on line 302:

302: (others => '0');
Count: 104074
Threshold: 1

	Evaluated to	Count	Threshold
Bin	True	277	1
Bin	False	6431	1

	Evaluated to	Count	Threshold
Bin	True	55090618	1
Bin	False	57493	1

	Evaluated to	Count	Threshold
Bin	True	355003	1
Bin	False	5479	1

	Evaluated to	Count	Threshold
Bin	True	2191339	1
Bin	False	36677	1

	Evaluated to	Count	Threshold
Bin	True	352550	1
Bin	False	5164	1

	Evaluated to	Count	Threshold
Bin	True	2606	1
Bin	False	104074	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	592	1
Bin	(31)	1	0	2193	1
Bin	(30)	0	1	585	1
Bin	(30)	1	0	2186	1
Bin	(29)	0	1	591	1
Bin	(29)	1	0	2192	1
Bin	(28)	0	1	622	1
Bin	(28)	1	0	2223	1
Bin	(27)	0	1	629	1
Bin	(27)	1	0	2230	1
Bin	(26)	0	1	625	1
Bin	(26)	1	0	2226	1
Bin	(25)	0	1	608	1
Bin	(25)	1	0	2209	1
Bin	(24)	0	1	649	1
Bin	(24)	1	0	2250	1
Bin	(23)	0	1	605	1
Bin	(23)	1	0	2206	1
Bin	(22)	0	1	634	1
Bin	(22)	1	0	2235	1
Bin	(21)	0	1	623	1
Bin	(21)	1	0	2224	1
Bin	(20)	0	1	616	1
Bin	(20)	1	0	2217	1
Bin	(19)	0	1	626	1
Bin	(19)	1	0	2227	1
Bin	(18)	0	1	624	1
Bin	(18)	1	0	2225	1
Bin	(17)	0	1	614	1
Bin	(17)	1	0	2215	1
Bin	(16)	0	1	588	1
Bin	(16)	1	0	2189	1
Bin	(15)	0	1	624	1
Bin	(15)	1	0	2225	1
Bin	(14)	0	1	601	1
Bin	(14)	1	0	2202	1
Bin	(13)	0	1	611	1
Bin	(13)	1	0	2212	1
Bin	(12)	0	1	613	1
Bin	(12)	1	0	2214	1
Bin	(11)	0	1	608	1
Bin	(11)	1	0	2209	1
Bin	(10)	0	1	615	1
Bin	(10)	1	0	2216	1
Bin	(9)	0	1	630	1
Bin	(9)	1	0	2231	1
Bin	(8)	0	1	595	1
Bin	(8)	1	0	2196	1
Bin	(7)	0	1	627	1
Bin	(7)	1	0	2228	1
Bin	(6)	0	1	628	1
Bin	(6)	1	0	2229	1
Bin	(5)	0	1	610	1
Bin	(5)	1	0	2211	1
Bin	(4)	0	1	614	1
Bin	(4)	1	0	2215	1
Bin	(3)	0	1	614	1
Bin	(3)	1	0	2215	1
Bin	(2)	0	1	616	1
Bin	(2)	1	0	2217	1
Bin	(1)	0	1	618	1
Bin	(1)	1	0	2219	1
Bin	(0)	0	1	608	1
Bin	(0)	1	0	2209	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5571	1
Bin	(31)	1	0	7122	1
Bin	(30)	0	1	5866	1
Bin	(30)	1	0	7417	1
Bin	(29)	0	1	5604	1
Bin	(29)	1	0	7155	1
Bin	(28)	0	1	17418	1
Bin	(28)	1	0	18925	1
Bin	(27)	0	1	14252	1
Bin	(27)	1	0	15766	1
Bin	(26)	0	1	17436	1
Bin	(26)	1	0	18947	1
Bin	(25)	0	1	14725	1
Bin	(25)	1	0	16231	1
Bin	(24)	0	1	17826	1
Bin	(24)	1	0	19337	1
Bin	(23)	0	1	15159	1
Bin	(23)	1	0	16669	1
Bin	(22)	0	1	17818	1
Bin	(22)	1	0	19320	1
Bin	(21)	0	1	15780	1
Bin	(21)	1	0	17278	1
Bin	(20)	0	1	17859	1
Bin	(20)	1	0	19373	1
Bin	(19)	0	1	15423	1
Bin	(19)	1	0	16918	1
Bin	(18)	0	1	17682	1
Bin	(18)	1	0	19183	1
Bin	(17)	0	1	9919	1
Bin	(17)	1	0	11447	1
Bin	(16)	0	1	9985	1
Bin	(16)	1	0	11519	1
Bin	(15)	0	1	9994	1
Bin	(15)	1	0	11529	1
Bin	(14)	0	1	10030	1
Bin	(14)	1	0	11564	1
Bin	(13)	0	1	9871	1
Bin	(13)	1	0	11406	1
Bin	(12)	0	1	9958	1
Bin	(12)	1	0	11493	1
Bin	(11)	0	1	9864	1
Bin	(11)	1	0	11403	1
Bin	(10)	0	1	11597	1
Bin	(10)	1	0	13059	1
Bin	(9)	0	1	19126	1
Bin	(9)	1	0	20535	1
Bin	(8)	0	1	10644	1
Bin	(8)	1	0	12178	1
Bin	(7)	0	1	24560	1
Bin	(7)	1	0	25796	1
Bin	(6)	0	1	16021	1
Bin	(6)	1	0	17439	1
Bin	(5)	0	1	13278	1
Bin	(5)	1	0	14805	1
Bin	(4)	0	1	12313	1
Bin	(4)	1	0	13845	1
Bin	(3)	0	1	19273	1
Bin	(3)	1	0	20731	1
Bin	(2)	0	1	20220	1
Bin	(2)	1	0	21656	1
Bin	(1)	0	1	20404	1
Bin	(1)	1	0	21848	1
Bin	(0)	0	1	27232	1
Bin	(0)	1	0	28510	1

Port:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1728	1
Bin	1	0	3329	1

Signal:

TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	328851	1
Bin	(4)	1	0	27172468	1
Bin	(3)	0	1	588369	1
Bin	(3)	1	0	26912904	1
Bin	(2)	0	1	446246	1
Bin	(2)	1	0	27055495	1
Bin	(1)	0	1	26729430	1
Bin	(1)	1	0	773237	1
Bin	(0)	0	1	17573467	1
Bin	(0)	1	0	9931137	1

Signal:

TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	128890	1
Bin	1	0	130617	1

Signal:

TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	68975	1
Bin	(31)	1	0	1022800	1
Bin	(30)	0	1	72700	1
Bin	(30)	1	0	1019073	1
Bin	(29)	0	1	72794	1
Bin	(29)	1	0	1019003	1
Bin	(28)	0	1	98557	1
Bin	(28)	1	0	993272	1
Bin	(27)	0	1	89783	1
Bin	(27)	1	0	1002032	1
Bin	(26)	0	1	87723	1
Bin	(26)	1	0	1004082	1
Bin	(25)	0	1	92656	1
Bin	(25)	1	0	999135	1
Bin	(24)	0	1	85577	1
Bin	(24)	1	0	1006252	1
Bin	(23)	0	1	77832	1
Bin	(23)	1	0	1013977	1
Bin	(22)	0	1	112136	1
Bin	(22)	1	0	979691	1
Bin	(21)	0	1	77579	1
Bin	(21)	1	0	1014234	1
Bin	(20)	0	1	86947	1
Bin	(20)	1	0	1004874	1
Bin	(19)	0	1	115185	1
Bin	(19)	1	0	976641	1
Bin	(18)	0	1	128939	1
Bin	(18)	1	0	962890	1
Bin	(17)	0	1	121142	1
Bin	(17)	1	0	970708	1
Bin	(16)	0	1	191327	1
Bin	(16)	1	0	900509	1
Bin	(15)	0	1	78403	1
Bin	(15)	1	0	1013428	1
Bin	(14)	0	1	93700	1
Bin	(14)	1	0	998133	1
Bin	(13)	0	1	82753	1
Bin	(13)	1	0	1009064	1
Bin	(12)	0	1	85762	1
Bin	(12)	1	0	1006065	1
Bin	(11)	0	1	105081	1
Bin	(11)	1	0	986744	1
Bin	(10)	0	1	126557	1
Bin	(10)	1	0	965268	1
Bin	(9)	0	1	181196	1
Bin	(9)	1	0	910661	1
Bin	(8)	0	1	157310	1
Bin	(8)	1	0	934511	1
Bin	(7)	0	1	133235	1
Bin	(7)	1	0	958600	1
Bin	(6)	0	1	115090	1
Bin	(6)	1	0	976763	1
Bin	(5)	0	1	108549	1
Bin	(5)	1	0	983276	1
Bin	(4)	0	1	167018	1
Bin	(4)	1	0	924813	1
Bin	(3)	0	1	142685	1
Bin	(3)	1	0	949109	1
Bin	(2)	0	1	167305	1
Bin	(2)	1	0	924545	1
Bin	(1)	0	1	235172	1
Bin	(1)	1	0	856679	1
Bin	(0)	0	1	196094	1
Bin	(0)	1	0	895809	1

Signal:

TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	27452	1
Bin	(4)	1	0	29053	1
Bin	(3)	0	1	3987	1
Bin	(3)	1	0	5588	1
Bin	(2)	0	1	47073	1
Bin	(2)	1	0	48674	1
Bin	(1)	0	1	39174	1
Bin	(1)	1	0	39178	1
Bin	(0)	0	1	104287	1
Bin	(0)	1	0	105884	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5571	1
Bin	(31)	1	0	7122	1
Bin	(30)	0	1	5866	1
Bin	(30)	1	0	7417	1
Bin	(29)	0	1	5604	1
Bin	(29)	1	0	7155	1
Bin	(28)	0	1	17418	1
Bin	(28)	1	0	18925	1
Bin	(27)	0	1	14252	1
Bin	(27)	1	0	15766	1
Bin	(26)	0	1	17436	1
Bin	(26)	1	0	18947	1
Bin	(25)	0	1	14725	1
Bin	(25)	1	0	16231	1
Bin	(24)	0	1	17826	1
Bin	(24)	1	0	19337	1
Bin	(23)	0	1	15159	1
Bin	(23)	1	0	16669	1
Bin	(22)	0	1	17818	1
Bin	(22)	1	0	19320	1
Bin	(21)	0	1	15780	1
Bin	(21)	1	0	17278	1
Bin	(20)	0	1	17859	1
Bin	(20)	1	0	19373	1
Bin	(19)	0	1	15423	1
Bin	(19)	1	0	16918	1
Bin	(18)	0	1	17682	1
Bin	(18)	1	0	19183	1
Bin	(17)	0	1	9919	1
Bin	(17)	1	0	11447	1
Bin	(16)	0	1	9985	1
Bin	(16)	1	0	11519	1
Bin	(15)	0	1	9994	1
Bin	(15)	1	0	11529	1
Bin	(14)	0	1	10030	1
Bin	(14)	1	0	11564	1
Bin	(13)	0	1	9871	1
Bin	(13)	1	0	11406	1
Bin	(12)	0	1	9958	1
Bin	(12)	1	0	11493	1
Bin	(11)	0	1	9864	1
Bin	(11)	1	0	11403	1
Bin	(10)	0	1	11597	1
Bin	(10)	1	0	13059	1
Bin	(9)	0	1	19126	1
Bin	(9)	1	0	20535	1
Bin	(8)	0	1	10644	1
Bin	(8)	1	0	12178	1
Bin	(7)	0	1	24560	1
Bin	(7)	1	0	25796	1
Bin	(6)	0	1	16021	1
Bin	(6)	1	0	17439	1
Bin	(5)	0	1	13278	1
Bin	(5)	1	0	14805	1
Bin	(4)	0	1	12313	1
Bin	(4)	1	0	13845	1
Bin	(3)	0	1	19273	1
Bin	(3)	1	0	20731	1
Bin	(2)	0	1	20220	1
Bin	(2)	1	0	21656	1
Bin	(1)	0	1	20404	1
Bin	(1)	1	0	21848	1
Bin	(0)	0	1	27232	1
Bin	(0)	1	0	28510	1

Signal:

TST_ENA

	From	To	Count	Threshold
Bin	0	1	277	1
Bin	1	0	1878	1

Signal:

PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	141	1
Bin	(20)	1	0	4777	1
Bin	(19)	0	1	4	1
Bin	(19)	1	0	4914	1
Bin	(18)	0	1	12	1
Bin	(18)	1	0	4906	1
Bin	(17)	0	1	223	1
Bin	(17)	1	0	4695	1
Bin	(16)	0	1	223	1
Bin	(16)	1	0	4695	1
Bin	(15)	0	1	242	1
Bin	(15)	1	0	4676	1
Bin	(14)	0	1	190	1
Bin	(14)	1	0	4728	1
Bin	(13)	0	1	90	1
Bin	(13)	1	0	4828	1
Bin	(12)	0	1	102	1
Bin	(12)	1	0	4816	1
Bin	(11)	0	1	363	1
Bin	(11)	1	0	4555	1
Bin	(10)	0	1	252	1
Bin	(10)	1	0	4666	1
Bin	(9)	0	1	316	1
Bin	(9)	1	0	4602	1
Bin	(8)	0	1	185	1
Bin	(8)	1	0	4733	1
Bin	(7)	0	1	231	1
Bin	(7)	1	0	4687	1
Bin	(6)	0	1	422	1
Bin	(6)	1	0	4496	1
Bin	(5)	0	1	661	1
Bin	(5)	1	0	4257	1
Bin	(4)	0	1	1203	1
Bin	(4)	1	0	3715	1
Bin	(3)	0	1	2151	1
Bin	(3)	1	0	2767	1
Bin	(2)	0	1	2533	1
Bin	(2)	1	0	2385	1
Bin	(1)	0	1	1523	1
Bin	(1)	1	0	3395	1
Bin	(0)	0	1	1519	1
Bin	(0)	1	0	3399	1

Signal:

PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	6968	1
Bin	1	0	7336	1

Signal:

PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	7329	1
Bin	1	0	8930	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_odd.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement on line 208:

If statement on lines 277 to 280:

Signal assignment statement on line 277:

Signal assignment statement on line 280:

If statement on lines 283 to 285:

Signal assignment statement on line 283:

Signal assignment statement on line 285:

If statement on lines 287 to 289:

Signal assignment statement on line 287:

Signal assignment statement on line 289:

If statement on lines 291 to 293:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 296 to 298:

Signal assignment statement on line 296:

Signal assignment statement on line 298:

If statement on lines 300 to 302:

Signal assignment statement on line 300:

Signal assignment statement on line 302:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on lines 277 to 278:

"if" / "when" / "else" condition on line 283:

"if" / "when" / "else" condition on line 287:

"if" / "when" / "else" condition on line 291:

"if" / "when" / "else" condition on line 296:

"if" / "when" / "else" condition on line 300:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

"and" expression on lines 277 to 278:

Excluded expressions:

Covered expressions:

"and" expression on lines 277 to 278:

"=" expression on line 277:

"=" expression on line 283:

"=" expression on line 287:

"=" expression on line 291:

"=" expression on line 296:

"=" expression on line 300:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage: