Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| DP_INF_RAM_BE_INST |
100.0 % (19/19) |
100.0 % (14/14) |
100.0 % (1578/1578) |
100.0 % (30/30) |
N.A. |
N.A. |
100.0 % (1641/1641) |
| PARITY_TRUE_GEN |
100.0 % (14/14) |
100.0 % (12/12) |
100.0 % (66/66) |
100.0 % (17/17) |
N.A. |
N.A. |
100.0 % (109/109) |
| PARITY_FALSE_GEN |
100.0 % (4/4) |
N.A. |
N.A. |
N.A. |
N.A. |
N.A. |
100.0 % (4/4) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4)))
279: else
280: '0'; Count: 6706
Threshold: 1
Signal assignment statement:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and Count: 278
Threshold: 1
Signal assignment statement:
280: '0'; Count: 6428
Threshold: 1
If statement:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0')
284: else
285: mr_tst_dest_tst_addr(4 downto 0); Count: 55685099
Threshold: 1
Signal assignment statement:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') Count: 55627585
Threshold: 1
Signal assignment statement:
285: mr_tst_dest_tst_addr(4 downto 0); Count: 57514
Threshold: 1
If statement:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0')
288: else
289: mr_tst_control_twrstb; Count: 359563
Threshold: 1
Signal assignment statement:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') Count: 354081
Threshold: 1
Signal assignment statement:
289: mr_tst_control_twrstb; Count: 5482
Threshold: 1
If statement:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0')
292: else
293: mr_tst_wdata_tst_wdata; Count: 2193273
Threshold: 1
Signal assignment statement:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') Count: 2156587
Threshold: 1
Signal assignment statement:
293: mr_tst_wdata_tst_wdata; Count: 36686
Threshold: 1
If statement:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0')
297: else
298: mr_tst_dest_tst_addr(4 downto 0); Count: 353605
Threshold: 1
Signal assignment statement:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') Count: 348432
Threshold: 1
Signal assignment statement:
298: mr_tst_dest_tst_addr(4 downto 0); Count: 5173
Threshold: 1
If statement:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1')
301: else
302: (others => '0'); Count: 106332
Threshold: 1
Signal assignment statement:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') Count: 2618
Threshold: 1
Signal assignment statement:
302: (others => '0'); Count: 103714
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 278 | 1 |
| Bin | False | 6428 | 1 |
"if" / "when" / "else" condition:
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 55627585 | 1 |
| Bin | False | 57514 | 1 |
"if" / "when" / "else" condition:
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 354081 | 1 |
| Bin | False | 5482 | 1 |
"if" / "when" / "else" condition:
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2156587 | 1 |
| Bin | False | 36686 | 1 |
"if" / "when" / "else" condition:
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 348432 | 1 |
| Bin | False | 5173 | 1 |
"if" / "when" / "else" condition:
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2618 | 1 |
| Bin | False | 103714 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14022469 | 1 |
| Bin | 1 | 0 | 14024069 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 648 | 1 |
| Bin | 1 | 0 | 2248 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32309 | 1 |
| Bin | 1 | 0 | 35200 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3617 | 1 |
| Bin | 1 | 0 | 5217 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5031 | 1 |
| Bin | 1 | 0 | 6631 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10323 | 1 |
| Bin | 1 | 0 | 11923 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22448 | 1 |
| Bin | 1 | 0 | 24048 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44884 | 1 |
| Bin | 1 | 0 | 46484 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1835 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 2114 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 979 | 1 |
| Bin | 1 | 0 | 2579 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1535 | 1 |
| Bin | 1 | 0 | 3135 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1484 | 1 |
| Bin | 1 | 0 | 3084 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1491 | 1 |
| Bin | 1 | 0 | 3091 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1631 | 1 |
| Bin | 1 | 0 | 3231 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 3245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 3229 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1641 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 3313 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1587 | 1 |
| Bin | 1 | 0 | 3187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1526 | 1 |
| Bin | 1 | 0 | 3126 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1560 | 1 |
| Bin | 1 | 0 | 3160 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1658 | 1 |
| Bin | 1 | 0 | 3258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1636 | 1 |
| Bin | 1 | 0 | 3236 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1632 | 1 |
| Bin | 1 | 0 | 3232 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 3270 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1575 | 1 |
| Bin | 1 | 0 | 3175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1501 | 1 |
| Bin | 1 | 0 | 3101 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1559 | 1 |
| Bin | 1 | 0 | 3159 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 3272 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1681 | 1 |
| Bin | 1 | 0 | 3281 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1633 | 1 |
| Bin | 1 | 0 | 3233 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1567 | 1 |
| Bin | 1 | 0 | 3167 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1601 | 1 |
| Bin | 1 | 0 | 3201 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1637 | 1 |
| Bin | 1 | 0 | 3237 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1655 | 1 |
| Bin | 1 | 0 | 3255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1656 | 1 |
| Bin | 1 | 0 | 3256 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1722 | 1 |
| Bin | 1 | 0 | 3322 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609 | 1 |
| Bin | 1 | 0 | 2209 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 594 | 1 |
| Bin | 1 | 0 | 2194 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 580 | 1 |
| Bin | 1 | 0 | 2180 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 2232 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 616 | 1 |
| Bin | 1 | 0 | 2216 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 642 | 1 |
| Bin | 1 | 0 | 2242 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635 | 1 |
| Bin | 1 | 0 | 2235 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 621 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609 | 1 |
| Bin | 1 | 0 | 2209 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 631 | 1 |
| Bin | 1 | 0 | 2231 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 613 | 1 |
| Bin | 1 | 0 | 2213 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 634 | 1 |
| Bin | 1 | 0 | 2234 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 589 | 1 |
| Bin | 1 | 0 | 2189 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 613 | 1 |
| Bin | 1 | 0 | 2213 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 602 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 626 | 1 |
| Bin | 1 | 0 | 2226 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 612 | 1 |
| Bin | 1 | 0 | 2212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 601 | 1 |
| Bin | 1 | 0 | 2201 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 2232 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 605 | 1 |
| Bin | 1 | 0 | 2205 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617 | 1 |
| Bin | 1 | 0 | 2217 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 611 | 1 |
| Bin | 1 | 0 | 2211 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 630 | 1 |
| Bin | 1 | 0 | 2230 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617 | 1 |
| Bin | 1 | 0 | 2217 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27467073 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27219534 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27359554 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 780396 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10140384 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61362 | 1 |
| Bin | 1 | 0 | 1030083 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67108 | 1 |
| Bin | 1 | 0 | 1024337 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63097 | 1 |
| Bin | 1 | 0 | 1028348 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91439 | 1 |
| Bin | 1 | 0 | 1000006 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79643 | 1 |
| Bin | 1 | 0 | 1011802 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76527 | 1 |
| Bin | 1 | 0 | 1014918 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88276 | 1 |
| Bin | 1 | 0 | 1003169 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78188 | 1 |
| Bin | 1 | 0 | 1013257 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70931 | 1 |
| Bin | 1 | 0 | 1020514 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108138 | 1 |
| Bin | 1 | 0 | 983307 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74867 | 1 |
| Bin | 1 | 0 | 1016578 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80468 | 1 |
| Bin | 1 | 0 | 1010977 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110009 | 1 |
| Bin | 1 | 0 | 981436 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 131558 | 1 |
| Bin | 1 | 0 | 959887 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123951 | 1 |
| Bin | 1 | 0 | 967494 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 193513 | 1 |
| Bin | 1 | 0 | 897932 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72382 | 1 |
| Bin | 1 | 0 | 1019063 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 86120 | 1 |
| Bin | 1 | 0 | 1005325 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76572 | 1 |
| Bin | 1 | 0 | 1014873 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80428 | 1 |
| Bin | 1 | 0 | 1011017 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 97296 | 1 |
| Bin | 1 | 0 | 994149 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116973 | 1 |
| Bin | 1 | 0 | 974472 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170870 | 1 |
| Bin | 1 | 0 | 920575 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 150526 | 1 |
| Bin | 1 | 0 | 940919 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126416 | 1 |
| Bin | 1 | 0 | 965029 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109550 | 1 |
| Bin | 1 | 0 | 981895 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103929 | 1 |
| Bin | 1 | 0 | 987516 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162358 | 1 |
| Bin | 1 | 0 | 929087 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135873 | 1 |
| Bin | 1 | 0 | 955572 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 159944 | 1 |
| Bin | 1 | 0 | 931501 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236123 | 1 |
| Bin | 1 | 0 | 855322 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 198401 | 1 |
| Bin | 1 | 0 | 893044 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 150105 | 1 |
Port:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 127349 | 1 |
| Bin | 1 | 0 | 128949 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26805 | 1 |
| Bin | 1 | 0 | 28405 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3865 | 1 |
| Bin | 1 | 0 | 5465 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45730 | 1 |
| Bin | 1 | 0 | 47330 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37881 | 1 |
| Bin | 1 | 0 | 37884 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101251 | 1 |
| Bin | 1 | 0 | 102848 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5911 | 1 |
| Bin | 1 | 0 | 7461 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6110 | 1 |
| Bin | 1 | 0 | 7660 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5834 | 1 |
| Bin | 1 | 0 | 7384 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17432 | 1 |
| Bin | 1 | 0 | 18943 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13971 | 1 |
| Bin | 1 | 0 | 15477 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17362 | 1 |
| Bin | 1 | 0 | 18871 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14054 | 1 |
| Bin | 1 | 0 | 15563 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17509 | 1 |
| Bin | 1 | 0 | 19012 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15147 | 1 |
| Bin | 1 | 0 | 16651 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18083 | 1 |
| Bin | 1 | 0 | 19582 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15194 | 1 |
| Bin | 1 | 0 | 16701 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17639 | 1 |
| Bin | 1 | 0 | 19138 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15448 | 1 |
| Bin | 1 | 0 | 16941 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18091 | 1 |
| Bin | 1 | 0 | 19592 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9683 | 1 |
| Bin | 1 | 0 | 11211 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10009 | 1 |
| Bin | 1 | 0 | 11537 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9772 | 1 |
| Bin | 1 | 0 | 11302 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10207 | 1 |
| Bin | 1 | 0 | 11734 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9974 | 1 |
| Bin | 1 | 0 | 11508 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10274 | 1 |
| Bin | 1 | 0 | 11806 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9752 | 1 |
| Bin | 1 | 0 | 11286 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10975 | 1 |
| Bin | 1 | 0 | 12443 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19591 | 1 |
| Bin | 1 | 0 | 21006 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10936 | 1 |
| Bin | 1 | 0 | 12467 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25055 | 1 |
| Bin | 1 | 0 | 26299 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15897 | 1 |
| Bin | 1 | 0 | 17314 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12775 | 1 |
| Bin | 1 | 0 | 14291 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11644 | 1 |
| Bin | 1 | 0 | 13169 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19107 | 1 |
| Bin | 1 | 0 | 20566 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20639 | 1 |
| Bin | 1 | 0 | 22069 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20586 | 1 |
| Bin | 1 | 0 | 22025 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26883 | 1 |
| Bin | 1 | 0 | 28179 | 1 |
Port:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1822 | 1 |
| Bin | 1 | 0 | 3422 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328745 | 1 |
| Bin | 1 | 0 | 27441088 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576261 | 1 |
| Bin | 1 | 0 | 27193526 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436476 | 1 |
| Bin | 1 | 0 | 27333781 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27004643 | 1 |
| Bin | 1 | 0 | 766548 | 1 |
Signal:
TXTB_PORT_A_ADDRESS_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17636608 | 1 |
| Bin | 1 | 0 | 10136529 | 1 |
Signal:
TXTB_PORT_A_WRITE_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 128483 | 1 |
| Bin | 1 | 0 | 130209 | 1 |
Signal:
TXTB_PORT_A_DATA_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60783 | 1 |
| Bin | 1 | 0 | 1013666 | 1 |
Signal:
TXTB_PORT_A_DATA_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 66537 | 1 |
| Bin | 1 | 0 | 1007922 | 1 |
Signal:
TXTB_PORT_A_DATA_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62515 | 1 |
| Bin | 1 | 0 | 1011916 | 1 |
Signal:
TXTB_PORT_A_DATA_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 90878 | 1 |
| Bin | 1 | 0 | 983585 | 1 |
Signal:
TXTB_PORT_A_DATA_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79071 | 1 |
| Bin | 1 | 0 | 995406 | 1 |
Signal:
TXTB_PORT_A_DATA_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75974 | 1 |
| Bin | 1 | 0 | 998499 | 1 |
Signal:
TXTB_PORT_A_DATA_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87661 | 1 |
| Bin | 1 | 0 | 986836 | 1 |
Signal:
TXTB_PORT_A_DATA_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77613 | 1 |
| Bin | 1 | 0 | 996848 | 1 |
Signal:
TXTB_PORT_A_DATA_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70382 | 1 |
| Bin | 1 | 0 | 1004097 | 1 |
Signal:
TXTB_PORT_A_DATA_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107578 | 1 |
| Bin | 1 | 0 | 966877 | 1 |
Signal:
TXTB_PORT_A_DATA_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74303 | 1 |
| Bin | 1 | 0 | 1000152 | 1 |
Signal:
TXTB_PORT_A_DATA_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79911 | 1 |
| Bin | 1 | 0 | 994548 | 1 |
Signal:
TXTB_PORT_A_DATA_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107845 | 1 |
| Bin | 1 | 0 | 966640 | 1 |
Signal:
TXTB_PORT_A_DATA_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126102 | 1 |
| Bin | 1 | 0 | 948389 | 1 |
Signal:
TXTB_PORT_A_DATA_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116846 | 1 |
| Bin | 1 | 0 | 957659 | 1 |
Signal:
TXTB_PORT_A_DATA_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 186370 | 1 |
| Bin | 1 | 0 | 888125 | 1 |
Signal:
TXTB_PORT_A_DATA_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71823 | 1 |
| Bin | 1 | 0 | 1002646 | 1 |
Signal:
TXTB_PORT_A_DATA_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 85544 | 1 |
| Bin | 1 | 0 | 988909 | 1 |
Signal:
TXTB_PORT_A_DATA_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76003 | 1 |
| Bin | 1 | 0 | 998468 | 1 |
Signal:
TXTB_PORT_A_DATA_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79870 | 1 |
| Bin | 1 | 0 | 994611 | 1 |
Signal:
TXTB_PORT_A_DATA_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96729 | 1 |
| Bin | 1 | 0 | 977726 | 1 |
Signal:
TXTB_PORT_A_DATA_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116412 | 1 |
| Bin | 1 | 0 | 958051 | 1 |
Signal:
TXTB_PORT_A_DATA_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170250 | 1 |
| Bin | 1 | 0 | 904229 | 1 |
Signal:
TXTB_PORT_A_DATA_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 149946 | 1 |
| Bin | 1 | 0 | 924523 | 1 |
Signal:
TXTB_PORT_A_DATA_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 125852 | 1 |
| Bin | 1 | 0 | 948641 | 1 |
Signal:
TXTB_PORT_A_DATA_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108987 | 1 |
| Bin | 1 | 0 | 965508 | 1 |
Signal:
TXTB_PORT_A_DATA_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103371 | 1 |
| Bin | 1 | 0 | 971122 | 1 |
Signal:
TXTB_PORT_A_DATA_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 159430 | 1 |
| Bin | 1 | 0 | 915041 | 1 |
Signal:
TXTB_PORT_A_DATA_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130837 | 1 |
| Bin | 1 | 0 | 943640 | 1 |
Signal:
TXTB_PORT_A_DATA_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 154748 | 1 |
| Bin | 1 | 0 | 919733 | 1 |
Signal:
TXTB_PORT_A_DATA_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 227152 | 1 |
| Bin | 1 | 0 | 847333 | 1 |
Signal:
TXTB_PORT_A_DATA_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 190168 | 1 |
| Bin | 1 | 0 | 884384 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26995 | 1 |
| Bin | 1 | 0 | 28595 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4027 | 1 |
| Bin | 1 | 0 | 5627 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46132 | 1 |
| Bin | 1 | 0 | 47732 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 38898 | 1 |
| Bin | 1 | 0 | 38901 | 1 |
Signal:
TXTB_PORT_B_ADDRESS_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102952 | 1 |
| Bin | 1 | 0 | 104549 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5911 | 1 |
| Bin | 1 | 0 | 7461 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6110 | 1 |
| Bin | 1 | 0 | 7660 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5834 | 1 |
| Bin | 1 | 0 | 7384 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17432 | 1 |
| Bin | 1 | 0 | 18943 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13971 | 1 |
| Bin | 1 | 0 | 15477 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17362 | 1 |
| Bin | 1 | 0 | 18871 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14054 | 1 |
| Bin | 1 | 0 | 15563 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17509 | 1 |
| Bin | 1 | 0 | 19012 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15147 | 1 |
| Bin | 1 | 0 | 16651 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18083 | 1 |
| Bin | 1 | 0 | 19582 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15194 | 1 |
| Bin | 1 | 0 | 16701 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17639 | 1 |
| Bin | 1 | 0 | 19138 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15448 | 1 |
| Bin | 1 | 0 | 16941 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18091 | 1 |
| Bin | 1 | 0 | 19592 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9683 | 1 |
| Bin | 1 | 0 | 11211 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10009 | 1 |
| Bin | 1 | 0 | 11537 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9772 | 1 |
| Bin | 1 | 0 | 11302 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10207 | 1 |
| Bin | 1 | 0 | 11734 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9974 | 1 |
| Bin | 1 | 0 | 11508 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10274 | 1 |
| Bin | 1 | 0 | 11806 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9752 | 1 |
| Bin | 1 | 0 | 11286 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10975 | 1 |
| Bin | 1 | 0 | 12443 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19591 | 1 |
| Bin | 1 | 0 | 21006 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10936 | 1 |
| Bin | 1 | 0 | 12467 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25055 | 1 |
| Bin | 1 | 0 | 26299 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15897 | 1 |
| Bin | 1 | 0 | 17314 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12775 | 1 |
| Bin | 1 | 0 | 14291 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11644 | 1 |
| Bin | 1 | 0 | 13169 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19107 | 1 |
| Bin | 1 | 0 | 20566 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20639 | 1 |
| Bin | 1 | 0 | 22069 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20586 | 1 |
| Bin | 1 | 0 | 22025 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26883 | 1 |
| Bin | 1 | 0 | 28179 | 1 |
Signal:
TST_ENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 278 | 1 |
| Bin | 1 | 0 | 1878 | 1 |
Signal:
PARITY_WORD(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141 | 1 |
| Bin | 1 | 0 | 4864 | 1 |
Signal:
PARITY_WORD(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8 | 1 |
| Bin | 1 | 0 | 4997 | 1 |
Signal:
PARITY_WORD(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18 | 1 |
| Bin | 1 | 0 | 4987 | 1 |
Signal:
PARITY_WORD(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 259 | 1 |
| Bin | 1 | 0 | 4746 | 1 |
Signal:
PARITY_WORD(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 258 | 1 |
| Bin | 1 | 0 | 4747 | 1 |
Signal:
PARITY_WORD(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 301 | 1 |
| Bin | 1 | 0 | 4704 | 1 |
Signal:
PARITY_WORD(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 218 | 1 |
| Bin | 1 | 0 | 4787 | 1 |
Signal:
PARITY_WORD(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 4900 | 1 |
Signal:
PARITY_WORD(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 128 | 1 |
| Bin | 1 | 0 | 4877 | 1 |
Signal:
PARITY_WORD(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 399 | 1 |
| Bin | 1 | 0 | 4606 | 1 |
Signal:
PARITY_WORD(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 278 | 1 |
| Bin | 1 | 0 | 4727 | 1 |
Signal:
PARITY_WORD(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 391 | 1 |
| Bin | 1 | 0 | 4614 | 1 |
Signal:
PARITY_WORD(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 225 | 1 |
| Bin | 1 | 0 | 4780 | 1 |
Signal:
PARITY_WORD(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 277 | 1 |
| Bin | 1 | 0 | 4728 | 1 |
Signal:
PARITY_WORD(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 451 | 1 |
| Bin | 1 | 0 | 4554 | 1 |
Signal:
PARITY_WORD(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 742 | 1 |
| Bin | 1 | 0 | 4263 | 1 |
Signal:
PARITY_WORD(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1233 | 1 |
| Bin | 1 | 0 | 3772 | 1 |
Signal:
PARITY_WORD(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2190 | 1 |
| Bin | 1 | 0 | 2815 | 1 |
Signal:
PARITY_WORD(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2578 | 1 |
| Bin | 1 | 0 | 2427 | 1 |
Signal:
PARITY_WORD(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1570 | 1 |
| Bin | 1 | 0 | 3435 | 1 |
Signal:
PARITY_WORD(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1618 | 1 |
| Bin | 1 | 0 | 3387 | 1 |
Signal:
PARITY_READ_REAL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6892 | 1 |
| Bin | 1 | 0 | 7263 | 1 |
Signal:
PARITY_READ_EXP | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7680 | 1 |
| Bin | 1 | 0 | 9280 | 1 |
Excluded expressions:
"and" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | LHS | RHS | Count | Threshold | Excluded due to |
|---|
| Bin | False | True | 0 | 1 | Unreachable |
Covered expressions:
"=" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4855 | 1 |
| Bin | True | 1851 | 1 |
"and" expression
277: tst_ena <= '1' when (mr_tst_control_tmaena = '1') and
278: (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) | LHS | RHS | Count | Threshold |
|---|
| Bin | True | False | 1573 | 1 |
| Bin | True | True | 278 | 1 |
"=" expression
283: txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 57514 | 1 |
| Bin | True | 55627585 | 1 |
"=" expression
287: txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5482 | 1 |
| Bin | True | 354081 | 1 |
"=" expression
291: txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 36686 | 1 |
| Bin | True | 2156587 | 1 |
"=" expression
296: txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5173 | 1 |
| Bin | True | 348432 | 1 |
"=" expression
300: mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 103714 | 1 |
| Bin | True | 2618 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: