NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_GEN(2)

File:  /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/address_decoder.vhd


Current Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.ADDRESS_DECODER_CONTROL_REGISTERS_COMP.ADDR_DEC_GEN(2) 100.0 % (3/3) 100.0 % (2/2) N.A. N.A. N.A. N.A. 100.0 % (5/5)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.


Statement Branch Toggle Expression FSM state Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 144 to 146:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
145:                             else 
146:                         '0'; 
Count: 55054226
Threshold: 1

Signal assignment statement on line 144:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
Count: 9428029
Threshold: 1

Signal assignment statement on line 146:

146:                         '0'; 
Count: 45626197
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 144:

144:        addr_dec_i(i) <= '1' when (address = addr_vect(h_ind downto l_ind)) 
Evaluated toCountThreshold
BinTrue94280291
BinFalse456261971

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

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Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: