NVC code coverage report

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
TX_CTR_REG_RST_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)
RX_CTR_REG_RST_INST	100.0 % (6/6)	100.0 % (6/6)	100.0 % (28/28)	100.0 % (2/2)	N.A.	N.A.	100.0 % (42/42)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST	100.0 % (25/25)	100.0 % (22/22)	100.0 % (410/410)	100.0 % (16/16)	N.A.	N.A.	100.0 % (473/473)

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 156 to 162:

156:        if (res_n = '0') then 
157:            tran_valid_q <= '0'; 
...
161:            rec_valid_q <= rec_valid; 
162:        end if;

Count: 165318284
Threshold: 1

Signal assignment statement on line 157:

157: tran_valid_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 158:

158: rec_valid_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 160:

160: tran_valid_q <= tran_valid;
Count: 81788549
Threshold: 1

Signal assignment statement on line 161:

161: rec_valid_q <= rec_valid;
Count: 81788549
Threshold: 1

Signal assignment statement on line 165:

165: tx_frame_ctr <= tx_frame_ctr_i;
Count: 6260
Threshold: 1

Signal assignment statement on line 166:

166: rx_frame_ctr <= rx_frame_ctr_i;
Count: 13539
Threshold: 1

If statement on lines 169 to 171:

169:    sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1') 
170:                                          else 
171:                 unsigned(rx_frame_ctr_i);

Count: 22623
Threshold: 1

Signal assignment statement on line 169:

169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1')
Count: 3820
Threshold: 1

Signal assignment statement on line 171:

171: unsigned(rx_frame_ctr_i);
Count: 18803
Threshold: 1

Signal assignment statement on line 174:

174: inc_value <= sel_value + 1;
Count: 19963
Threshold: 1

If statement on lines 179 to 181:

179:    tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1') 
180:                          else 
181:                      '1';

Count: 4122
Threshold: 1

Signal assignment statement on line 179:

179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1')
Count: 124
Threshold: 1

Signal assignment statement on line 181:

181: '1';
Count: 3998
Threshold: 1

If statement on lines 183 to 185:

183:    rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1') 
184:                          else 
185:                      '1';

Count: 4122
Threshold: 1

Signal assignment statement on line 183:

183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1')
Count: 124
Threshold: 1

Signal assignment statement on line 185:

185: '1';
Count: 3998
Threshold: 1

If statement on lines 229 to 235:

229:        if (tx_ctr_rst_n_q_scan = '0') then 
230:            tx_frame_ctr_i <= (others => '0'); 
...
234:            end if; 
235:        end if;

Count: 165318532
Threshold: 1

Signal assignment statement on line 230:

230: tx_frame_ctr_i <= (others => '0');
Count: 1742422
Threshold: 1

If statement on lines 232 to 234:

232:            if (tran_valid_q = '1') then 
233:                tx_frame_ctr_i <= std_logic_vector(inc_value); 
234:            end if;

Count: 81786241
Threshold: 1

Signal assignment statement on line 233:

233: tx_frame_ctr_i <= std_logic_vector(inc_value);
Count: 3820
Threshold: 1

If statement on lines 243 to 249:

243:        if (rx_ctr_rst_n_q_scan = '0') then 
244:            rx_frame_ctr_i <= (others => '0'); 
...
248:            end if; 
249:        end if;

Count: 165318532
Threshold: 1

Signal assignment statement on line 244:

244: rx_frame_ctr_i <= (others => '0');
Count: 1742422
Threshold: 1

If statement on lines 246 to 248:

246:            if (rec_valid_q = '1') then 
247:                rx_frame_ctr_i <= std_logic_vector(inc_value); 
248:            end if;

Count: 81786241
Threshold: 1

Signal assignment statement on line 247:

247: rx_frame_ctr_i <= std_logic_vector(inc_value);
Count: 11502
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 156:

156: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1737682	1
Bin	False	163580602	1

"if" / "when" / "else" condition on line 159:

159: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	81788549	1
Bin	False	81792053	1

"if" / "when" / "else" condition on line 169:

169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1')

	Evaluated to	Count	Threshold
Bin	True	3820	1
Bin	False	18803	1

"if" / "when" / "else" condition on line 179:

179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1')

	Evaluated to	Count	Threshold
Bin	True	124	1
Bin	False	3998	1

"if" / "when" / "else" condition on line 183:

183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1')

	Evaluated to	Count	Threshold
Bin	True	124	1
Bin	False	3998	1

"if" / "when" / "else" condition on line 229:

229: if (tx_ctr_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	1742422	1
Bin	False	163576110	1

"if" / "when" / "else" condition on line 231:

231: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	81786241	1
Bin	False	81789869	1

"if" / "when" / "else" condition on line 232:

232: if (tran_valid_q = '1') then

	Evaluated to	Count	Threshold
Bin	True	3820	1
Bin	False	81782421	1

"if" / "when" / "else" condition on line 243:

243: if (rx_ctr_rst_n_q_scan = '0') then

	Evaluated to	Count	Threshold
Bin	True	1742422	1
Bin	False	163576110	1

"if" / "when" / "else" condition on line 245:

245: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	81786241	1
Bin	False	81789869	1

"if" / "when" / "else" condition on line 246:

246: if (rec_valid_q = '1') then

	Evaluated to	Count	Threshold
Bin	True	11502	1
Bin	False	81774739	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REC_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_RXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_COMMAND_TXFCRST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	101	1
Bin	(31)	1	0	761	1
Bin	(30)	0	1	106	1
Bin	(30)	1	0	766	1
Bin	(29)	0	1	110	1
Bin	(29)	1	0	770	1
Bin	(28)	0	1	98	1
Bin	(28)	1	0	758	1
Bin	(27)	0	1	105	1
Bin	(27)	1	0	765	1
Bin	(26)	0	1	101	1
Bin	(26)	1	0	761	1
Bin	(25)	0	1	99	1
Bin	(25)	1	0	759	1
Bin	(24)	0	1	97	1
Bin	(24)	1	0	757	1
Bin	(23)	0	1	102	1
Bin	(23)	1	0	762	1
Bin	(22)	0	1	100	1
Bin	(22)	1	0	760	1
Bin	(21)	0	1	105	1
Bin	(21)	1	0	765	1
Bin	(20)	0	1	108	1
Bin	(20)	1	0	768	1
Bin	(19)	0	1	97	1
Bin	(19)	1	0	757	1
Bin	(18)	0	1	98	1
Bin	(18)	1	0	758	1
Bin	(17)	0	1	105	1
Bin	(17)	1	0	765	1
Bin	(16)	0	1	111	1
Bin	(16)	1	0	771	1
Bin	(15)	0	1	102	1
Bin	(15)	1	0	762	1
Bin	(14)	0	1	105	1
Bin	(14)	1	0	765	1
Bin	(13)	0	1	91	1
Bin	(13)	1	0	751	1
Bin	(12)	0	1	99	1
Bin	(12)	1	0	759	1
Bin	(11)	0	1	98	1
Bin	(11)	1	0	758	1
Bin	(10)	0	1	96	1
Bin	(10)	1	0	756	1
Bin	(9)	0	1	106	1
Bin	(9)	1	0	766	1
Bin	(8)	0	1	104	1
Bin	(8)	1	0	764	1
Bin	(7)	0	1	103	1
Bin	(7)	1	0	763	1
Bin	(6)	0	1	108	1
Bin	(6)	1	0	768	1
Bin	(5)	0	1	109	1
Bin	(5)	1	0	769	1
Bin	(4)	0	1	152	1
Bin	(4)	1	0	812	1
Bin	(3)	0	1	258	1
Bin	(3)	1	0	918	1
Bin	(2)	0	1	619	1
Bin	(2)	1	0	1279	1
Bin	(1)	0	1	1052	1
Bin	(1)	1	0	1712	1
Bin	(0)	0	1	2203	1
Bin	(0)	1	0	2863	1

Port:

RX_FRAME_CTR

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	711	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	715	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	709	1
Bin	(28)	0	1	50	1
Bin	(28)	1	0	707	1
Bin	(27)	0	1	53	1
Bin	(27)	1	0	711	1
Bin	(26)	0	1	49	1
Bin	(26)	1	0	709	1
Bin	(25)	0	1	49	1
Bin	(25)	1	0	706	1
Bin	(24)	0	1	57	1
Bin	(24)	1	0	715	1
Bin	(23)	0	1	49	1
Bin	(23)	1	0	709	1
Bin	(22)	0	1	49	1
Bin	(22)	1	0	709	1
Bin	(21)	0	1	54	1
Bin	(21)	1	0	712	1
Bin	(20)	0	1	57	1
Bin	(20)	1	0	715	1
Bin	(19)	0	1	53	1
Bin	(19)	1	0	710	1
Bin	(18)	0	1	53	1
Bin	(18)	1	0	711	1
Bin	(17)	0	1	55	1
Bin	(17)	1	0	713	1
Bin	(16)	0	1	54	1
Bin	(16)	1	0	712	1
Bin	(15)	0	1	54	1
Bin	(15)	1	0	710	1
Bin	(14)	0	1	47	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	57	1
Bin	(13)	1	0	715	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	719	1
Bin	(11)	0	1	50	1
Bin	(11)	1	0	707	1
Bin	(10)	0	1	54	1
Bin	(10)	1	0	711	1
Bin	(9)	0	1	53	1
Bin	(9)	1	0	710	1
Bin	(8)	0	1	66	1
Bin	(8)	1	0	724	1
Bin	(7)	0	1	87	1
Bin	(7)	1	0	745	1
Bin	(6)	0	1	113	1
Bin	(6)	1	0	771	1
Bin	(5)	0	1	215	1
Bin	(5)	1	0	873	1
Bin	(4)	0	1	353	1
Bin	(4)	1	0	1012	1
Bin	(3)	0	1	747	1
Bin	(3)	1	0	1404	1
Bin	(2)	0	1	1493	1
Bin	(2)	1	0	2151	1
Bin	(1)	0	1	2963	1
Bin	(1)	1	0	3620	1
Bin	(0)	0	1	5921	1
Bin	(0)	1	0	6580	1

Signal:

TX_FRAME_CTR_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	101	1
Bin	(31)	1	0	761	1
Bin	(30)	0	1	106	1
Bin	(30)	1	0	766	1
Bin	(29)	0	1	110	1
Bin	(29)	1	0	770	1
Bin	(28)	0	1	98	1
Bin	(28)	1	0	758	1
Bin	(27)	0	1	105	1
Bin	(27)	1	0	765	1
Bin	(26)	0	1	101	1
Bin	(26)	1	0	761	1
Bin	(25)	0	1	99	1
Bin	(25)	1	0	759	1
Bin	(24)	0	1	97	1
Bin	(24)	1	0	757	1
Bin	(23)	0	1	102	1
Bin	(23)	1	0	762	1
Bin	(22)	0	1	100	1
Bin	(22)	1	0	760	1
Bin	(21)	0	1	105	1
Bin	(21)	1	0	765	1
Bin	(20)	0	1	108	1
Bin	(20)	1	0	768	1
Bin	(19)	0	1	97	1
Bin	(19)	1	0	757	1
Bin	(18)	0	1	98	1
Bin	(18)	1	0	758	1
Bin	(17)	0	1	105	1
Bin	(17)	1	0	765	1
Bin	(16)	0	1	111	1
Bin	(16)	1	0	771	1
Bin	(15)	0	1	102	1
Bin	(15)	1	0	762	1
Bin	(14)	0	1	105	1
Bin	(14)	1	0	765	1
Bin	(13)	0	1	91	1
Bin	(13)	1	0	751	1
Bin	(12)	0	1	99	1
Bin	(12)	1	0	759	1
Bin	(11)	0	1	98	1
Bin	(11)	1	0	758	1
Bin	(10)	0	1	96	1
Bin	(10)	1	0	756	1
Bin	(9)	0	1	106	1
Bin	(9)	1	0	766	1
Bin	(8)	0	1	104	1
Bin	(8)	1	0	764	1
Bin	(7)	0	1	103	1
Bin	(7)	1	0	763	1
Bin	(6)	0	1	108	1
Bin	(6)	1	0	768	1
Bin	(5)	0	1	109	1
Bin	(5)	1	0	769	1
Bin	(4)	0	1	152	1
Bin	(4)	1	0	812	1
Bin	(3)	0	1	258	1
Bin	(3)	1	0	918	1
Bin	(2)	0	1	619	1
Bin	(2)	1	0	1279	1
Bin	(1)	0	1	1052	1
Bin	(1)	1	0	1712	1
Bin	(0)	0	1	2203	1
Bin	(0)	1	0	2863	1

Signal:

RX_FRAME_CTR_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	711	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	715	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	709	1
Bin	(28)	0	1	50	1
Bin	(28)	1	0	707	1
Bin	(27)	0	1	53	1
Bin	(27)	1	0	711	1
Bin	(26)	0	1	49	1
Bin	(26)	1	0	709	1
Bin	(25)	0	1	49	1
Bin	(25)	1	0	706	1
Bin	(24)	0	1	57	1
Bin	(24)	1	0	715	1
Bin	(23)	0	1	49	1
Bin	(23)	1	0	709	1
Bin	(22)	0	1	49	1
Bin	(22)	1	0	709	1
Bin	(21)	0	1	54	1
Bin	(21)	1	0	712	1
Bin	(20)	0	1	57	1
Bin	(20)	1	0	715	1
Bin	(19)	0	1	53	1
Bin	(19)	1	0	710	1
Bin	(18)	0	1	53	1
Bin	(18)	1	0	711	1
Bin	(17)	0	1	55	1
Bin	(17)	1	0	713	1
Bin	(16)	0	1	54	1
Bin	(16)	1	0	712	1
Bin	(15)	0	1	54	1
Bin	(15)	1	0	710	1
Bin	(14)	0	1	47	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	57	1
Bin	(13)	1	0	715	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	719	1
Bin	(11)	0	1	50	1
Bin	(11)	1	0	707	1
Bin	(10)	0	1	54	1
Bin	(10)	1	0	711	1
Bin	(9)	0	1	53	1
Bin	(9)	1	0	710	1
Bin	(8)	0	1	66	1
Bin	(8)	1	0	724	1
Bin	(7)	0	1	87	1
Bin	(7)	1	0	745	1
Bin	(6)	0	1	113	1
Bin	(6)	1	0	771	1
Bin	(5)	0	1	215	1
Bin	(5)	1	0	873	1
Bin	(4)	0	1	353	1
Bin	(4)	1	0	1012	1
Bin	(3)	0	1	747	1
Bin	(3)	1	0	1404	1
Bin	(2)	0	1	1493	1
Bin	(2)	1	0	2151	1
Bin	(1)	0	1	2963	1
Bin	(1)	1	0	3620	1
Bin	(0)	0	1	5921	1
Bin	(0)	1	0	6580	1

Signal:

SEL_VALUE

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	711	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	715	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	709	1
Bin	(28)	0	1	50	1
Bin	(28)	1	0	707	1
Bin	(27)	0	1	53	1
Bin	(27)	1	0	711	1
Bin	(26)	0	1	49	1
Bin	(26)	1	0	709	1
Bin	(25)	0	1	49	1
Bin	(25)	1	0	706	1
Bin	(24)	0	1	57	1
Bin	(24)	1	0	715	1
Bin	(23)	0	1	49	1
Bin	(23)	1	0	709	1
Bin	(22)	0	1	49	1
Bin	(22)	1	0	709	1
Bin	(21)	0	1	54	1
Bin	(21)	1	0	712	1
Bin	(20)	0	1	57	1
Bin	(20)	1	0	715	1
Bin	(19)	0	1	53	1
Bin	(19)	1	0	710	1
Bin	(18)	0	1	53	1
Bin	(18)	1	0	711	1
Bin	(17)	0	1	55	1
Bin	(17)	1	0	713	1
Bin	(16)	0	1	54	1
Bin	(16)	1	0	712	1
Bin	(15)	0	1	54	1
Bin	(15)	1	0	710	1
Bin	(14)	0	1	47	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	57	1
Bin	(13)	1	0	715	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	719	1
Bin	(11)	0	1	50	1
Bin	(11)	1	0	707	1
Bin	(10)	0	1	54	1
Bin	(10)	1	0	711	1
Bin	(9)	0	1	53	1
Bin	(9)	1	0	710	1
Bin	(8)	0	1	130	1
Bin	(8)	1	0	788	1
Bin	(7)	0	1	242	1
Bin	(7)	1	0	900	1
Bin	(6)	0	1	463	1
Bin	(6)	1	0	1121	1
Bin	(5)	0	1	653	1
Bin	(5)	1	0	1311	1
Bin	(4)	0	1	958	1
Bin	(4)	1	0	1617	1
Bin	(3)	0	1	1595	1
Bin	(3)	1	0	2252	1
Bin	(2)	0	1	2621	1
Bin	(2)	1	0	3279	1
Bin	(1)	0	1	4556	1
Bin	(1)	1	0	5213	1
Bin	(0)	0	1	7843	1
Bin	(0)	1	0	8502	1

Signal:

INC_VALUE

	Element	From	To	Count	Threshold
Bin	(31)	0	1	53	1
Bin	(31)	1	0	711	1
Bin	(30)	0	1	56	1
Bin	(30)	1	0	715	1
Bin	(29)	0	1	51	1
Bin	(29)	1	0	709	1
Bin	(28)	0	1	50	1
Bin	(28)	1	0	707	1
Bin	(27)	0	1	53	1
Bin	(27)	1	0	711	1
Bin	(26)	0	1	49	1
Bin	(26)	1	0	709	1
Bin	(25)	0	1	49	1
Bin	(25)	1	0	706	1
Bin	(24)	0	1	57	1
Bin	(24)	1	0	715	1
Bin	(23)	0	1	49	1
Bin	(23)	1	0	709	1
Bin	(22)	0	1	49	1
Bin	(22)	1	0	709	1
Bin	(21)	0	1	54	1
Bin	(21)	1	0	712	1
Bin	(20)	0	1	57	1
Bin	(20)	1	0	715	1
Bin	(19)	0	1	53	1
Bin	(19)	1	0	710	1
Bin	(18)	0	1	53	1
Bin	(18)	1	0	711	1
Bin	(17)	0	1	55	1
Bin	(17)	1	0	713	1
Bin	(16)	0	1	54	1
Bin	(16)	1	0	712	1
Bin	(15)	0	1	54	1
Bin	(15)	1	0	710	1
Bin	(14)	0	1	47	1
Bin	(14)	1	0	706	1
Bin	(13)	0	1	57	1
Bin	(13)	1	0	715	1
Bin	(12)	0	1	61	1
Bin	(12)	1	0	719	1
Bin	(11)	0	1	50	1
Bin	(11)	1	0	707	1
Bin	(10)	0	1	54	1
Bin	(10)	1	0	711	1
Bin	(9)	0	1	53	1
Bin	(9)	1	0	710	1
Bin	(8)	0	1	131	1
Bin	(8)	1	0	789	1
Bin	(7)	0	1	245	1
Bin	(7)	1	0	903	1
Bin	(6)	0	1	463	1
Bin	(6)	1	0	1121	1
Bin	(5)	0	1	662	1
Bin	(5)	1	0	1320	1
Bin	(4)	0	1	983	1
Bin	(4)	1	0	1641	1
Bin	(3)	0	1	1647	1
Bin	(3)	1	0	2305	1
Bin	(2)	0	1	2926	1
Bin	(2)	1	0	3585	1
Bin	(1)	0	1	5027	1
Bin	(1)	1	0	5685	1
Bin	(0)	0	1	8502	1
Bin	(0)	1	0	7843	1

Signal:

TX_CTR_RST_N_D

	From	To	Count	Threshold
Bin	0	1	784	1
Bin	1	0	124	1

Signal:

TX_CTR_RST_N_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	2968	1
Bin	1	0	2967	1

Signal:

RX_CTR_RST_N_D

	From	To	Count	Threshold
Bin	0	1	784	1
Bin	1	0	124	1

Signal:

RX_CTR_RST_N_Q_SCAN

	From	To	Count	Threshold
Bin	0	1	2968	1
Bin	1	0	2967	1

Signal:

TRAN_VALID_Q

	From	To	Count	Threshold
Bin	0	1	3820	1
Bin	1	0	4480	1

Signal:

REC_VALID_Q

	From	To	Count	Threshold
Bin	0	1	11502	1
Bin	1	0	12162	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_core.vhd

Details:

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Signal assignment statement on line 157:

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Signal assignment statement on line 165:

Signal assignment statement on line 166:

If statement on lines 169 to 171:

Signal assignment statement on line 169:

Signal assignment statement on line 171:

Signal assignment statement on line 174:

If statement on lines 179 to 181:

Signal assignment statement on line 179:

Signal assignment statement on line 181:

If statement on lines 183 to 185:

Signal assignment statement on line 183:

Signal assignment statement on line 185:

If statement on lines 229 to 235:

Signal assignment statement on line 230:

If statement on lines 232 to 234:

Signal assignment statement on line 233:

If statement on lines 243 to 249:

Signal assignment statement on line 244:

If statement on lines 246 to 248:

Signal assignment statement on line 247:

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Covered branches:

"if" / "when" / "else" condition on line 156:

"if" / "when" / "else" condition on line 159:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on line 183:

"if" / "when" / "else" condition on line 229:

"if" / "when" / "else" condition on line 231:

"if" / "when" / "else" condition on line 232:

"if" / "when" / "else" condition on line 243:

"if" / "when" / "else" condition on line 245:

"if" / "when" / "else" condition on line 246:

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Port:

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"=" expression on line 156:

"=" expression on line 169:

"=" expression on line 179:

"=" expression on line 183:

"=" expression on line 229:

"=" expression on line 232:

"=" expression on line 243:

"=" expression on line 246: