Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| TX_CTR_REG_RST_INST |
100.0 % (6/6) |
100.0 % (6/6) |
100.0 % (28/28) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (42/42) |
| RX_CTR_REG_RST_INST |
100.0 % (6/6) |
100.0 % (6/6) |
100.0 % (28/28) |
100.0 % (2/2) |
N.A. |
N.A. |
100.0 % (42/42) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
156: if (res_n = '0') then
157: tran_valid_q <= '0';
...
161: rec_valid_q <= rec_valid;
162: end if; Count: 162324562
Threshold: 1
Signal assignment statement:
157: tran_valid_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
158: rec_valid_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
160: tran_valid_q <= tran_valid; Count: 80292006
Threshold: 1
Signal assignment statement:
161: rec_valid_q <= rec_valid; Count: 80292006
Threshold: 1
If statement:
169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1')
170: else
171: unsigned(rx_frame_ctr_i); Count: 22601
Threshold: 1
Signal assignment statement:
169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1') Count: 3808
Threshold: 1
Signal assignment statement:
171: unsigned(rx_frame_ctr_i); Count: 18793
Threshold: 1
Signal assignment statement:
174: inc_value <= sel_value + 1; Count: 19941
Threshold: 1
If statement:
179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1')
180: else
181: '1'; Count: 4120
Threshold: 1
Signal assignment statement:
179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1') Count: 124
Threshold: 1
Signal assignment statement:
181: '1'; Count: 3996
Threshold: 1
If statement:
183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1')
184: else
185: '1'; Count: 4120
Threshold: 1
Signal assignment statement:
183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1') Count: 124
Threshold: 1
Signal assignment statement:
185: '1'; Count: 3996
Threshold: 1
If statement:
229: if (tx_ctr_rst_n_q_scan = '0') then
230: tx_frame_ctr_i <= (others => '0');
...
234: end if;
235: end if; Count: 162324810
Threshold: 1
Signal assignment statement:
230: tx_frame_ctr_i <= (others => '0'); Count: 1741786
Threshold: 1
If statement:
232: if (tran_valid_q = '1') then
233: tx_frame_ctr_i <= std_logic_vector(inc_value);
234: end if; Count: 80289698
Threshold: 1
Signal assignment statement:
233: tx_frame_ctr_i <= std_logic_vector(inc_value); Count: 3808
Threshold: 1
If statement:
243: if (rx_ctr_rst_n_q_scan = '0') then
244: rx_frame_ctr_i <= (others => '0');
...
248: end if;
249: end if; Count: 162324810
Threshold: 1
Signal assignment statement:
244: rx_frame_ctr_i <= (others => '0'); Count: 1741786
Threshold: 1
If statement:
246: if (rec_valid_q = '1') then
247: rx_frame_ctr_i <= std_logic_vector(inc_value);
248: end if; Count: 80289698
Threshold: 1
Signal assignment statement:
247: rx_frame_ctr_i <= std_logic_vector(inc_value); Count: 11503
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
156: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1737046 | 1 |
| Bin | False | 160587516 | 1 |
"if" / "when" / "else" condition:
159: elsif rising_edge(clk_sys) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 80292006 | 1 |
| Bin | False | 80295510 | 1 |
"if" / "when" / "else" condition:
169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 3808 | 1 |
| Bin | False | 18793 | 1 |
"if" / "when" / "else" condition:
179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 124 | 1 |
| Bin | False | 3996 | 1 |
"if" / "when" / "else" condition:
183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 124 | 1 |
| Bin | False | 3996 | 1 |
"if" / "when" / "else" condition:
229: if (tx_ctr_rst_n_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1741786 | 1 |
| Bin | False | 160583024 | 1 |
"if" / "when" / "else" condition:
231: elsif rising_edge(clk_sys) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 80289698 | 1 |
| Bin | False | 80293326 | 1 |
"if" / "when" / "else" condition:
232: if (tran_valid_q = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 3808 | 1 |
| Bin | False | 80285890 | 1 |
"if" / "when" / "else" condition:
243: if (rx_ctr_rst_n_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1741786 | 1 |
| Bin | False | 160583024 | 1 |
"if" / "when" / "else" condition:
245: elsif rising_edge(clk_sys) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 80289698 | 1 |
| Bin | False | 80293326 | 1 |
"if" / "when" / "else" condition:
246: if (rec_valid_q = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 11503 | 1 |
| Bin | False | 80278195 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 81158777 | 1 |
| Bin | 1 | 0 | 81159437 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2844 | 1 |
| Bin | 1 | 0 | 2844 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 664 | 1 |
Port:
TRAN_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 4468 | 1 |
Port:
REC_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11503 | 1 |
| Bin | 1 | 0 | 12163 | 1 |
Port:
MR_COMMAND_RXFCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 1998 | 1 |
Port:
MR_COMMAND_TXFCRST | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 1998 | 1 |
Port:
TX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Port:
TX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 768 | 1 |
Port:
TX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Port:
TX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 769 | 1 |
Port:
TX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 751 | 1 |
Port:
TX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 755 | 1 |
Port:
TX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Port:
TX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Port:
TX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 766 | 1 |
Port:
TX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Port:
TX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Port:
TX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Port:
TX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 758 | 1 |
Port:
TX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Port:
TX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Port:
TX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 767 | 1 |
Port:
TX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Port:
TX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 760 | 1 |
Port:
TX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Port:
TX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 760 | 1 |
Port:
TX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 765 | 1 |
Port:
TX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Port:
TX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Port:
TX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 767 | 1 |
Port:
TX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 754 | 1 |
Port:
TX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Port:
TX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 789 | 1 |
Port:
TX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 812 | 1 |
Port:
TX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 923 | 1 |
Port:
TX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593 | 1 |
| Bin | 1 | 0 | 1253 | 1 |
Port:
TX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1072 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
Port:
TX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2211 | 1 |
| Bin | 1 | 0 | 2871 | 1 |
Port:
RX_FRAME_CTR(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Port:
RX_FRAME_CTR(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Port:
RX_FRAME_CTR(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Port:
RX_FRAME_CTR(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Port:
RX_FRAME_CTR(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Port:
RX_FRAME_CTR(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Port:
RX_FRAME_CTR(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 714 | 1 |
Port:
RX_FRAME_CTR(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Port:
RX_FRAME_CTR(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 715 | 1 |
Port:
RX_FRAME_CTR(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Port:
RX_FRAME_CTR(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Port:
RX_FRAME_CTR(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Port:
RX_FRAME_CTR(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Port:
RX_FRAME_CTR(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Port:
RX_FRAME_CTR(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Port:
RX_FRAME_CTR(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 708 | 1 |
Port:
RX_FRAME_CTR(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Port:
RX_FRAME_CTR(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 716 | 1 |
Port:
RX_FRAME_CTR(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Port:
RX_FRAME_CTR(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Port:
RX_FRAME_CTR(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 713 | 1 |
Port:
RX_FRAME_CTR(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 717 | 1 |
Port:
RX_FRAME_CTR(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Port:
RX_FRAME_CTR(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 721 | 1 |
Port:
RX_FRAME_CTR(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 736 | 1 |
Port:
RX_FRAME_CTR(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Port:
RX_FRAME_CTR(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 222 | 1 |
| Bin | 1 | 0 | 880 | 1 |
Port:
RX_FRAME_CTR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 355 | 1 |
| Bin | 1 | 0 | 1014 | 1 |
Port:
RX_FRAME_CTR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 746 | 1 |
| Bin | 1 | 0 | 1404 | 1 |
Port:
RX_FRAME_CTR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1495 | 1 |
| Bin | 1 | 0 | 2153 | 1 |
Port:
RX_FRAME_CTR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 3617 | 1 |
Port:
RX_FRAME_CTR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5919 | 1 |
| Bin | 1 | 0 | 6578 | 1 |
Signal:
TX_FRAME_CTR_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Signal:
TX_FRAME_CTR_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 768 | 1 |
Signal:
TX_FRAME_CTR_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Signal:
TX_FRAME_CTR_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109 | 1 |
| Bin | 1 | 0 | 769 | 1 |
Signal:
TX_FRAME_CTR_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 751 | 1 |
Signal:
TX_FRAME_CTR_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 755 | 1 |
Signal:
TX_FRAME_CTR_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Signal:
TX_FRAME_CTR_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Signal:
TX_FRAME_CTR_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 106 | 1 |
| Bin | 1 | 0 | 766 | 1 |
Signal:
TX_FRAME_CTR_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Signal:
TX_FRAME_CTR_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Signal:
TX_FRAME_CTR_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 102 | 1 |
| Bin | 1 | 0 | 762 | 1 |
Signal:
TX_FRAME_CTR_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 98 | 1 |
| Bin | 1 | 0 | 758 | 1 |
Signal:
TX_FRAME_CTR_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Signal:
TX_FRAME_CTR_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Signal:
TX_FRAME_CTR_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 767 | 1 |
Signal:
TX_FRAME_CTR_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Signal:
TX_FRAME_CTR_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 760 | 1 |
Signal:
TX_FRAME_CTR_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 764 | 1 |
Signal:
TX_FRAME_CTR_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100 | 1 |
| Bin | 1 | 0 | 760 | 1 |
Signal:
TX_FRAME_CTR_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 105 | 1 |
| Bin | 1 | 0 | 765 | 1 |
Signal:
TX_FRAME_CTR_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103 | 1 |
| Bin | 1 | 0 | 763 | 1 |
Signal:
TX_FRAME_CTR_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Signal:
TX_FRAME_CTR_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 107 | 1 |
| Bin | 1 | 0 | 767 | 1 |
Signal:
TX_FRAME_CTR_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 94 | 1 |
| Bin | 1 | 0 | 754 | 1 |
Signal:
TX_FRAME_CTR_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 111 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Signal:
TX_FRAME_CTR_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 789 | 1 |
Signal:
TX_FRAME_CTR_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 152 | 1 |
| Bin | 1 | 0 | 812 | 1 |
Signal:
TX_FRAME_CTR_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 923 | 1 |
Signal:
TX_FRAME_CTR_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 593 | 1 |
| Bin | 1 | 0 | 1253 | 1 |
Signal:
TX_FRAME_CTR_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1072 | 1 |
| Bin | 1 | 0 | 1732 | 1 |
Signal:
TX_FRAME_CTR_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2211 | 1 |
| Bin | 1 | 0 | 2871 | 1 |
Signal:
RX_FRAME_CTR_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
RX_FRAME_CTR_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
RX_FRAME_CTR_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
RX_FRAME_CTR_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Signal:
RX_FRAME_CTR_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
RX_FRAME_CTR_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
RX_FRAME_CTR_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 714 | 1 |
Signal:
RX_FRAME_CTR_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
RX_FRAME_CTR_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 715 | 1 |
Signal:
RX_FRAME_CTR_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
RX_FRAME_CTR_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
RX_FRAME_CTR_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
RX_FRAME_CTR_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
RX_FRAME_CTR_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
RX_FRAME_CTR_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
RX_FRAME_CTR_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 708 | 1 |
Signal:
RX_FRAME_CTR_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
RX_FRAME_CTR_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 716 | 1 |
Signal:
RX_FRAME_CTR_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
RX_FRAME_CTR_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
RX_FRAME_CTR_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 713 | 1 |
Signal:
RX_FRAME_CTR_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 717 | 1 |
Signal:
RX_FRAME_CTR_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
RX_FRAME_CTR_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 62 | 1 |
| Bin | 1 | 0 | 721 | 1 |
Signal:
RX_FRAME_CTR_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 77 | 1 |
| Bin | 1 | 0 | 736 | 1 |
Signal:
RX_FRAME_CTR_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 771 | 1 |
Signal:
RX_FRAME_CTR_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 222 | 1 |
| Bin | 1 | 0 | 880 | 1 |
Signal:
RX_FRAME_CTR_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 355 | 1 |
| Bin | 1 | 0 | 1014 | 1 |
Signal:
RX_FRAME_CTR_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 746 | 1 |
| Bin | 1 | 0 | 1404 | 1 |
Signal:
RX_FRAME_CTR_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1495 | 1 |
| Bin | 1 | 0 | 2153 | 1 |
Signal:
RX_FRAME_CTR_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 3617 | 1 |
Signal:
RX_FRAME_CTR_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5919 | 1 |
| Bin | 1 | 0 | 6578 | 1 |
Signal:
SEL_VALUE(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
SEL_VALUE(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
SEL_VALUE(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
SEL_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Signal:
SEL_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
SEL_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
SEL_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 714 | 1 |
Signal:
SEL_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
SEL_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 715 | 1 |
Signal:
SEL_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
SEL_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
SEL_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
SEL_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
SEL_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
SEL_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
SEL_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 708 | 1 |
Signal:
SEL_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
SEL_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 716 | 1 |
Signal:
SEL_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
SEL_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
SEL_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 713 | 1 |
Signal:
SEL_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 60 | 1 |
| Bin | 1 | 0 | 717 | 1 |
Signal:
SEL_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
SEL_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126 | 1 |
| Bin | 1 | 0 | 785 | 1 |
Signal:
SEL_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 229 | 1 |
| Bin | 1 | 0 | 888 | 1 |
Signal:
SEL_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 465 | 1 |
| Bin | 1 | 0 | 1122 | 1 |
Signal:
SEL_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 672 | 1 |
| Bin | 1 | 0 | 1330 | 1 |
Signal:
SEL_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 960 | 1 |
| Bin | 1 | 0 | 1619 | 1 |
Signal:
SEL_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1586 | 1 |
| Bin | 1 | 0 | 2244 | 1 |
Signal:
SEL_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2640 | 1 |
| Bin | 1 | 0 | 3298 | 1 |
Signal:
SEL_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4536 | 1 |
| Bin | 1 | 0 | 5194 | 1 |
Signal:
SEL_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7826 | 1 |
| Bin | 1 | 0 | 8485 | 1 |
Signal:
INC_VALUE(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
INC_VALUE(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
INC_VALUE(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
INC_VALUE(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Signal:
INC_VALUE(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
INC_VALUE(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 54 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
INC_VALUE(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 714 | 1 |
Signal:
INC_VALUE(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
INC_VALUE(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 715 | 1 |
Signal:
INC_VALUE(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53 | 1 |
| Bin | 1 | 0 | 712 | 1 |
Signal:
INC_VALUE(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
INC_VALUE(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52 | 1 |
| Bin | 1 | 0 | 710 | 1 |
Signal:
INC_VALUE(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
INC_VALUE(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 48 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
INC_VALUE(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 711 | 1 |
Signal:
INC_VALUE(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 708 | 1 |
Signal:
INC_VALUE(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49 | 1 |
| Bin | 1 | 0 | 707 | 1 |
Signal:
INC_VALUE(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58 | 1 |
| Bin | 1 | 0 | 716 | 1 |
Signal:
INC_VALUE(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 47 | 1 |
| Bin | 1 | 0 | 705 | 1 |
Signal:
INC_VALUE(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 709 | 1 |
Signal:
INC_VALUE(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56 | 1 |
| Bin | 1 | 0 | 713 | 1 |
Signal:
INC_VALUE(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 59 | 1 |
| Bin | 1 | 0 | 716 | 1 |
Signal:
INC_VALUE(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 55 | 1 |
| Bin | 1 | 0 | 713 | 1 |
Signal:
INC_VALUE(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126 | 1 |
| Bin | 1 | 0 | 785 | 1 |
Signal:
INC_VALUE(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 233 | 1 |
| Bin | 1 | 0 | 892 | 1 |
Signal:
INC_VALUE(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 469 | 1 |
| Bin | 1 | 0 | 1126 | 1 |
Signal:
INC_VALUE(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 679 | 1 |
| Bin | 1 | 0 | 1337 | 1 |
Signal:
INC_VALUE(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 984 | 1 |
| Bin | 1 | 0 | 1643 | 1 |
Signal:
INC_VALUE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 2303 | 1 |
Signal:
INC_VALUE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2936 | 1 |
| Bin | 1 | 0 | 3593 | 1 |
Signal:
INC_VALUE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5031 | 1 |
| Bin | 1 | 0 | 5690 | 1 |
Signal:
INC_VALUE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8485 | 1 |
| Bin | 1 | 0 | 7826 | 1 |
Signal:
TX_CTR_RST_N_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 784 | 1 |
| Bin | 1 | 0 | 124 | 1 |
Signal:
TX_CTR_RST_N_Q_SCAN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2968 | 1 |
| Bin | 1 | 0 | 2968 | 1 |
Signal:
RX_CTR_RST_N_D | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 784 | 1 |
| Bin | 1 | 0 | 124 | 1 |
Signal:
RX_CTR_RST_N_Q_SCAN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2968 | 1 |
| Bin | 1 | 0 | 2968 | 1 |
Signal:
TRAN_VALID_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 4468 | 1 |
Signal:
REC_VALID_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11503 | 1 |
| Bin | 1 | 0 | 12163 | 1 |
Covered expressions:
"=" expression
156: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 160587516 | 1 |
| Bin | True | 1737046 | 1 |
"=" expression
169: sel_value <= unsigned(tx_frame_ctr_i) when (tran_valid_q = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 18793 | 1 |
| Bin | True | 3808 | 1 |
"=" expression
179: tx_ctr_rst_n_d <= '0' when (mr_command_txfcrst = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 3996 | 1 |
| Bin | True | 124 | 1 |
"=" expression
183: rx_ctr_rst_n_d <= '0' when (mr_command_rxfcrst = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 3996 | 1 |
| Bin | True | 124 | 1 |
"=" expression
229: if (tx_ctr_rst_n_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 160583024 | 1 |
| Bin | True | 1741786 | 1 |
"=" expression
232: if (tran_valid_q = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 80285890 | 1 |
| Bin | True | 3808 | 1 |
"=" expression
243: if (rx_ctr_rst_n_q_scan = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 160583024 | 1 |
| Bin | True | 1741786 | 1 |
"=" expression
246: if (rec_valid_q = '1') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 80278195 | 1 |
| Bin | True | 11503 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: