NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
SWAP_BY_GENERIC_TRUE_GEN	100.0 % (1/1)	N.A.	N.A.	N.A.	N.A.	N.A.	100.0 % (1/1)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

SWAP_BY_GENERIC_TRUE_GEN

100.0 % (1/1)

N.A.

100.0 % (1/1)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ENDIAN_SWAPPER_TX_INST	100.0 % (7/7)	N.A.	100.0 % (192/192)	N.A.	N.A.	N.A.	100.0 % (199/199)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ENDIAN_SWAPPER_TX_INST

100.0 % (7/7)

N.A.

100.0 % (192/192)

N.A.

100.0 % (199/199)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

Loop statement on lines 130 to 138:

130:        for i in 0 to G_WORD_SIZE - 1 loop 
131:            l_ind_orig := i * G_GROUP_SIZE; 
...
137:                input(u_ind_orig downto l_ind_orig); 
138:        end loop;

Count: 159545
Threshold: 1

Variable assignment statement on line 131:

131: l_ind_orig := i * G_GROUP_SIZE;
Count: 638180
Threshold: 1

Variable assignment statement on line 132:

132: u_ind_orig := (i + 1) * G_GROUP_SIZE - 1;
Count: 638180
Threshold: 1

Variable assignment statement on line 133:

133: i_inv := G_WORD_SIZE - i - 1;
Count: 638180
Threshold: 1

Variable assignment statement on line 134:

134: l_ind_swap := i_inv * G_GROUP_SIZE;
Count: 638180
Threshold: 1

Variable assignment statement on line 135:

135: u_ind_swap := (i_inv + 1) * G_GROUP_SIZE - 1;
Count: 638180
Threshold: 1

Signal assignment statement on lines 136 to 137:

136:            swapped(u_ind_swap downto l_ind_swap) <= 
137:                input(u_ind_orig downto l_ind_orig);

Count: 638180
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

INPUT

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

OUTPUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	35636	1
Bin	(31)	1	0	37237	1
Bin	(30)	0	1	26492	1
Bin	(30)	1	0	28093	1
Bin	(29)	0	1	19634	1
Bin	(29)	1	0	21235	1
Bin	(28)	0	1	18379	1
Bin	(28)	1	0	19980	1
Bin	(27)	0	1	26281	1
Bin	(27)	1	0	27882	1
Bin	(26)	0	1	27751	1
Bin	(26)	1	0	29352	1
Bin	(25)	0	1	29032	1
Bin	(25)	1	0	30633	1
Bin	(24)	0	1	36401	1
Bin	(24)	1	0	38002	1
Bin	(23)	0	1	15010	1
Bin	(23)	1	0	16611	1
Bin	(22)	0	1	15577	1
Bin	(22)	1	0	17178	1
Bin	(21)	0	1	15548	1
Bin	(21)	1	0	17149	1
Bin	(20)	0	1	15770	1
Bin	(20)	1	0	17371	1
Bin	(19)	0	1	16048	1
Bin	(19)	1	0	17649	1
Bin	(18)	0	1	17948	1
Bin	(18)	1	0	19549	1
Bin	(17)	0	1	25142	1
Bin	(17)	1	0	26743	1
Bin	(16)	0	1	16245	1
Bin	(16)	1	0	17846	1
Bin	(15)	0	1	22559	1
Bin	(15)	1	0	24160	1
Bin	(14)	0	1	26443	1
Bin	(14)	1	0	28044	1
Bin	(13)	0	1	22115	1
Bin	(13)	1	0	23716	1
Bin	(12)	0	1	26193	1
Bin	(12)	1	0	27794	1
Bin	(11)	0	1	23117	1
Bin	(11)	1	0	24718	1
Bin	(10)	0	1	26236	1
Bin	(10)	1	0	27837	1
Bin	(9)	0	1	15043	1
Bin	(9)	1	0	16644	1
Bin	(8)	0	1	15226	1
Bin	(8)	1	0	16827	1
Bin	(7)	0	1	8376	1
Bin	(7)	1	0	9977	1
Bin	(6)	0	1	8561	1
Bin	(6)	1	0	10162	1
Bin	(5)	0	1	8142	1
Bin	(5)	1	0	9743	1
Bin	(4)	0	1	26007	1
Bin	(4)	1	0	27608	1
Bin	(3)	0	1	21693	1
Bin	(3)	1	0	23294	1
Bin	(2)	0	1	25772	1
Bin	(2)	1	0	27373	1
Bin	(1)	0	1	21893	1
Bin	(1)	1	0	23494	1
Bin	(0)	0	1	26638	1
Bin	(0)	1	0	28239	1

Signal:

SWAPPED

	Element	From	To	Count	Threshold
Bin	(31)	0	1	35717	1
Bin	(31)	1	0	46484	1
Bin	(30)	0	1	26569	1
Bin	(30)	1	0	33483	1
Bin	(29)	0	1	19646	1
Bin	(29)	1	0	27743	1
Bin	(28)	0	1	18407	1
Bin	(28)	1	0	24035	1
Bin	(27)	0	1	26307	1
Bin	(27)	1	0	34362	1
Bin	(26)	0	1	27803	1
Bin	(26)	1	0	36175	1
Bin	(25)	0	1	29100	1
Bin	(25)	1	0	37258	1
Bin	(24)	0	1	36483	1
Bin	(24)	1	0	46185	1
Bin	(23)	0	1	16678	1
Bin	(23)	1	0	56782	1
Bin	(22)	0	1	17472	1
Bin	(22)	1	0	61248	1
Bin	(21)	0	1	17234	1
Bin	(21)	1	0	59689	1
Bin	(20)	0	1	17564	1
Bin	(20)	1	0	58763	1
Bin	(19)	0	1	17587	1
Bin	(19)	1	0	58727	1
Bin	(18)	0	1	19748	1
Bin	(18)	1	0	62147	1
Bin	(17)	0	1	26734	1
Bin	(17)	1	0	73337	1
Bin	(16)	0	1	18138	1
Bin	(16)	1	0	61115	1
Bin	(15)	0	1	24098	1
Bin	(15)	1	0	58996	1
Bin	(14)	0	1	26608	1
Bin	(14)	1	0	63798	1
Bin	(13)	0	1	23649	1
Bin	(13)	1	0	57226	1
Bin	(12)	0	1	26299	1
Bin	(12)	1	0	63923	1
Bin	(11)	0	1	24695	1
Bin	(11)	1	0	59145	1
Bin	(10)	0	1	26467	1
Bin	(10)	1	0	63066	1
Bin	(9)	0	1	16571	1
Bin	(9)	1	0	36075	1
Bin	(8)	0	1	17070	1
Bin	(8)	1	0	37013	1
Bin	(7)	0	1	10042	1
Bin	(7)	1	0	25683	1
Bin	(6)	0	1	10570	1
Bin	(6)	1	0	25286	1
Bin	(5)	0	1	9820	1
Bin	(5)	1	0	25818	1
Bin	(4)	0	1	26261	1
Bin	(4)	1	0	65140	1
Bin	(3)	0	1	23244	1
Bin	(3)	1	0	58162	1
Bin	(2)	0	1	26085	1
Bin	(2)	1	0	65783	1
Bin	(1)	0	1	23442	1
Bin	(1)	1	0	59729	1
Bin	(0)	0	1	26868	1
Bin	(0)	1	0	67985	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ENDIAN_SWAPPER_TX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Loop statement on lines 130 to 138:

Variable assignment statement on line 131:

Variable assignment statement on line 132:

Variable assignment statement on line 133:

Variable assignment statement on line 134:

Variable assignment statement on line 135:

Signal assignment statement on lines 136 to 137:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Port:

Covered toggles:

Port:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: