NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
SWAP_BY_GENERIC_TRUE_GEN	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.	N.A.

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ENDIAN_SWAPPER_TX_INST	100.0 % (7/7)	N.A.	100.0 % (192/192)	N.A.	N.A.	N.A.	100.0 % (199/199)

Uncovered statements:

Excluded statements:

Covered statements:

Loop statement:

130:        for i in 0 to G_WORD_SIZE - 1 loop 
131:            l_ind_orig := i * G_GROUP_SIZE; 
...
137:                input(u_ind_orig downto l_ind_orig); 
138:        end loop;

Count: 157308
Threshold: 1

Variable assignment statement:

131: l_ind_orig := i * G_GROUP_SIZE;
Count: 629232
Threshold: 1

Variable assignment statement:

132: u_ind_orig := (i + 1) * G_GROUP_SIZE - 1;
Count: 629232
Threshold: 1

Variable assignment statement:

133: i_inv := G_WORD_SIZE - i - 1;
Count: 629232
Threshold: 1

Variable assignment statement:

134: l_ind_swap := i_inv * G_GROUP_SIZE;
Count: 629232
Threshold: 1

Variable assignment statement:

135: u_ind_swap := (i_inv + 1) * G_GROUP_SIZE - 1;
Count: 629232
Threshold: 1

Signal assignment statement:

136:            swapped(u_ind_swap downto l_ind_swap) <= 
137:                input(u_ind_orig downto l_ind_orig);

Count: 629232
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

INPUT(31)

	From	To	Count	Threshold
Bin	0	1	8251	1
Bin	1	0	9851	1

Port:

INPUT(30)

	From	To	Count	Threshold
Bin	0	1	8670	1
Bin	1	0	10270	1

Port:

INPUT(29)

	From	To	Count	Threshold
Bin	0	1	8250	1
Bin	1	0	9850	1

Port:

INPUT(28)

	From	To	Count	Threshold
Bin	0	1	26016	1
Bin	1	0	27616	1

Port:

INPUT(27)

	From	To	Count	Threshold
Bin	0	1	20559	1
Bin	1	0	22159	1

Port:

INPUT(26)

	From	To	Count	Threshold
Bin	0	1	26228	1
Bin	1	0	27828	1

Port:

INPUT(25)

	From	To	Count	Threshold
Bin	0	1	21530	1
Bin	1	0	23130	1

Port:

INPUT(24)

	From	To	Count	Threshold
Bin	0	1	25986	1
Bin	1	0	27586	1

Port:

INPUT(23)

	From	To	Count	Threshold
Bin	0	1	22777	1
Bin	1	0	24377	1

Port:

INPUT(22)

	From	To	Count	Threshold
Bin	0	1	25704	1
Bin	1	0	27304	1

Port:

INPUT(21)

	From	To	Count	Threshold
Bin	0	1	22032	1
Bin	1	0	23632	1

Port:

INPUT(20)

	From	To	Count	Threshold
Bin	0	1	25833	1
Bin	1	0	27433	1

Port:

INPUT(19)

	From	To	Count	Threshold
Bin	0	1	22441	1
Bin	1	0	24041	1

Port:

INPUT(18)

	From	To	Count	Threshold
Bin	0	1	26355	1
Bin	1	0	27955	1

Port:

INPUT(17)

	From	To	Count	Threshold
Bin	0	1	14208	1
Bin	1	0	15808	1

Port:

INPUT(16)

	From	To	Count	Threshold
Bin	0	1	15135	1
Bin	1	0	16735	1

Port:

INPUT(15)

	From	To	Count	Threshold
Bin	0	1	14400	1
Bin	1	0	16000	1

Port:

INPUT(14)

	From	To	Count	Threshold
Bin	0	1	15059	1
Bin	1	0	16659	1

Port:

INPUT(13)

	From	To	Count	Threshold
Bin	0	1	14849	1
Bin	1	0	16449	1

Port:

INPUT(12)

	From	To	Count	Threshold
Bin	0	1	15821	1
Bin	1	0	17421	1

Port:

INPUT(11)

	From	To	Count	Threshold
Bin	0	1	14688	1
Bin	1	0	16288	1

Port:

INPUT(10)

	From	To	Count	Threshold
Bin	0	1	15846	1
Bin	1	0	17446	1

Port:

INPUT(9)

	From	To	Count	Threshold
Bin	0	1	25928	1
Bin	1	0	27528	1

Port:

INPUT(8)

	From	To	Count	Threshold
Bin	0	1	16627	1
Bin	1	0	18227	1

Port:

INPUT(7)

	From	To	Count	Threshold
Bin	0	1	35438	1
Bin	1	0	37038	1

Port:

INPUT(6)

	From	To	Count	Threshold
Bin	0	1	26739	1
Bin	1	0	28339	1

Port:

INPUT(5)

	From	To	Count	Threshold
Bin	0	1	19032	1
Bin	1	0	20632	1

Port:

INPUT(4)

	From	To	Count	Threshold
Bin	0	1	16938	1
Bin	1	0	18538	1

Port:

INPUT(3)

	From	To	Count	Threshold
Bin	0	1	26470	1
Bin	1	0	28070	1

Port:

INPUT(2)

	From	To	Count	Threshold
Bin	0	1	26680	1
Bin	1	0	28280	1

Port:

INPUT(1)

	From	To	Count	Threshold
Bin	0	1	27552	1
Bin	1	0	29152	1

Port:

INPUT(0)

	From	To	Count	Threshold
Bin	0	1	35377	1
Bin	1	0	36977	1

Port:

OUTPUT(31)

	From	To	Count	Threshold
Bin	0	1	35438	1
Bin	1	0	37038	1

Port:

OUTPUT(30)

	From	To	Count	Threshold
Bin	0	1	26739	1
Bin	1	0	28339	1

Port:

OUTPUT(29)

	From	To	Count	Threshold
Bin	0	1	19032	1
Bin	1	0	20632	1

Port:

OUTPUT(28)

	From	To	Count	Threshold
Bin	0	1	16938	1
Bin	1	0	18538	1

Port:

OUTPUT(27)

	From	To	Count	Threshold
Bin	0	1	26470	1
Bin	1	0	28070	1

Port:

OUTPUT(26)

	From	To	Count	Threshold
Bin	0	1	26680	1
Bin	1	0	28280	1

Port:

OUTPUT(25)

	From	To	Count	Threshold
Bin	0	1	27552	1
Bin	1	0	29152	1

Port:

OUTPUT(24)

	From	To	Count	Threshold
Bin	0	1	35377	1
Bin	1	0	36977	1

Port:

OUTPUT(23)

	From	To	Count	Threshold
Bin	0	1	14400	1
Bin	1	0	16000	1

Port:

OUTPUT(22)

	From	To	Count	Threshold
Bin	0	1	15059	1
Bin	1	0	16659	1

Port:

OUTPUT(21)

	From	To	Count	Threshold
Bin	0	1	14849	1
Bin	1	0	16449	1

Port:

OUTPUT(20)

	From	To	Count	Threshold
Bin	0	1	15821	1
Bin	1	0	17421	1

Port:

OUTPUT(19)

	From	To	Count	Threshold
Bin	0	1	14688	1
Bin	1	0	16288	1

Port:

OUTPUT(18)

	From	To	Count	Threshold
Bin	0	1	15846	1
Bin	1	0	17446	1

Port:

OUTPUT(17)

	From	To	Count	Threshold
Bin	0	1	25928	1
Bin	1	0	27528	1

Port:

OUTPUT(16)

	From	To	Count	Threshold
Bin	0	1	16627	1
Bin	1	0	18227	1

Port:

OUTPUT(15)

	From	To	Count	Threshold
Bin	0	1	22777	1
Bin	1	0	24377	1

Port:

OUTPUT(14)

	From	To	Count	Threshold
Bin	0	1	25704	1
Bin	1	0	27304	1

Port:

OUTPUT(13)

	From	To	Count	Threshold
Bin	0	1	22032	1
Bin	1	0	23632	1

Port:

OUTPUT(12)

	From	To	Count	Threshold
Bin	0	1	25833	1
Bin	1	0	27433	1

Port:

OUTPUT(11)

	From	To	Count	Threshold
Bin	0	1	22441	1
Bin	1	0	24041	1

Port:

OUTPUT(10)

	From	To	Count	Threshold
Bin	0	1	26355	1
Bin	1	0	27955	1

Port:

OUTPUT(9)

	From	To	Count	Threshold
Bin	0	1	14208	1
Bin	1	0	15808	1

Port:

OUTPUT(8)

	From	To	Count	Threshold
Bin	0	1	15135	1
Bin	1	0	16735	1

Port:

OUTPUT(7)

	From	To	Count	Threshold
Bin	0	1	8251	1
Bin	1	0	9851	1

Port:

OUTPUT(6)

	From	To	Count	Threshold
Bin	0	1	8670	1
Bin	1	0	10270	1

Port:

OUTPUT(5)

	From	To	Count	Threshold
Bin	0	1	8250	1
Bin	1	0	9850	1

Port:

OUTPUT(4)

	From	To	Count	Threshold
Bin	0	1	26016	1
Bin	1	0	27616	1

Port:

OUTPUT(3)

	From	To	Count	Threshold
Bin	0	1	20559	1
Bin	1	0	22159	1

Port:

OUTPUT(2)

	From	To	Count	Threshold
Bin	0	1	26228	1
Bin	1	0	27828	1

Port:

OUTPUT(1)

	From	To	Count	Threshold
Bin	0	1	21530	1
Bin	1	0	23130	1

Port:

OUTPUT(0)

	From	To	Count	Threshold
Bin	0	1	25986	1
Bin	1	0	27586	1

Signal:

SWAPPED(31)

	From	To	Count	Threshold
Bin	0	1	35509	1
Bin	1	0	47077	1

Signal:

SWAPPED(30)

	From	To	Count	Threshold
Bin	0	1	26823	1
Bin	1	0	34371	1

Signal:

SWAPPED(29)

	From	To	Count	Threshold
Bin	0	1	19060	1
Bin	1	0	27795	1

Signal:

SWAPPED(28)

	From	To	Count	Threshold
Bin	0	1	16970	1
Bin	1	0	23304	1

Signal:

SWAPPED(27)

	From	To	Count	Threshold
Bin	0	1	26494	1
Bin	1	0	35051	1

Signal:

SWAPPED(26)

	From	To	Count	Threshold
Bin	0	1	26734	1
Bin	1	0	35569	1

Signal:

SWAPPED(25)

	From	To	Count	Threshold
Bin	0	1	27625	1
Bin	1	0	36277	1

Signal:

SWAPPED(24)

	From	To	Count	Threshold
Bin	0	1	35451	1
Bin	1	0	46149	1

Signal:

SWAPPED(23)

	From	To	Count	Threshold
Bin	0	1	16072	1
Bin	1	0	58113	1

Signal:

SWAPPED(22)

	From	To	Count	Threshold
Bin	0	1	16956	1
Bin	1	0	59694	1

Signal:

SWAPPED(21)

	From	To	Count	Threshold
Bin	0	1	16531	1
Bin	1	0	57973	1

Signal:

SWAPPED(20)

	From	To	Count	Threshold
Bin	0	1	17606	1
Bin	1	0	57960	1

Signal:

SWAPPED(19)

	From	To	Count	Threshold
Bin	0	1	16228	1
Bin	1	0	56489	1

Signal:

SWAPPED(18)

	From	To	Count	Threshold
Bin	0	1	17638	1
Bin	1	0	57978	1

Signal:

SWAPPED(17)

	From	To	Count	Threshold
Bin	0	1	27517	1
Bin	1	0	73986	1

Signal:

SWAPPED(16)

	From	To	Count	Threshold
Bin	0	1	18519	1
Bin	1	0	62401	1

Signal:

SWAPPED(15)

	From	To	Count	Threshold
Bin	0	1	24319	1
Bin	1	0	57561	1

Signal:

SWAPPED(14)

	From	To	Count	Threshold
Bin	0	1	25863	1
Bin	1	0	61872	1

Signal:

SWAPPED(13)

	From	To	Count	Threshold
Bin	0	1	23576	1
Bin	1	0	56681	1

Signal:

SWAPPED(12)

	From	To	Count	Threshold
Bin	0	1	25935	1
Bin	1	0	63703	1

Signal:

SWAPPED(11)

	From	To	Count	Threshold
Bin	0	1	23984	1
Bin	1	0	58684	1

Signal:

SWAPPED(10)

	From	To	Count	Threshold
Bin	0	1	26582	1
Bin	1	0	64113	1

Signal:

SWAPPED(9)

	From	To	Count	Threshold
Bin	0	1	15734	1
Bin	1	0	36187	1

Signal:

SWAPPED(8)

	From	To	Count	Threshold
Bin	0	1	16976	1
Bin	1	0	37522	1

Signal:

SWAPPED(7)

	From	To	Count	Threshold
Bin	0	1	9918	1
Bin	1	0	25871	1

Signal:

SWAPPED(6)

	From	To	Count	Threshold
Bin	0	1	10689	1
Bin	1	0	26605	1

Signal:

SWAPPED(5)

	From	To	Count	Threshold
Bin	0	1	9932	1
Bin	1	0	25900	1

Signal:

SWAPPED(4)

	From	To	Count	Threshold
Bin	0	1	26263	1
Bin	1	0	68252	1

Signal:

SWAPPED(3)

	From	To	Count	Threshold
Bin	0	1	22111	1
Bin	1	0	55080	1

Signal:

SWAPPED(2)

	From	To	Count	Threshold
Bin	0	1	26535	1
Bin	1	0	67887	1

Signal:

SWAPPED(1)

	From	To	Count	Threshold
Bin	0	1	23062	1
Bin	1	0	59311	1

Signal:

SWAPPED(0)

	From	To	Count	Threshold
Bin	0	1	26213	1
Bin	1	0	66155	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.ENDIAN_SWAPPER_TX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/endian_swapper.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Loop statement:

Variable assignment statement:

Variable assignment statement:

Variable assignment statement:

Variable assignment statement:

Variable assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

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