Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage:
PSL cover point on line 151:
151: -- psl txtb_set_ready_cov : cover {mr_tx_command_txcr = '1' and mr_tx_command_txbi = '1'};
Count: 7894
Threshold: 1
PSL cover point on line 152:
152: -- psl txtb_set_empty_cov : cover {mr_tx_command_txce = '1' and mr_tx_command_txbi = '1'};
Count: 227
Threshold: 1
PSL cover point on line 153:
153: -- psl txtb_set_abort_cov : cover {mr_tx_command_txca = '1' and mr_tx_command_txbi = '1'};
Count: 497
Threshold: 1
PSL cover point on line 159:
159: -- psl txtb_hw_lock : cover {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1'};
Count: 9652
Threshold: 1
PSL cover point on line 160:
160: -- psl txtb_hw_valid : cover {txtb_hw_cmd.valid = '1' and txtb_hw_cmd_cs = '1'};
Count: 5057
Threshold: 1
PSL cover point on line 161:
161: -- psl txtb_hw_err : cover {txtb_hw_cmd.err = '1' and txtb_hw_cmd_cs = '1'};
Count: 2166
Threshold: 1
PSL cover point on line 162:
162: -- psl txtb_hw_arbl : cover {txtb_hw_cmd.arbl = '1' and txtb_hw_cmd_cs = '1'};
Count: 213
Threshold: 1
PSL cover point on line 163:
163: -- psl txtb_hw_failed : cover {txtb_hw_cmd.failed = '1' and txtb_hw_cmd_cs = '1'};
Count: 2211
Threshold: 1
PSL cover point on lines 169 to 170:
169: -- psl txtb_perr_txt_ready_cov : cover
170: -- {curr_state = s_txt_ready and txtb_parity_error_valid = '1'};
Count: 67
Threshold: 1
PSL cover point on lines 172 to 173:
172: -- psl txtb_perr_txt_tx_prog_cov : cover
173: -- {curr_state = s_txt_tx_prog and txtb_parity_error_valid = '1'};
Count: 41
Threshold: 1
PSL cover point on lines 175 to 176:
175: -- psl txtb_perr_txt_ab_prog_cov : cover
176: -- {curr_state = s_txt_ab_prog and txtb_parity_error_valid = '1'};
Count: 10
Threshold: 1
PSL cover point on lines 183 to 184:
183: -- psl txtb_skip_backup_buffers : cover
184: -- {curr_state = s_txt_ready and buffer_skipped = '1' and abort_applied = '0'};
Count: 72
Threshold: 1
PSL cover point on lines 190 to 192:
190: -- psl txtb_hw_sw_cmd_txt_ready_hazard_cov : cover
191: -- {txtb_hw_cmd.lock = '1' and txtb_hw_cmd_cs = '1' and abort_applied = '1' and
192: -- curr_state = s_txt_ready};
Count: 11
Threshold: 1
PSL cover point on lines 194 to 197:
194: -- psl txtb_hw_sw_cmd_txt_tx_prog_hazard_cov : cover
195: -- {((txtb_hw_cmd_i.valid = '1' or txtb_hw_cmd_i.err = '1' or
196: -- txtb_hw_cmd_i.arbl = '1' or txtb_hw_cmd_i.failed = '1') and
197: -- abort_applied = '1' and curr_state = s_txt_tx_prog)};
Count: 11
Threshold: 1
PSL cover point on lines 203 to 204:
203: -- psl txtb_ready_to_abt_in_progress_cov : cover
204: -- {curr_state = s_txt_ready and next_state = s_txt_ab_prog and txt_fsm_ce = '1'};
Count: 11
Threshold: 1
PSL cover point on lines 206 to 207:
206: -- psl txtb_abt_in_progress_to_parity_error_cov : cover
207: -- {curr_state = s_txt_ab_prog and next_state = s_txt_parity_err and txt_fsm_ce = '1'};
Count: 10
Threshold: 1
PSL cover point on lines 209 to 210:
209: -- psl txtb_tx_in_progress_to_aborted_cov : cover
210: -- {curr_state = s_txt_tx_prog and next_state = s_txt_aborted and txt_fsm_ce = '1'};
Count: 11
Threshold: 1