NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST	100.0 % (19/19)	100.0 % (20/20)	100.0 % (46/46)	100.0 % (6/6)	N.A.	N.A.	100.0 % (91/91)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

114: dlc_int <= to_integer(unsigned(dlc));
Count: 80908
Threshold: 1

If statement:

117:    data_len_8_to_64_integer <= 
118:        12 when (dlc = "1001") else 
...
124:        64 when (dlc = "1111") else 
125:        0;

Count: 80908
Threshold: 1

Signal assignment statement:

118: 12 when (dlc = "1001") else
Count: 763
Threshold: 1

Signal assignment statement:

119: 16 when (dlc = "1010") else
Count: 565
Threshold: 1

Signal assignment statement:

120: 20 when (dlc = "1011") else
Count: 528
Threshold: 1

Signal assignment statement:

121: 24 when (dlc = "1100") else
Count: 919
Threshold: 1

Signal assignment statement:

122: 32 when (dlc = "1101") else
Count: 449
Threshold: 1

Signal assignment statement:

123: 48 when (dlc = "1110") else
Count: 784
Threshold: 1

Signal assignment statement:

124: 64 when (dlc = "1111") else
Count: 13294
Threshold: 1

Signal assignment statement:

125: 0;
Count: 63606
Threshold: 1

If statement:

130:    data_len_can_2_0 <= dlc when (dlc_int <= 8) 
131:                            else 
132:                        "1000";

Count: 158616
Threshold: 1

Signal assignment statement:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)
Count: 124013
Threshold: 1

Signal assignment statement:

132: "1000";
Count: 34603
Threshold: 1

If statement:

137:    data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8) 
138:                                     else 
139:                       std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));

Count: 158616
Threshold: 1

Signal assignment statement:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)
Count: 124013
Threshold: 1

Signal assignment statement:

139: std_logic_vector(to_unsigned(data_len_8_to_64_integer, 7));
Count: 34603
Threshold: 1

If statement:

142:    data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN) 
143:                                            else 
144:                   data_len_can_fd;

Count: 147490
Threshold: 1

Signal assignment statement:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)
Count: 75183
Threshold: 1

Signal assignment statement:

144: data_len_can_fd;
Count: 72307
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

118: 12 when (dlc = "1001") else

	Evaluated to	Count	Threshold
Bin	True	763	1
Bin	False	80145	1

"if" / "when" / "else" condition:

119: 16 when (dlc = "1010") else

	Evaluated to	Count	Threshold
Bin	True	565	1
Bin	False	79580	1

"if" / "when" / "else" condition:

120: 20 when (dlc = "1011") else

	Evaluated to	Count	Threshold
Bin	True	528	1
Bin	False	79052	1

"if" / "when" / "else" condition:

121: 24 when (dlc = "1100") else

	Evaluated to	Count	Threshold
Bin	True	919	1
Bin	False	78133	1

"if" / "when" / "else" condition:

122: 32 when (dlc = "1101") else

	Evaluated to	Count	Threshold
Bin	True	449	1
Bin	False	77684	1

"if" / "when" / "else" condition:

123: 48 when (dlc = "1110") else

	Evaluated to	Count	Threshold
Bin	True	784	1
Bin	False	76900	1

"if" / "when" / "else" condition:

124: 64 when (dlc = "1111") else

	Evaluated to	Count	Threshold
Bin	True	13294	1
Bin	False	63606	1

"if" / "when" / "else" condition:

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	124013	1
Bin	False	34603	1

"if" / "when" / "else" condition:

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	True	124013	1
Bin	False	34603	1

"if" / "when" / "else" condition:

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	True	75183	1
Bin	False	72307	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DLC(3)

	From	To	Count	Threshold
Bin	0	1	20320	1
Bin	1	0	21919	1

Port:

DLC(2)

	From	To	Count	Threshold
Bin	0	1	22531	1
Bin	1	0	24130	1

Port:

DLC(1)

	From	To	Count	Threshold
Bin	0	1	22383	1
Bin	1	0	23980	1

Port:

DLC(0)

	From	To	Count	Threshold
Bin	0	1	26951	1
Bin	1	0	28549	1

Port:

FRAME_TYPE

	From	To	Count	Threshold
Bin	0	1	28440	1
Bin	1	0	30036	1

Port:

DATA_LENGTH(6)

	From	To	Count	Threshold
Bin	0	1	12817	1
Bin	1	0	14417	1

Port:

DATA_LENGTH(5)

	From	To	Count	Threshold
Bin	0	1	977	1
Bin	1	0	2577	1

Port:

DATA_LENGTH(4)

	From	To	Count	Threshold
Bin	0	1	1979	1
Bin	1	0	3579	1

Port:

DATA_LENGTH(3)

	From	To	Count	Threshold
Bin	0	1	34944	1
Bin	1	0	36543	1

Port:

DATA_LENGTH(2)

	From	To	Count	Threshold
Bin	0	1	23537	1
Bin	1	0	25136	1

Port:

DATA_LENGTH(1)

	From	To	Count	Threshold
Bin	0	1	22383	1
Bin	1	0	23981	1

Port:

DATA_LENGTH(0)

	From	To	Count	Threshold
Bin	0	1	26951	1
Bin	1	0	28549	1

Signal:

DATA_LEN_CAN_2_0(3)

	From	To	Count	Threshold
Bin	0	1	20320	1
Bin	1	0	21919	1

Signal:

DATA_LEN_CAN_2_0(2)

	From	To	Count	Threshold
Bin	0	1	22531	1
Bin	1	0	24130	1

Signal:

DATA_LEN_CAN_2_0(1)

	From	To	Count	Threshold
Bin	0	1	22383	1
Bin	1	0	23981	1

Signal:

DATA_LEN_CAN_2_0(0)

	From	To	Count	Threshold
Bin	0	1	26951	1
Bin	1	0	28549	1

Signal:

DATA_LEN_CAN_FD(6)

	From	To	Count	Threshold
Bin	0	1	13294	1
Bin	1	0	14894	1

Signal:

DATA_LEN_CAN_FD(5)

	From	To	Count	Threshold
Bin	0	1	1233	1
Bin	1	0	2833	1

Signal:

DATA_LEN_CAN_FD(4)

	From	To	Count	Threshold
Bin	0	1	2796	1
Bin	1	0	4395	1

Signal:

DATA_LEN_CAN_FD(3)

	From	To	Count	Threshold
Bin	0	1	20320	1
Bin	1	0	21920	1

Signal:

DATA_LEN_CAN_FD(2)

	From	To	Count	Threshold
Bin	0	1	23822	1
Bin	1	0	25421	1

Signal:

DATA_LEN_CAN_FD(1)

	From	To	Count	Threshold
Bin	0	1	22383	1
Bin	1	0	23981	1

Signal:

DATA_LEN_CAN_FD(0)

	From	To	Count	Threshold
Bin	0	1	26951	1
Bin	1	0	28549	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

130: data_len_can_2_0 <= dlc when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	34603	1
Bin	True	124013	1

"<=" expression

137: data_len_can_fd <= ("000" & dlc) when (dlc_int <= 8)

	Evaluated to	Count	Threshold
Bin	False	34603	1
Bin	True	124013	1

"=" expression

142: data_length <= "000" & data_len_can_2_0 when (frame_type = NORMAL_CAN)

	Evaluated to	Count	Threshold
Bin	False	72307	1
Bin	True	75183	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.PROTOCOL_CONTROL_FSM_INST.DLC_DECODER_RX_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dlc_decoder.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"<=" expression

"<=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: