NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST.DFF_HALT_REG	100.0 % (3/3)	100.0 % (4/4)	100.0 % (8/8)	100.0 % (2/2)	N.A.	N.A.	100.0 % (17/17)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST.DFF_HALT_REG

100.0 % (3/3)

100.0 % (4/4)

100.0 % (8/8)

100.0 % (2/2)

N.A.

100.0 % (17/17)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 105 to 109:

105:        if (arst = G_RESET_POLARITY) then 
106:            reg_q <= G_RST_VAL; 
107:        elsif (rising_edge(clk)) then 
108:            reg_q <= reg_d; 
109:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 106:

106: reg_q <= G_RST_VAL;
Count: 2424883
Threshold: 1

Signal assignment statement on line 108:

108: reg_q <= reg_d;
Count: 543791678
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 105:

105: if (arst = G_RESET_POLARITY) then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 107:

107: elsif (rising_edge(clk)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

Uncovered toggles:

Excluded toggles:

Port:

ARST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CLK

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

REG_D

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

REG_Q

	From	To	Count	Threshold
Bin	0	1	315350	1
Bin	1	0	316951	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 105:

arst = G_RESET_POLARITY

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

NVC code coverage report

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BIT_STUFFING_INST.DFF_HALT_REG

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/bit_stuffing.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 105 to 109:

Signal assignment statement on line 106:

Signal assignment statement on line 108:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 105:

"if" / "when" / "else" condition on line 107:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Covered toggles:

Port:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 105:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: