NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.CLK_GATE_TXT_BUFFER_RAM_COMP.G_TECH_ASIC

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.CLK_GATE_TXT_BUFFER_RAM_COMP.G_TECH_ASIC	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (8/8)	N.A.	N.A.	100.0 % (13/13)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

113:            if (clk_in = '0') then 
114:                clk_en_q <= clk_en or scan_enable; 
115:            end if;

Count: 136440372
Threshold: 1

Signal assignment statement:

114: clk_en_q <= clk_en or scan_enable;
Count: 68199278
Threshold: 1

Signal assignment statement:

119: clk_out <= clk_in AND clk_en_q;
Count: 136440867
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

113: if (clk_in = '0') then

	Evaluated to	Count	Threshold
Bin	True	68199278	1
Bin	False	68241094	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

113: if (clk_in = '0') then

	Evaluated to	Count	Threshold
Bin	False	68241094	1
Bin	True	68199278	1

"or" expression

114:                clk_en_q <= clk_en or scan_enable; 
                                <LHS->    <---RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	67552038	1
Bin	'0'	'1'	30	1
Bin	'1'	'0'	647210	1

"and" expression

119:        clk_out <= clk_in AND clk_en_q; 
                       <LHS->     <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	702320	1
Bin	'1'	'0'	67517371	1
Bin	'1'	'1'	647240	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.CLK_GATE_TXT_BUFFER_RAM_COMP.G_TECH_ASIC

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"or" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: