NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 3551
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 3551
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 113632
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 3551
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	339	1
Bin	1	0	494	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	204	1
Bin	1	0	359	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	206	1
Bin	1	0	361	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	621	1
Bin	1	0	771	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	557	1
Bin	1	0	706	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	525	1
Bin	1	0	678	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	544	1
Bin	1	0	694	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	561	1
Bin	1	0	709	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	427	1
Bin	1	0	575	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	604	1
Bin	1	0	755	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	570	1
Bin	1	0	722	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	625	1
Bin	1	0	774	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	661	1
Bin	1	0	810	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	506	1
Bin	1	0	655	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	313	1
Bin	1	0	467	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	329	1
Bin	1	0	484	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	342	1
Bin	1	0	495	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	520	1
Bin	1	0	674	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	389	1
Bin	1	0	542	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	481	1
Bin	1	0	634	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	345	1
Bin	1	0	498	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	442	1
Bin	1	0	594	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	821	1
Bin	1	0	971	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	672	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	922	1
Bin	1	0	1066	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	600	1
Bin	1	0	746	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	568	1
Bin	1	0	719	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	291	1
Bin	1	0	444	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	435	1
Bin	1	0	585	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	782	1
Bin	1	0	932	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	608	1
Bin	1	0	754	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	452	1
Bin	1	0	598	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	848	1
Bin	1	0	700	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	26302	1
Bin	'0'	'1'	8959	1
Bin	'1'	'0'	62758	1
Bin	'1'	'1'	10333	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(7).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: