NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_DEST_TST_ADDR_SLICE_1_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (60/60)	100.0 % (6/6)	N.A.	N.A.	100.0 % (67/67)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 717103
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	13267459	1
Bin	1	0	13269059	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	126416	1
Bin	1	0	963429	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	109550	1
Bin	1	0	980295	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	103929	1
Bin	1	0	985916	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	162358	1
Bin	1	0	927487	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	135873	1
Bin	1	0	953972	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	159944	1
Bin	1	0	929901	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	236123	1
Bin	1	0	853722	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	198401	1
Bin	1	0	891444	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	219247	1
Bin	1	0	220847	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	135078	1
Bin	1	0	136678	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	2626	1
Bin	1	0	1027	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	165	1
Bin	1	0	1765	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	355	1
Bin	1	0	1955	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	705	1
Bin	1	0	2305	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	3617	1
Bin	1	0	5217	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	5031	1
Bin	1	0	6631	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	10323	1
Bin	1	0	11923	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	22448	1
Bin	1	0	24048	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	44884	1
Bin	1	0	46484	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	20485	1
Bin	1	0	71192	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	22405	1
Bin	1	0	69272	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	22405	1
Bin	1	0	69272	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	31593	1
Bin	1	0	60084	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	40185	1
Bin	1	0	51492	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	40539	1
Bin	1	0	51138	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	44848	1
Bin	1	0	46829	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	44905	1
Bin	1	0	46772	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	90848	1
Bin	1	0	92448	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	135078	1
Bin	'1'	'0'	219247	1
Bin	'1'	'1'	135068	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	405429	1
Bin	'1'	'0'	44220	1
Bin	'1'	'1'	90848	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.TEST_REGISTERS_GEN_TRUE.TEST_REGISTERS_REG_MAP_COMP.TST_DEST_TST_ADDR_SLICE_1_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

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Port:

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Signal:

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Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: