NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.CONTROL_COUNTER_INST	100.0 % (45/45)	100.0 % (40/40)	100.0 % (158/158)	100.0 % (33/33)	N.A.	N.A.	100.0 % (276/276)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.CONTROL_COUNTER_INST

100.0 % (45/45)

100.0 % (40/40)

100.0 % (158/158)

100.0 % (33/33)

N.A.

100.0 % (276/276)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 178 to 180:

178:    ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else 
179:                              (ctrl_ctr_q - 1) when (rx_trigger = '1') else 
180:                                   ctrl_ctr_q;

Count: 30000099
Threshold: 1

Signal assignment statement on line 178:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else
Count: 1863775
Threshold: 1

Signal assignment statement on line 179:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else
Count: 17455150
Threshold: 1

Signal assignment statement on line 180:

180: ctrl_ctr_q;
Count: 10681174
Threshold: 1

If statement on lines 183 to 185:

183:    ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else 
184:                   '1' when (ctrl_ctr_pload = '1') else 
185:                   '0';

Count: 22376288
Threshold: 1

Signal assignment statement on line 183:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else
Count: 7646756
Threshold: 1

Signal assignment statement on line 184:

184: '1' when (ctrl_ctr_pload = '1') else
Count: 828450
Threshold: 1

Signal assignment statement on line 185:

185: '0';
Count: 13901082
Threshold: 1

If statement on lines 187 to 189:

187:    ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0) 
188:                         else 
189:                     '0';

Count: 7390749
Threshold: 1

Signal assignment statement on line 187:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)
Count: 355655
Threshold: 1

Signal assignment statement on line 189:

189: '0';
Count: 7035094
Threshold: 1

If statement on lines 191 to 193:

191:    ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1) 
192:                        else 
193:                    '0';

Count: 7390749
Threshold: 1

Signal assignment statement on line 191:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)
Count: 351446
Threshold: 1

Signal assignment statement on line 193:

193: '0';
Count: 7039303
Threshold: 1

If statement on lines 200 to 206:

200:        if (res_n = '0') then 
201:            ctrl_ctr_q <= (others => '0'); 
...
205:            end if; 
206:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 201:

201: ctrl_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 203 to 205:

203:            if (ctrl_ctr_ce = '1') then 
204:                ctrl_ctr_q <= ctrl_ctr_d; 
205:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 204:

204: ctrl_ctr_q <= ctrl_ctr_d;
Count: 7846950
Threshold: 1

If statement on lines 218 to 219:

218:    compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else 
219:                   compl_ctr_q + 1;

Count: 6179186
Threshold: 1

Signal assignment statement on line 218:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else
Count: 878930
Threshold: 1

Signal assignment statement on line 219:

219: compl_ctr_q + 1;
Count: 5300256
Threshold: 1

If statement on lines 221 to 223:

221:    compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else 
222:                    '1' when (compl_ctr_ena = '1') else 
223:                    '0';

Count: 10641200
Threshold: 1

Signal assignment statement on line 221:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else
Count: 889564
Threshold: 1

Signal assignment statement on line 222:

222: '1' when (compl_ctr_ena = '1') else
Count: 4471851
Threshold: 1

Signal assignment statement on line 223:

223: '0';
Count: 5279785
Threshold: 1

If statement on lines 227 to 233:

227:        if (res_n = '0') then 
228:            compl_ctr_q <= (others => '0'); 
...
232:            end if; 
233:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 228:

228: compl_ctr_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 230 to 232:

230:            if (compl_ctr_ce = '1') then 
231:                compl_ctr_q <= compl_ctr_d; 
232:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 231:

231: compl_ctr_q <= compl_ctr_d;
Count: 5350263
Threshold: 1

If statement on lines 240 to 242:

240:    ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111") 
241:                             else 
242:                         '0';

Count: 4491351
Threshold: 1

Signal assignment statement on line 240:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")
Count: 552157
Threshold: 1

Signal assignment statement on line 242:

242: '0';
Count: 3939194
Threshold: 1

Signal assignment statement on line 245:

245: ctrl_counted_byte_index <= std_logic_vector(compl_ctr_q(4 downto 3));
Count: 558319
Threshold: 1

Signal assignment statement on line 248:

248: compl_ctr_div_32 <= compl_ctr_q(G_CTRL_CTR_WIDTH - 1 downto 5);
Count: 144592
Threshold: 1

Signal assignment statement on line 251:

251: compl_ctr_div_32_plus_5 <= to_integer(compl_ctr_div_32) + 5;
Count: 144592
Threshold: 1

If statement on lines 254 to 256:

254:    compl_ctr_div_32_plus_5_sat <= 
255:        compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else 
256:        19;

Count: 144592
Threshold: 1

Signal assignment statement on line 255:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else
Count: 141174
Threshold: 1

Signal assignment statement on line 256:

256: 19;
Count: 3418
Threshold: 1

Signal assignment statement on line 267:

267: std_logic_vector(to_unsigned(compl_ctr_div_32_plus_5_sat, 5));
Count: 143267
Threshold: 1

If statement on lines 275 to 283:

275:        if (res_n = '0') then 
276:            alc_alc_bit <= (others => '0'); 
...
282:            end if; 
283:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 276:

276: alc_alc_bit <= (others => '0');
Count: 2424883
Threshold: 1

Signal assignment statement on line 277:

277: alc_alc_id_field <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 279 to 282:

279:            if (arbitration_lost = '1') then 
280:                alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0)); 
281:                alc_alc_id_field <= arbitration_part; 
282:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 280:

280: alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0));
Count: 711
Threshold: 1

Signal assignment statement on line 281:

281: alc_alc_id_field <= arbitration_part;
Count: 711
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 178:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	1863775	1
Bin	False	28136324	1

"if" / "when" / "else" condition on line 179:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	17455150	1
Bin	False	10681174	1

"if" / "when" / "else" condition on line 183:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	7646756	1
Bin	False	14729532	1

"if" / "when" / "else" condition on line 184:

184: '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	828450	1
Bin	False	13901082	1

"if" / "when" / "else" condition on line 187:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)

	Evaluated to	Count	Threshold
Bin	True	355655	1
Bin	False	7035094	1

"if" / "when" / "else" condition on line 191:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)

	Evaluated to	Count	Threshold
Bin	True	351446	1
Bin	False	7039303	1

"if" / "when" / "else" condition on line 200:

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 202:

202: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 203:

203: if (ctrl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	7846950	1
Bin	False	535944728	1

"if" / "when" / "else" condition on line 218:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	878930	1
Bin	False	5300256	1

"if" / "when" / "else" condition on line 221:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	889564	1
Bin	False	9751636	1

"if" / "when" / "else" condition on line 222:

222: '1' when (compl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	4471851	1
Bin	False	5279785	1

"if" / "when" / "else" condition on line 227:

227: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 229:

229: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 230:

230: if (compl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	5350263	1
Bin	False	538441415	1

"if" / "when" / "else" condition on line 240:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")

	Evaluated to	Count	Threshold
Bin	True	552157	1
Bin	False	3939194	1

"if" / "when" / "else" condition on line 255:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else

	Evaluated to	Count	Threshold
Bin	True	141174	1
Bin	False	3418	1

"if" / "when" / "else" condition on line 275:

275: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 278:

278: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 279:

279: if (arbitration_lost = '1') then

	Evaluated to	Count	Threshold
Bin	True	711	1
Bin	False	543790967	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_PLOAD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRL_CTR_PLOAD_VAL

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

COMPL_CTR_ENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ARBITRATION_LOST

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ARBITRATION_PART

	Element	From	To	Threshold	Excluded due to
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

CTRL_CTR_ZERO

	From	To	Count	Threshold
Bin	0	1	355655	1
Bin	1	0	355664	1

Port:

CTRL_CTR_ONE

	From	To	Count	Threshold
Bin	0	1	351446	1
Bin	1	0	353047	1

Port:

CTRL_COUNTED_BYTE

	From	To	Count	Threshold
Bin	0	1	552157	1
Bin	1	0	553758	1

Port:

CTRL_COUNTED_BYTE_INDEX

	Element	From	To	Count	Threshold
Bin	(1)	0	1	136998	1
Bin	(1)	1	0	138599	1
Bin	(0)	0	1	274576	1
Bin	(0)	1	0	276177	1

Port:

CTRL_CTR_MEM_INDEX

	Element	From	To	Count	Threshold
Bin	(4)	0	1	4751	1
Bin	(4)	1	0	6352	1
Bin	(3)	0	1	12555	1
Bin	(3)	1	0	14156	1
Bin	(2)	0	1	18907	1
Bin	(2)	1	0	18907	1
Bin	(1)	0	1	40779	1
Bin	(1)	1	0	42380	1
Bin	(0)	0	1	67845	1
Bin	(0)	1	0	67845	1

Port:

ALC_ALC_BIT

	Element	From	To	Count	Threshold
Bin	(4)	0	1	68	1
Bin	(4)	1	0	1667	1
Bin	(3)	0	1	89	1
Bin	(3)	1	0	1688	1
Bin	(2)	0	1	102	1
Bin	(2)	1	0	1701	1
Bin	(1)	0	1	170	1
Bin	(1)	1	0	1769	1
Bin	(0)	0	1	297	1
Bin	(0)	1	0	1896	1

Port:

ALC_ALC_ID_FIELD

	Element	From	To	Count	Threshold
Bin	(2)	0	1	35	1
Bin	(2)	1	0	1636	1
Bin	(1)	0	1	41	1
Bin	(1)	1	0	1640	1
Bin	(0)	0	1	92	1
Bin	(0)	1	0	1693	1

Signal:

CTRL_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	860457	1
Bin	(8)	1	0	862058	1
Bin	(7)	0	1	884542	1
Bin	(7)	1	0	886143	1
Bin	(6)	0	1	932167	1
Bin	(6)	1	0	933768	1
Bin	(5)	0	1	1047119	1
Bin	(5)	1	0	1048720	1
Bin	(4)	0	1	1311676	1
Bin	(4)	1	0	1313277	1
Bin	(3)	0	1	2077611	1
Bin	(3)	1	0	2079211	1
Bin	(2)	0	1	3437911	1
Bin	(2)	1	0	3439505	1
Bin	(1)	0	1	6009693	1
Bin	(1)	1	0	6011289	1
Bin	(0)	0	1	14104430	1
Bin	(0)	1	0	14106022	1

Signal:

CTRL_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	125557	1
Bin	(8)	1	0	127158	1
Bin	(7)	0	1	133454	1
Bin	(7)	1	0	135055	1
Bin	(6)	0	1	149218	1
Bin	(6)	1	0	150819	1
Bin	(5)	0	1	187298	1
Bin	(5)	1	0	188899	1
Bin	(4)	0	1	270313	1
Bin	(4)	1	0	271914	1
Bin	(3)	0	1	517613	1
Bin	(3)	1	0	519214	1
Bin	(2)	0	1	959409	1
Bin	(2)	1	0	961003	1
Bin	(1)	0	1	1864662	1
Bin	(1)	1	0	1866258	1
Bin	(0)	0	1	3584832	1
Bin	(0)	1	0	3586425	1

Signal:

CTRL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	7792162	1
Bin	1	0	7793762	1

Signal:

COMPL_CTR_D

	Element	From	To	Count	Threshold
Bin	(8)	0	1	8037	1
Bin	(8)	1	0	9638	1
Bin	(7)	0	1	17317	1
Bin	(7)	1	0	18918	1
Bin	(6)	0	1	37462	1
Bin	(6)	1	0	39063	1
Bin	(5)	0	1	75980	1
Bin	(5)	1	0	77581	1
Bin	(4)	0	1	145217	1
Bin	(4)	1	0	146818	1
Bin	(3)	0	1	292604	1
Bin	(3)	1	0	294205	1
Bin	(2)	0	1	562443	1
Bin	(2)	1	0	564044	1
Bin	(1)	0	1	1125158	1
Bin	(1)	1	0	1126759	1
Bin	(0)	0	1	3038642	1
Bin	(0)	1	0	3037042	1

Signal:

COMPL_CTR_Q

	Element	From	To	Count	Threshold
Bin	(8)	0	1	213888	1
Bin	(8)	1	0	351540	1
Bin	(7)	0	1	453517	1
Bin	(7)	1	0	597682	1
Bin	(6)	0	1	926353	1
Bin	(6)	1	0	1076482	1
Bin	(5)	0	1	1999632	1
Bin	(5)	1	0	2287323	1
Bin	(4)	0	1	1083011	1
Bin	(4)	1	0	1182395	1
Bin	(3)	0	1	2170548	1
Bin	(3)	1	0	2271469	1
Bin	(2)	0	1	560516	1
Bin	(2)	1	0	563920	1
Bin	(1)	0	1	1121344	1
Bin	(1)	1	0	1124748	1
Bin	(0)	0	1	2239758	1
Bin	(0)	1	0	2243162	1

Signal:

COMPL_CTR_DIV_32

	Element	From	To	Count	Threshold
Bin	(3)	0	1	7056	1
Bin	(3)	1	0	8657	1
Bin	(2)	0	1	14933	1
Bin	(2)	1	0	16534	1
Bin	(1)	0	1	30488	1
Bin	(1)	1	0	32089	1
Bin	(0)	0	1	67569	1
Bin	(0)	1	0	69170	1

Signal:

COMPL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	5274983	1
Bin	1	0	5276583	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 178:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	28136324	1
Bin	True	1863775	1

"=" expression on line 179:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	10681174	1
Bin	True	17455150	1

"and" expression on line 183:

 rx_trigger = '1' and ctrl_ctr_ena = '1' 
 <-----LHS------>     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	7885652	1
Bin	True	False	3486520	1
Bin	True	True	7646756	1

"=" expression on line 183:

rx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11243012	1
Bin	True	11133276	1

"=" expression on line 183:

ctrl_ctr_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	6843880	1
Bin	True	15532408	1

"=" expression on line 184:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	13901082	1
Bin	True	828450	1

"=" expression on line 200:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 203:

ctrl_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	535944728	1
Bin	True	7846950	1

"=" expression on line 218:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	5300256	1
Bin	True	878930	1

"=" expression on line 221:

ctrl_ctr_pload = '1'

	Evaluated to	Count	Threshold
Bin	False	9751636	1
Bin	True	889564	1

"=" expression on line 222:

compl_ctr_ena = '1'

	Evaluated to	Count	Threshold
Bin	False	5279785	1
Bin	True	4471851	1

"=" expression on line 227:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 230:

compl_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	538441415	1
Bin	True	5350263	1

"<" expression on line 255:

compl_ctr_div_32_plus_5 < 19

	Evaluated to	Count	Threshold
Bin	False	3418	1
Bin	True	141174	1

"=" expression on line 275:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 279:

arbitration_lost = '1'

	Evaluated to	Count	Threshold
Bin	False	543790967	1
Bin	True	711	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.CONTROL_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control.vhd

Details:

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"if" / "when" / "else" condition on line 183:

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"if" / "when" / "else" condition on line 278:

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