NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.CONTROL_COUNTER_INST	100.0 % (44/44)	100.0 % (40/40)	100.0 % (158/158)	100.0 % (33/33)	N.A.	N.A.	100.0 % (275/275)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

178:    ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else 
179:                              (ctrl_ctr_q - 1) when (rx_trigger = '1') else 
180:                                   ctrl_ctr_q;

Count: 29255495
Threshold: 1

Signal assignment statement:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else
Count: 1834797
Threshold: 1

Signal assignment statement:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else
Count: 17087580
Threshold: 1

Signal assignment statement:

180: ctrl_ctr_q;
Count: 10333118
Threshold: 1

If statement:

183:    ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else 
184:                   '1' when (ctrl_ctr_pload = '1') else 
185:                   '0';

Count: 21662235
Threshold: 1

Signal assignment statement:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else
Count: 7613189
Threshold: 1

Signal assignment statement:

184: '1' when (ctrl_ctr_pload = '1') else
Count: 816938
Threshold: 1

Signal assignment statement:

185: '0';
Count: 13232108
Threshold: 1

If statement:

187:    ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0) 
188:                         else 
189:                     '0';

Count: 7362207
Threshold: 1

Signal assignment statement:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)
Count: 350694
Threshold: 1

Signal assignment statement:

189: '0';
Count: 7011513
Threshold: 1

If statement:

191:    ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1) 
192:                        else 
193:                    '0';

Count: 7362207
Threshold: 1

Signal assignment statement:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)
Count: 346470
Threshold: 1

Signal assignment statement:

193: '0';
Count: 7015737
Threshold: 1

If statement:

200:        if (res_n = '0') then 
201:            ctrl_ctr_q <= (others => '0'); 
...
205:            end if; 
206:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

201: ctrl_ctr_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

203:            if (ctrl_ctr_ce = '1') then 
204:                ctrl_ctr_q <= ctrl_ctr_d; 
205:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

204: ctrl_ctr_q <= ctrl_ctr_d;
Count: 7814928
Threshold: 1

If statement:

218:    compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else 
219:                   compl_ctr_q + 1;

Count: 6180551
Threshold: 1

Signal assignment statement:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else
Count: 866026
Threshold: 1

Signal assignment statement:

219: compl_ctr_q + 1;
Count: 5314525
Threshold: 1

If statement:

221:    compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else 
222:                    '1' when (compl_ctr_ena = '1') else 
223:                    '0';

Count: 10669433
Threshold: 1

Signal assignment statement:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else
Count: 876733
Threshold: 1

Signal assignment statement:

222: '1' when (compl_ctr_ena = '1') else
Count: 4497889
Threshold: 1

Signal assignment statement:

223: '0';
Count: 5294811
Threshold: 1

If statement:

227:        if (res_n = '0') then 
228:            compl_ctr_q <= (others => '0'); 
...
232:            end if; 
233:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

228: compl_ctr_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

230:            if (compl_ctr_ce = '1') then 
231:                compl_ctr_q <= compl_ctr_d; 
232:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

231: compl_ctr_q <= compl_ctr_d;
Count: 5366267
Threshold: 1

If statement:

240:    ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111") 
241:                             else 
242:                         '0';

Count: 4517028
Threshold: 1

Signal assignment statement:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")
Count: 555551
Threshold: 1

Signal assignment statement:

242: '0';
Count: 3961477
Threshold: 1

Signal assignment statement:

245: ctrl_counted_byte_index <= std_logic_vector(compl_ctr_q(4 downto 3));
Count: 561315
Threshold: 1

Signal assignment statement:

251: compl_ctr_div_32_plus_5 <= to_integer(compl_ctr_div_32) + 5;
Count: 145817
Threshold: 1

If statement:

254:    compl_ctr_div_32_plus_5_sat <= 
255:        compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else 
256:        19;

Count: 145817
Threshold: 1

Signal assignment statement:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else
Count: 142343
Threshold: 1

Signal assignment statement:

256: 19;
Count: 3474
Threshold: 1

Signal assignment statement:

267: std_logic_vector(to_unsigned(compl_ctr_div_32_plus_5_sat, 5));
Count: 144464
Threshold: 1

If statement:

275:        if (res_n = '0') then 
276:            alc_alc_bit <= (others => '0'); 
...
282:            end if; 
283:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

276: alc_alc_bit <= (others => '0');
Count: 2418499
Threshold: 1

Signal assignment statement:

277: alc_alc_id_field <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

279:            if (arbitration_lost = '1') then 
280:                alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0)); 
281:                alc_alc_id_field <= arbitration_part; 
282:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

280: alc_alc_bit <= std_logic_vector(ctrl_ctr_q(4 downto 0));
Count: 709
Threshold: 1

Signal assignment statement:

281: alc_alc_id_field <= arbitration_part;
Count: 709
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	1834797	1
Bin	False	27420698	1

"if" / "when" / "else" condition:

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	17087580	1
Bin	False	10333118	1

"if" / "when" / "else" condition:

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	7613189	1
Bin	False	14049046	1

"if" / "when" / "else" condition:

184: '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	816938	1
Bin	False	13232108	1

"if" / "when" / "else" condition:

187: ctrl_ctr_zero <= '1' when (ctrl_ctr_q = 0)

	Evaluated to	Count	Threshold
Bin	True	350694	1
Bin	False	7011513	1

"if" / "when" / "else" condition:

191: ctrl_ctr_one <= '1' when (ctrl_ctr_q = 1)

	Evaluated to	Count	Threshold
Bin	True	346470	1
Bin	False	7015737	1

"if" / "when" / "else" condition:

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

202: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

203: if (ctrl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	7814928	1
Bin	False	518559372	1

"if" / "when" / "else" condition:

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	866026	1
Bin	False	5314525	1

"if" / "when" / "else" condition:

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	True	876733	1
Bin	False	9792700	1

"if" / "when" / "else" condition:

222: '1' when (compl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	True	4497889	1
Bin	False	5294811	1

"if" / "when" / "else" condition:

227: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

229: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

230: if (compl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	5366267	1
Bin	False	521008033	1

"if" / "when" / "else" condition:

240: ctrl_counted_byte <= '1' when (compl_ctr_q(2 downto 0) = "111")

	Evaluated to	Count	Threshold
Bin	True	555551	1
Bin	False	3961477	1

"if" / "when" / "else" condition:

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else

	Evaluated to	Count	Threshold
Bin	True	142343	1
Bin	False	3474	1

"if" / "when" / "else" condition:

275: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

278: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

279: if (arbitration_lost = '1') then

	Evaluated to	Count	Threshold
Bin	True	709	1
Bin	False	526373591	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

RX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	10015414	1
Bin	1	0	10017014	1

Port:

CTRL_CTR_ENA

	From	To	Count	Threshold
Bin	0	1	211888	1
Bin	1	0	213482	1

Port:

CTRL_CTR_PLOAD

	From	To	Count	Threshold
Bin	0	1	830082	1
Bin	1	0	831681	1

Port:

CTRL_CTR_PLOAD_VAL(8)

	From	To	Count	Threshold
Bin	0	1	16717	1
Bin	1	0	18317	1

Port:

CTRL_CTR_PLOAD_VAL(7)

	From	To	Count	Threshold
Bin	0	1	18114	1
Bin	1	0	19714	1

Port:

CTRL_CTR_PLOAD_VAL(6)

	From	To	Count	Threshold
Bin	0	1	19404	1
Bin	1	0	21004	1

Port:

CTRL_CTR_PLOAD_VAL(5)

	From	To	Count	Threshold
Bin	0	1	29382	1
Bin	1	0	30982	1

Port:

CTRL_CTR_PLOAD_VAL(4)

	From	To	Count	Threshold
Bin	0	1	81832	1
Bin	1	0	83432	1

Port:

CTRL_CTR_PLOAD_VAL(3)

	From	To	Count	Threshold
Bin	0	1	152935	1
Bin	1	0	154534	1

Port:

CTRL_CTR_PLOAD_VAL(2)

	From	To	Count	Threshold
Bin	0	1	266397	1
Bin	1	0	267996	1

Port:

CTRL_CTR_PLOAD_VAL(1)

	From	To	Count	Threshold
Bin	0	1	400847	1
Bin	1	0	402445	1

Port:

CTRL_CTR_PLOAD_VAL(0)

	From	To	Count	Threshold
Bin	0	1	284777	1
Bin	1	0	286375	1

Port:

COMPL_CTR_ENA

	From	To	Count	Threshold
Bin	0	1	4533937	1
Bin	1	0	4535537	1

Port:

ARBITRATION_LOST

	From	To	Count	Threshold
Bin	0	1	1172	1
Bin	1	0	2772	1

Port:

ARBITRATION_PART(2)

	From	To	Count	Threshold
Bin	0	1	15717	1
Bin	1	0	17317	1

Port:

ARBITRATION_PART(1)

	From	To	Count	Threshold
Bin	0	1	52648	1
Bin	1	0	54248	1

Port:

ARBITRATION_PART(0)

	From	To	Count	Threshold
Bin	0	1	121694	1
Bin	1	0	123294	1

Port:

CTRL_CTR_ZERO

	From	To	Count	Threshold
Bin	0	1	350694	1
Bin	1	0	350701	1

Port:

CTRL_CTR_ONE

	From	To	Count	Threshold
Bin	0	1	346470	1
Bin	1	0	348070	1

Port:

CTRL_COUNTED_BYTE

	From	To	Count	Threshold
Bin	0	1	555551	1
Bin	1	0	557151	1

Port:

CTRL_COUNTED_BYTE_INDEX(1)

	From	To	Count	Threshold
Bin	0	1	137781	1
Bin	1	0	139381	1

Port:

CTRL_COUNTED_BYTE_INDEX(0)

	From	To	Count	Threshold
Bin	0	1	276272	1
Bin	1	0	277872	1

Port:

CTRL_CTR_MEM_INDEX(4)

	From	To	Count	Threshold
Bin	0	1	4934	1
Bin	1	0	6534	1

Port:

CTRL_CTR_MEM_INDEX(3)

	From	To	Count	Threshold
Bin	0	1	12610	1
Bin	1	0	14210	1

Port:

CTRL_CTR_MEM_INDEX(2)

	From	To	Count	Threshold
Bin	0	1	19144	1
Bin	1	0	19144	1

Port:

CTRL_CTR_MEM_INDEX(1)

	From	To	Count	Threshold
Bin	0	1	40973	1
Bin	1	0	42573	1

Port:

CTRL_CTR_MEM_INDEX(0)

	From	To	Count	Threshold
Bin	0	1	68453	1
Bin	1	0	68453	1

Port:

ALC_ALC_BIT(4)

	From	To	Count	Threshold
Bin	0	1	67	1
Bin	1	0	1665	1

Port:

ALC_ALC_BIT(3)

	From	To	Count	Threshold
Bin	0	1	88	1
Bin	1	0	1686	1

Port:

ALC_ALC_BIT(2)

	From	To	Count	Threshold
Bin	0	1	101	1
Bin	1	0	1699	1

Port:

ALC_ALC_BIT(1)

	From	To	Count	Threshold
Bin	0	1	171	1
Bin	1	0	1769	1

Port:

ALC_ALC_BIT(0)

	From	To	Count	Threshold
Bin	0	1	296	1
Bin	1	0	1894	1

Port:

ALC_ALC_ID_FIELD(2)

	From	To	Count	Threshold
Bin	0	1	30	1
Bin	1	0	1630	1

Port:

ALC_ALC_ID_FIELD(1)

	From	To	Count	Threshold
Bin	0	1	40	1
Bin	1	0	1638	1

Port:

ALC_ALC_ID_FIELD(0)

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	1696	1

Signal:

CTRL_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	849760	1
Bin	1	0	851360	1

Signal:

CTRL_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	873706	1
Bin	1	0	875306	1

Signal:

CTRL_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	921783	1
Bin	1	0	923383	1

Signal:

CTRL_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	1037427	1
Bin	1	0	1039027	1

Signal:

CTRL_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	1299223	1
Bin	1	0	1300823	1

Signal:

CTRL_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	2064170	1
Bin	1	0	2065769	1

Signal:

CTRL_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	3418510	1
Bin	1	0	3420105	1

Signal:

CTRL_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	5983550	1
Bin	1	0	5985145	1

Signal:

CTRL_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	13744876	1
Bin	1	0	13746469	1

Signal:

CTRL_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	123143	1
Bin	1	0	124743	1

Signal:

CTRL_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	130974	1
Bin	1	0	132574	1

Signal:

CTRL_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	146909	1
Bin	1	0	148509	1

Signal:

CTRL_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	185102	1
Bin	1	0	186702	1

Signal:

CTRL_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	268203	1
Bin	1	0	269803	1

Signal:

CTRL_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	514719	1
Bin	1	0	516319	1

Signal:

CTRL_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	954317	1
Bin	1	0	955912	1

Signal:

CTRL_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	1856770	1
Bin	1	0	1858365	1

Signal:

CTRL_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	3572380	1
Bin	1	0	3573974	1

Signal:

CTRL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	7758415	1
Bin	1	0	7760014	1

Signal:

COMPL_CTR_D(8)

	From	To	Count	Threshold
Bin	0	1	8431	1
Bin	1	0	10031	1

Signal:

COMPL_CTR_D(7)

	From	To	Count	Threshold
Bin	0	1	17656	1
Bin	1	0	19256	1

Signal:

COMPL_CTR_D(6)

	From	To	Count	Threshold
Bin	0	1	38027	1
Bin	1	0	39627	1

Signal:

COMPL_CTR_D(5)

	From	To	Count	Threshold
Bin	0	1	75789	1
Bin	1	0	77389	1

Signal:

COMPL_CTR_D(4)

	From	To	Count	Threshold
Bin	0	1	145407	1
Bin	1	0	147007	1

Signal:

COMPL_CTR_D(3)

	From	To	Count	Threshold
Bin	0	1	293989	1
Bin	1	0	295589	1

Signal:

COMPL_CTR_D(2)

	From	To	Count	Threshold
Bin	0	1	565613	1
Bin	1	0	567213	1

Signal:

COMPL_CTR_D(1)

	From	To	Count	Threshold
Bin	0	1	1131518	1
Bin	1	0	1133118	1

Signal:

COMPL_CTR_D(0)

	From	To	Count	Threshold
Bin	0	1	3040358	1
Bin	1	0	3038759	1

Signal:

COMPL_CTR_Q(8)

	From	To	Count	Threshold
Bin	0	1	219712	1
Bin	1	0	356583	1

Signal:

COMPL_CTR_Q(7)

	From	To	Count	Threshold
Bin	0	1	457654	1
Bin	1	0	599044	1

Signal:

COMPL_CTR_Q(6)

	From	To	Count	Threshold
Bin	0	1	939038	1
Bin	1	0	1082761	1

Signal:

COMPL_CTR_Q(5)

	From	To	Count	Threshold
Bin	0	1	2026270	1
Bin	1	0	2289073	1

Signal:

COMPL_CTR_Q(4)

	From	To	Count	Threshold
Bin	0	1	1089785	1
Bin	1	0	1189398	1

Signal:

COMPL_CTR_Q(3)

	From	To	Count	Threshold
Bin	0	1	2184722	1
Bin	1	0	2286546	1

Signal:

COMPL_CTR_Q(2)

	From	To	Count	Threshold
Bin	0	1	563735	1
Bin	1	0	567095	1

Signal:

COMPL_CTR_Q(1)

	From	To	Count	Threshold
Bin	0	1	1127799	1
Bin	1	0	1131159	1

Signal:

COMPL_CTR_Q(0)

	From	To	Count	Threshold
Bin	0	1	2252682	1
Bin	1	0	2256042	1

Signal:

COMPL_CTR_DIV_32(3)

	From	To	Count	Threshold
Bin	0	1	7238	1
Bin	1	0	8838	1

Signal:

COMPL_CTR_DIV_32(2)

	From	To	Count	Threshold
Bin	0	1	15062	1
Bin	1	0	16662	1

Signal:

COMPL_CTR_DIV_32(1)

	From	To	Count	Threshold
Bin	0	1	30869	1
Bin	1	0	32469	1

Signal:

COMPL_CTR_DIV_32(0)

	From	To	Count	Threshold
Bin	0	1	68206	1
Bin	1	0	69806	1

Signal:

COMPL_CTR_CE

	From	To	Count	Threshold
Bin	0	1	5290012	1
Bin	1	0	5291611	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

178: ctrl_ctr_d <= unsigned(ctrl_ctr_pload_val) when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	False	27420698	1
Bin	True	1834797	1

"=" expression

179: (ctrl_ctr_q - 1) when (rx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	False	10333118	1
Bin	True	17087580	1

"=" expression

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	False	10887127	1
Bin	True	10775108	1

"=" expression

183: ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	False	6198971	1
Bin	True	15463264	1

"and" expression

183:    ctrl_ctr_ce <= '1' when (rx_trigger = '1' and ctrl_ctr_ena = '1') else 
                                 <-----LHS------>     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	7850075	1
Bin	True	False	3161919	1
Bin	True	True	7613189	1

"=" expression

184: '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	False	13232108	1
Bin	True	816938	1

"=" expression

200: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

203: if (ctrl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	518559372	1
Bin	True	7814928	1

"=" expression

218: compl_ctr_d <= (others => '0') when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	False	5314525	1
Bin	True	866026	1

"=" expression

221: compl_ctr_ce <= '1' when (ctrl_ctr_pload = '1') else

	Evaluated to	Count	Threshold
Bin	False	9792700	1
Bin	True	876733	1

"=" expression

222: '1' when (compl_ctr_ena = '1') else

	Evaluated to	Count	Threshold
Bin	False	5294811	1
Bin	True	4497889	1

"=" expression

227: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

230: if (compl_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	521008033	1
Bin	True	5366267	1

"<" expression

255: compl_ctr_div_32_plus_5 when (compl_ctr_div_32_plus_5 < 19) else

	Evaluated to	Count	Threshold
Bin	False	3474	1
Bin	True	142343	1

"=" expression

275: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

279: if (arbitration_lost = '1') then

	Evaluated to	Count	Threshold
Bin	False	526373591	1
Bin	True	709	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.PROTOCOL_CONTROL_INST.CONTROL_COUNTER_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/control_counter.vhd

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