NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 19156
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 19156
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 612992
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 19156
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	973	1
Bin	1	0	1592	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	1091	1
Bin	1	0	1711	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	993	1
Bin	1	0	1612	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	2718	1
Bin	1	0	3327	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	2695	1
Bin	1	0	3296	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	2787	1
Bin	1	0	3394	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	2562	1
Bin	1	0	3169	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	2692	1
Bin	1	0	3300	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	3012	1
Bin	1	0	3615	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	2766	1
Bin	1	0	3367	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	3130	1
Bin	1	0	3728	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	2846	1
Bin	1	0	3450	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	3322	1
Bin	1	0	3922	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	3063	1
Bin	1	0	3669	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	2398	1
Bin	1	0	3013	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	2168	1
Bin	1	0	2784	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	1899	1
Bin	1	0	2508	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	2448	1
Bin	1	0	3064	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	2061	1
Bin	1	0	2674	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	2487	1
Bin	1	0	3100	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	2085	1
Bin	1	0	2696	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	2481	1
Bin	1	0	3092	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	3211	1
Bin	1	0	3810	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	2183	1
Bin	1	0	2793	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	4011	1
Bin	1	0	4597	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	3294	1
Bin	1	0	3888	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	3111	1
Bin	1	0	3719	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	1852	1
Bin	1	0	2466	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	2671	1
Bin	1	0	3265	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	3234	1
Bin	1	0	3837	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	2781	1
Bin	1	0	3377	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	3526	1
Bin	1	0	4121	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	4609	1
Bin	1	0	4022	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	128097	1
Bin	'0'	'1'	46507	1
Bin	'1'	'0'	365100	1
Bin	'1'	'1'	52168	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

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Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: