NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CLK_GATE_CONTROL_REGS_COMP.G_TECH_ASIC	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (8/8)	N.A.	N.A.	100.0 % (13/13)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CLK_GATE_CONTROL_REGS_COMP.G_TECH_ASIC

100.0 % (3/3)

100.0 % (2/2)

N.A.

100.0 % (8/8)

N.A.

100.0 % (13/13)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 113 to 115:

113:            if (clk_in = '0') then 
114:                clk_en_q <= clk_en or scan_enable; 
115:            end if;

Count: 1095979370
Threshold: 1

Signal assignment statement on line 114:

114: clk_en_q <= clk_en or scan_enable;
Count: 547989675
Threshold: 1

Signal assignment statement on line 119:

119: clk_out <= clk_in AND clk_en_q;
Count: 1095980805
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 113:

113: if (clk_in = '0') then

	Evaluated to	Count	Threshold
Bin	True	547989675	1
Bin	False	547989695	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 113:

clk_in = '0'

	Evaluated to	Count	Threshold
Bin	False	547989695	1
Bin	True	547989675	1

"or" expression on line 114:

 clk_en or scan_enable 
 <LHS->    <---RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	530812939	1
Bin	'0'	'1'	40	1
Bin	'1'	'0'	17176696	1

"and" expression on line 119:

 clk_in AND clk_en_q 
 <LHS->     <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	34353435	1
Bin	'1'	'0'	513634819	1
Bin	'1'	'1'	17176736	1