NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.MT_5_TXT_BUFFS

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.MT_5_TXT_BUFFS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

649:        mr_tx_command_txbi(5)   <= mr_ctrl_out_i.tx_command_txb6 when (mr_ctrl_out_i.mode_txbbm = '0') 
650:                                                                 else 
651:                                   mr_ctrl_out_i.tx_command_txb5 or mr_ctrl_out_i.tx_command_txb6;

Count: 565
Threshold: 1

Signal assignment statement:

649:        mr_tx_command_txbi(5)   <= mr_ctrl_out_i.tx_command_txb6 when (mr_ctrl_out_i.mode_txbbm = '0')

Count: 369
Threshold: 1

Signal assignment statement:

651:                                   mr_ctrl_out_i.tx_command_txb5 or mr_ctrl_out_i.tx_command_txb6;

Count: 196
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

649:        mr_tx_command_txbi(5)   <= mr_ctrl_out_i.tx_command_txb6 when (mr_ctrl_out_i.mode_txbbm = '0')

	Evaluated to	Count	Threshold
Bin	True	369	1
Bin	False	196	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

649:        mr_tx_command_txbi(5)   <= mr_ctrl_out_i.tx_command_txb6 when (mr_ctrl_out_i.mode_txbbm = '0')

	Evaluated to	Count	Threshold
Bin	False	196	1
Bin	True	369	1

"or" expression

651:                                   mr_ctrl_out_i.tx_command_txb5 or mr_ctrl_out_i.tx_command_txb6; 
                                       <------------LHS------------>    <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	17	1
Bin	'0'	'1'	2	1
Bin	'1'	'0'	12	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.MT_5_TXT_BUFFS

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/memory_registers.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"or" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: