NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CLK_GATE_TEST_REGS_COMP.G_TECH_FPGA

File:  /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/clk_gate.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CLK_GATE_TEST_REGS_COMP.G_TECH_FPGA 100.0 % (1/1) N.A. N.A. N.A. N.A. N.A. 100.0 % (1/1)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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Signal assignment statement:

130:        clk_en_q <= '1'; 
Count: 165
Threshold: 1

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