NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(1)	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (7/7)	N.A.	N.A.	100.0 % (12/12)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

143:        byte_we(i) <= '1' when (write = '1' and be(i) = '1') 
144:                          else 
145:                      '0';

Count: 55911247
Threshold: 1

Signal assignment statement:

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')
Count: 158140
Threshold: 1

Signal assignment statement:

145: '0';
Count: 55753107
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')

	Evaluated to	Count	Threshold
Bin	True	158140	1
Bin	False	55753107	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"and" expression

143:        byte_we(i) <= '1' when (write = '1' and be(i) = '1') 
                                    <---LHS--->     <---RHS--->

	LHS	RHS	Count	Threshold	Excluded due to
Bin	False	True	0	1	Unreachable

Covered expressions:

"=" expression

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')

	Evaluated to	Count	Threshold
Bin	False	55594392	1
Bin	True	316855	1

"=" expression

143: byte_we(i) <= '1' when (write = '1' and be(i) = '1')

	Evaluated to	Count	Threshold
Bin	False	158715	1
Bin	True	158140	1

"and" expression

143:        byte_we(i) <= '1' when (write = '1' and be(i) = '1') 
                                    <---LHS--->     <---RHS--->

	LHS	RHS	Count	Threshold
Bin	True	False	158715	1
Bin	True	True	158140	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.BYTE_GEN(1)

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

"and" expression

Covered expressions:

"=" expression

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: