NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 5688
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 5688
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 182016
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 5688
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	227	1
Bin	1	0	382	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	486	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	303	1
Bin	1	0	458	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	599	1
Bin	1	0	748	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	775	1
Bin	1	0	925	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	786	1
Bin	1	0	936	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	749	1
Bin	1	0	900	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	798	1
Bin	1	0	950	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	925	1
Bin	1	0	1072	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	925	1
Bin	1	0	1075	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	802	1
Bin	1	0	951	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	732	1
Bin	1	0	884	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	905	1
Bin	1	0	1056	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	765	1
Bin	1	0	915	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	506	1
Bin	1	0	660	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	545	1
Bin	1	0	700	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	513	1
Bin	1	0	667	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	656	1
Bin	1	0	809	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	653	1
Bin	1	0	806	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	514	1
Bin	1	0	666	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	576	1
Bin	1	0	729	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	479	1
Bin	1	0	633	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	1027	1
Bin	1	0	1175	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	716	1
Bin	1	0	870	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	1322	1
Bin	1	0	1467	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	998	1
Bin	1	0	1144	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	936	1
Bin	1	0	1086	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	671	1
Bin	1	0	824	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	701	1
Bin	1	0	851	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	945	1
Bin	1	0	1093	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	882	1
Bin	1	0	1032	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	1119	1
Bin	1	0	1264	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	1449	1
Bin	1	0	1309	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	41943	1
Bin	'0'	'1'	13302	1
Bin	'1'	'0'	106230	1
Bin	'1'	'1'	15261	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_READ_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

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Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

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Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: