NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_C_INST.GEN_FILT_POS

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd

Sub-instances:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average

Current Instance:

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_C_INST.GEN_FILT_POS	100.0 % (3/3)	100.0 % (2/2)	N.A.	100.0 % (5/5)	N.A.	N.A.	100.0 % (10/10)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

126:        valid <= '1' when (masked_input = masked_value) and (enable = '1') 
127:                     else 
128:                 '0';

Count: 2645
Threshold: 1

Signal assignment statement:

126: valid <= '1' when (masked_input = masked_value) and (enable = '1')
Count: 546
Threshold: 1

Signal assignment statement:

128: '0';
Count: 2099
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

126: valid <= '1' when (masked_input = masked_value) and (enable = '1')

	Evaluated to	Count	Threshold
Bin	True	546	1
Bin	False	2099	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

126: valid <= '1' when (masked_input = masked_value) and (enable = '1')

	Evaluated to	Count	Threshold
Bin	False	1647	1
Bin	True	998	1

"and" expression

126:        valid <= '1' when (masked_input = masked_value) and (enable = '1') 
                               <-----------LHS----------->       <---RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	452	1
Bin	True	False	784	1
Bin	True	True	546	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.FRAME_FILTERS_INST.BIT_FILTER_C_INST.GEN_FILT_POS

File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/bit_filter.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: