NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.TRIGGER_GENERATOR_INST	100.0 % (16/16)	100.0 % (14/14)	100.0 % (22/22)	100.0 % (18/18)	N.A.	N.A.	100.0 % (70/70)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.TRIGGER_GENERATOR_INST

100.0 % (16/16)

100.0 % (14/14)

100.0 % (22/22)

100.0 % (18/18)

N.A.

100.0 % (70/70)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 168 to 170:

168:    tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else 
169:                          '0' when (rx_trig_req_q = '0') else 
170:                          tx_trig_req_flag_q;

Count: 68316590
Threshold: 1

Signal assignment statement on line 168:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else
Count: 11382229
Threshold: 1

Signal assignment statement on line 169:

169: '0' when (rx_trig_req_q = '0') else
Count: 34167586
Threshold: 1

Signal assignment statement on line 170:

170: tx_trig_req_flag_q;
Count: 22766775
Threshold: 1

If statement on lines 174 to 178:

174:        if (res_n = '0') then 
175:            tx_trig_req_flag_q <= '0'; 
176:        elsif (rising_edge(clk_sys)) then 
177:            tx_trig_req_flag_q <= tx_trig_req_flag_d; 
178:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 175:

175: tx_trig_req_flag_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 177:

177: tx_trig_req_flag_q <= tx_trig_req_flag_d;
Count: 543791678
Threshold: 1

Signal assignment statement on line 181:

181: tx_trig_req_flag_dq <= tx_trig_req or tx_trig_req_flag_q;
Count: 45551402
Threshold: 1

If statement on lines 188 to 192:

188:        if (res_n = '0') then 
189:            rx_trig_req_q <= '0'; 
190:        elsif (rising_edge(clk_sys)) then 
191:            rx_trig_req_q <= rx_trig_req; 
192:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 189:

189: rx_trig_req_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 191:

191: rx_trig_req_q <= rx_trig_req;
Count: 543791678
Threshold: 1

Signal assignment statement on line 200:

200: rx_triggers(1) <= rx_trig_req;
Count: 45560178
Threshold: 1

Signal assignment statement on line 201:

201: rx_triggers(0) <= rx_trig_req_q;
Count: 22767676
Threshold: 1

If statement on lines 208 to 209:

208:    tx_trigger <= '0' when (rx_trig_req_q = '1') else 
209:                  tx_trig_req_flag_dq;

Count: 68314096
Threshold: 1

Signal assignment statement on line 208:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else
Count: 34145796
Threshold: 1

Signal assignment statement on line 209:

209: tx_trig_req_flag_dq;
Count: 34168300
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 168:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	11382229	1
Bin	False	56934361	1

"if" / "when" / "else" condition on line 169:

169: '0' when (rx_trig_req_q = '0') else

	Evaluated to	Count	Threshold
Bin	True	34167586	1
Bin	False	22766775	1

"if" / "when" / "else" condition on line 174:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 176:

176: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 188:

188: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 190:

190: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 208:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	34145796	1
Bin	False	34168300	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RX_TRIG_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIG_REQ

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

RX_TRIGGERS

	Element	From	To	Count	Threshold
Bin	(1)	0	1	34160725	1
Bin	(1)	1	0	34163927	1
Bin	(0)	0	1	22764474	1
Bin	(0)	1	0	45558577	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11391077	1
Bin	1	0	11392677	1

Signal:

RX_TRIG_REQ_Q

	From	To	Count	Threshold
Bin	0	1	11382237	1
Bin	1	0	11383838	1

Signal:

TX_TRIG_REQ_FLAG_D

	From	To	Count	Threshold
Bin	0	1	11382229	1
Bin	1	0	11383830	1

Signal:

TX_TRIG_REQ_FLAG_Q

	From	To	Count	Threshold
Bin	0	1	887	1
Bin	1	0	2488	1

Signal:

TX_TRIG_REQ_FLAG_DQ

	From	To	Count	Threshold
Bin	0	1	22772413	1
Bin	1	0	22774013	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 168:

 rx_trig_req_q = '1' and tx_trig_req = '1' 
 <-------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11391077	1
Bin	True	False	22763573	1
Bin	True	True	11382229	1

"=" expression on line 168:

rx_trig_req_q = '1'

	Evaluated to	Count	Threshold
Bin	False	34170788	1
Bin	True	34145802	1

"=" expression on line 168:

tx_trig_req = '1'

	Evaluated to	Count	Threshold
Bin	False	45543284	1
Bin	True	22773306	1

"=" expression on line 169:

rx_trig_req_q = '0'

	Evaluated to	Count	Threshold
Bin	False	22766775	1
Bin	True	34167586	1

"=" expression on line 174:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"or" expression on line 181:

 tx_trig_req or tx_trig_req_flag_q 
 <---LHS--->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	22774013	1
Bin	'0'	'1'	887	1
Bin	'1'	'0'	22772413	1

"=" expression on line 188:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 208:

rx_trig_req_q = '1'

	Evaluated to	Count	Threshold
Bin	False	34168300	1
Bin	True	34145796	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.TRIGGER_GENERATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 168 to 170:

Signal assignment statement on line 168:

Signal assignment statement on line 169:

Signal assignment statement on line 170:

If statement on lines 174 to 178:

Signal assignment statement on line 175:

Signal assignment statement on line 177:

Signal assignment statement on line 181:

If statement on lines 188 to 192:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

Signal assignment statement on line 200:

Signal assignment statement on line 201:

If statement on lines 208 to 209:

Signal assignment statement on line 208:

Signal assignment statement on line 209:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 168:

"if" / "when" / "else" condition on line 169:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 176:

"if" / "when" / "else" condition on line 188:

"if" / "when" / "else" condition on line 190:

"if" / "when" / "else" condition on line 208:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 168:

"=" expression on line 168:

"=" expression on line 168:

"=" expression on line 169:

"=" expression on line 174:

"or" expression on line 181:

"=" expression on line 188:

"=" expression on line 208:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: