NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.TRIGGER_GENERATOR_INST	100.0 % (14/14)	100.0 % (14/14)	100.0 % (22/22)	100.0 % (18/18)	N.A.	N.A.	100.0 % (68/68)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

168:    tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else 
169:                          '0' when (rx_trig_req_q = '0') else 
170:                          tx_trig_req_flag_q;

Count: 66234385
Threshold: 1

Signal assignment statement:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else
Count: 11035231
Threshold: 1

Signal assignment statement:

169: '0' when (rx_trig_req_q = '0') else
Count: 33126434
Threshold: 1

Signal assignment statement:

170: tx_trig_req_flag_q;
Count: 22072720
Threshold: 1

If statement:

174:        if (res_n = '0') then 
175:            tx_trig_req_flag_q <= '0'; 
176:        elsif (rising_edge(clk_sys)) then 
177:            tx_trig_req_flag_q <= tx_trig_req_flag_d; 
178:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

175: tx_trig_req_flag_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

177: tx_trig_req_flag_q <= tx_trig_req_flag_d;
Count: 526374300
Threshold: 1

Signal assignment statement:

181: tx_trig_req_flag_dq <= tx_trig_req or tx_trig_req_flag_q;
Count: 44163255
Threshold: 1

If statement:

188:        if (res_n = '0') then 
189:            rx_trig_req_q <= '0'; 
190:        elsif (rising_edge(clk_sys)) then 
191:            rx_trig_req_q <= rx_trig_req; 
192:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

189: rx_trig_req_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

191: rx_trig_req_q <= rx_trig_req;
Count: 526374300
Threshold: 1

If statement:

208:    tx_trigger <= '0' when (rx_trig_req_q = '1') else 
209:                  tx_trig_req_flag_dq;

Count: 66231839
Threshold: 1

Signal assignment statement:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else
Count: 33104745
Threshold: 1

Signal assignment statement:

209: tx_trig_req_flag_dq;
Count: 33127094
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else

	Evaluated to	Count	Threshold
Bin	True	11035231	1
Bin	False	55199154	1

"if" / "when" / "else" condition:

169: '0' when (rx_trig_req_q = '0') else

	Evaluated to	Count	Threshold
Bin	True	33126434	1
Bin	False	22072720	1

"if" / "when" / "else" condition:

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

176: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

188: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

190: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	33104745	1
Bin	False	33127094	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

RX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22084127	1
Bin	1	0	22085727	1

Port:

TX_TRIG_REQ

	From	To	Count	Threshold
Bin	0	1	22078288	1
Bin	1	0	22079887	1

Port:

RX_TRIGGERS(1)

	From	To	Count	Threshold
Bin	0	1	33119362	1
Bin	1	0	33122562	1

Port:

RX_TRIGGERS(0)

	From	To	Count	Threshold
Bin	0	1	22070470	1
Bin	1	0	44169854	1

Port:

TX_TRIGGER

	From	To	Count	Threshold
Bin	0	1	11044003	1
Bin	1	0	11045602	1

Signal:

RX_TRIG_REQ_Q

	From	To	Count	Threshold
Bin	0	1	11035235	1
Bin	1	0	11036835	1

Signal:

TX_TRIG_REQ_FLAG_D

	From	To	Count	Threshold
Bin	0	1	11035231	1
Bin	1	0	11036831	1

Signal:

TX_TRIG_REQ_FLAG_Q

	From	To	Count	Threshold
Bin	0	1	940	1
Bin	1	0	2540	1

Signal:

TX_TRIG_REQ_FLAG_DQ

	From	To	Count	Threshold
Bin	0	1	22078288	1
Bin	1	0	22079887	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else

	Evaluated to	Count	Threshold
Bin	False	33129634	1
Bin	True	33104751	1

"=" expression

168: tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else

	Evaluated to	Count	Threshold
Bin	False	44155151	1
Bin	True	22079234	1

"and" expression

168:    tx_trig_req_flag_d <= '1' when (rx_trig_req_q = '1' and tx_trig_req = '1') else 
                                        <-------LHS------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11044003	1
Bin	True	False	22069520	1
Bin	True	True	11035231	1

"=" expression

169: '0' when (rx_trig_req_q = '0') else

	Evaluated to	Count	Threshold
Bin	False	22072720	1
Bin	True	33126434	1

"=" expression

174: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"or" expression

181:    tx_trig_req_flag_dq <= tx_trig_req or tx_trig_req_flag_q; 
                               <---LHS--->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	22079887	1
Bin	'0'	'1'	940	1
Bin	'1'	'0'	22078288	1

"=" expression

188: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

208: tx_trigger <= '0' when (rx_trig_req_q = '1') else

	Evaluated to	Count	Threshold
Bin	False	33127094	1
Bin	True	33104745	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.TRIGGER_GENERATOR_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/trigger_generator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"and" expression

"=" expression

"=" expression

"or" expression

"=" expression

"=" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: