NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
TXT_BUFFER_RAM_INST	100.0 % (56/56)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2308/2312)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

TXT_BUFFER_RAM_INST

100.0 % (56/56)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2308/2312)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST	100.0 % (38/38)	100.0 % (24/24)	100.0 % (468/468)	100.0 % (75/75)	N.A.	N.A.	100.0 % (605/605)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

100.0 % (38/38)

100.0 % (24/24)

100.0 % (468/468)

100.0 % (75/75)

N.A.

100.0 % (605/605)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

253:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
254:                             else 
255:                         '0';

Count: 272462
Threshold: 1

Signal assignment statement on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 127757
Threshold: 1

Signal assignment statement on line 255:

255: '0';
Count: 144705
Threshold: 1

If statement on lines 266 to 268:

266:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
267:                                                   else 
268:                                    (others => '0');

Count: 117727
Threshold: 1

Signal assignment statement on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 51522
Threshold: 1

Signal assignment statement on line 268:

268: (others => '0');
Count: 66205
Threshold: 1

If statement on lines 276 to 280:

276:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
277:                           else 
278:                       '1' when (mr_tst_control_tmaena = '1') 
279:                           else 
280:                       '0';

Count: 475598
Threshold: 1

Signal assignment statement on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 234691
Threshold: 1

Signal assignment statement on line 278:

278: '1' when (mr_tst_control_tmaena = '1')
Count: 648
Threshold: 1

Signal assignment statement on line 280:

280: '0';
Count: 240259
Threshold: 1

If statement on lines 287 to 291:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID) 
290:                                     else 
291:                                 '0';

Count: 413746
Threshold: 1

Signal assignment statement on line 287:

287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 307
Threshold: 1

Signal assignment statement on line 291:

291: '0';
Count: 413439
Threshold: 1

Signal assignment statement on line 293:

293: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 3816
Threshold: 1

If statement on lines 301 to 309:

301:        if (res_n = '0') then 
302:            mr_tx_command_txce_q <= '0'; 
...
308:            mr_tx_command_txca_q <= mr_tx_command_txca; 
309:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 302:

302: mr_tx_command_txce_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 303:

303: mr_tx_command_txcr_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 304:

304: mr_tx_command_txca_q <= '0';
Count: 2424883
Threshold: 1

Signal assignment statement on line 306:

306: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 543791678
Threshold: 1

Signal assignment statement on line 307:

307: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 543791678
Threshold: 1

Signal assignment statement on line 308:

308: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 543791678
Threshold: 1

If statement on lines 312 to 314:

312:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
313:                                 else 
314:                             '0';

Count: 16765
Threshold: 1

Signal assignment statement on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 104
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 16661
Threshold: 1

If statement on lines 315 to 317:

315:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
316:                                 else 
317:                             '0';

Count: 58711
Threshold: 1

Signal assignment statement on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 11668
Threshold: 1

Signal assignment statement on line 317:

317: '0';
Count: 47043
Threshold: 1

If statement on lines 319 to 321:

319:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
320:                         else 
321:                     '0';

Count: 19525
Threshold: 1

Signal assignment statement on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 229
Threshold: 1

Signal assignment statement on line 321:

321: '0';
Count: 19296
Threshold: 1

If statement on lines 323 to 326:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1')) 
325:                        else 
326:                    '0';

Count: 46073
Threshold: 1

Signal assignment statement on line 323:

323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
Count: 44
Threshold: 1

Signal assignment statement on line 326:

326: '0';
Count: 46029
Threshold: 1

Signal assignment statement on line 328:

328: abort_or_skipped <= abort_applied or buffer_skipped;
Count: 3748
Threshold: 1

If statement on lines 333 to 335:

333:    txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') 
334:                                else 
335:                            '0';

Count: 5483
Threshold: 1

Signal assignment statement on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
Count: 151
Threshold: 1

Signal assignment statement on line 335:

335: '0';
Count: 5332
Threshold: 1

Signal assignment statement on line 423:

423: txtb_parity_mismatch <= parity_mismatch;
Count: 6658
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	127757	1
Bin	False	144705	1

"if" / "when" / "else" condition on line 266:

266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	51522	1
Bin	False	66205	1

"if" / "when" / "else" condition on line 276:

276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	234691	1
Bin	False	240907	1

"if" / "when" / "else" condition on line 278:

278: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	648	1
Bin	False	240259	1

"if" / "when" / "else" condition on lines 287 to 289:

287:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
288:                                           txtb_parity_check_valid = '1' and 
289:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	307	1
Bin	False	413439	1

"if" / "when" / "else" condition on line 301:

301: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 305:

305: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 312:

312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	104	1
Bin	False	16661	1

"if" / "when" / "else" condition on line 315:

315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	11668	1
Bin	False	47043	1

"if" / "when" / "else" condition on line 319:

319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	229	1
Bin	False	19296	1

"if" / "when" / "else" condition on lines 323 to 324:

323:    buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and 
324:                                (txtb_is_bb = '1'))

	Evaluated to	Count	Threshold
Bin	True	44	1
Bin	False	46029	1

"if" / "when" / "else" condition on line 333:

333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')

	Evaluated to	Count	Threshold
Bin	True	151	1
Bin	False	5332	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_IS_BB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	592	1
Bin	(31)	1	0	2193	1
Bin	(30)	0	1	585	1
Bin	(30)	1	0	2186	1
Bin	(29)	0	1	591	1
Bin	(29)	1	0	2192	1
Bin	(28)	0	1	622	1
Bin	(28)	1	0	2223	1
Bin	(27)	0	1	629	1
Bin	(27)	1	0	2230	1
Bin	(26)	0	1	625	1
Bin	(26)	1	0	2226	1
Bin	(25)	0	1	608	1
Bin	(25)	1	0	2209	1
Bin	(24)	0	1	649	1
Bin	(24)	1	0	2250	1
Bin	(23)	0	1	605	1
Bin	(23)	1	0	2206	1
Bin	(22)	0	1	634	1
Bin	(22)	1	0	2235	1
Bin	(21)	0	1	623	1
Bin	(21)	1	0	2224	1
Bin	(20)	0	1	616	1
Bin	(20)	1	0	2217	1
Bin	(19)	0	1	626	1
Bin	(19)	1	0	2227	1
Bin	(18)	0	1	624	1
Bin	(18)	1	0	2225	1
Bin	(17)	0	1	614	1
Bin	(17)	1	0	2215	1
Bin	(16)	0	1	588	1
Bin	(16)	1	0	2189	1
Bin	(15)	0	1	624	1
Bin	(15)	1	0	2225	1
Bin	(14)	0	1	601	1
Bin	(14)	1	0	2202	1
Bin	(13)	0	1	611	1
Bin	(13)	1	0	2212	1
Bin	(12)	0	1	613	1
Bin	(12)	1	0	2214	1
Bin	(11)	0	1	608	1
Bin	(11)	1	0	2209	1
Bin	(10)	0	1	615	1
Bin	(10)	1	0	2216	1
Bin	(9)	0	1	630	1
Bin	(9)	1	0	2231	1
Bin	(8)	0	1	595	1
Bin	(8)	1	0	2196	1
Bin	(7)	0	1	627	1
Bin	(7)	1	0	2228	1
Bin	(6)	0	1	628	1
Bin	(6)	1	0	2229	1
Bin	(5)	0	1	610	1
Bin	(5)	1	0	2211	1
Bin	(4)	0	1	614	1
Bin	(4)	1	0	2215	1
Bin	(3)	0	1	614	1
Bin	(3)	1	0	2215	1
Bin	(2)	0	1	616	1
Bin	(2)	1	0	2217	1
Bin	(1)	0	1	618	1
Bin	(1)	1	0	2219	1
Bin	(0)	0	1	608	1
Bin	(0)	1	0	2209	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	4045	1
Bin	(3)	1	0	2444	1
Bin	(2)	0	1	6518	1
Bin	(2)	1	0	8119	1
Bin	(1)	0	1	8589	1
Bin	(1)	1	0	10190	1
Bin	(0)	0	1	8485	1
Bin	(0)	1	0	10086	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	6329	1
Bin	1	0	7930	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	25275	1
Bin	LOCK	1	0	26876	1
Bin	VALID	0	1	11112	1
Bin	VALID	1	0	12713	1
Bin	ERR	0	1	4262	1
Bin	ERR	1	0	5863	1
Bin	ARBL	0	1	455	1
Bin	ARBL	1	0	2056	1
Bin	FAILED	0	1	9436	1
Bin	FAILED	1	0	11037	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	2679	1
Bin	(31)	1	0	4280	1
Bin	(30)	0	1	2814	1
Bin	(30)	1	0	4415	1
Bin	(29)	0	1	2662	1
Bin	(29)	1	0	4263	1
Bin	(28)	0	1	10028	1
Bin	(28)	1	0	11629	1
Bin	(27)	0	1	7832	1
Bin	(27)	1	0	9433	1
Bin	(26)	0	1	10275	1
Bin	(26)	1	0	11876	1
Bin	(25)	0	1	8104	1
Bin	(25)	1	0	9705	1
Bin	(24)	0	1	10289	1
Bin	(24)	1	0	11890	1
Bin	(23)	0	1	8453	1
Bin	(23)	1	0	10054	1
Bin	(22)	0	1	10317	1
Bin	(22)	1	0	11918	1
Bin	(21)	0	1	8400	1
Bin	(21)	1	0	10001	1
Bin	(20)	0	1	10346	1
Bin	(20)	1	0	11947	1
Bin	(19)	0	1	8325	1
Bin	(19)	1	0	9926	1
Bin	(18)	0	1	10201	1
Bin	(18)	1	0	11802	1
Bin	(17)	0	1	5028	1
Bin	(17)	1	0	6629	1
Bin	(16)	0	1	5213	1
Bin	(16)	1	0	6814	1
Bin	(15)	0	1	5046	1
Bin	(15)	1	0	6647	1
Bin	(14)	0	1	5148	1
Bin	(14)	1	0	6749	1
Bin	(13)	0	1	5046	1
Bin	(13)	1	0	6647	1
Bin	(12)	0	1	5013	1
Bin	(12)	1	0	6614	1
Bin	(11)	0	1	4993	1
Bin	(11)	1	0	6594	1
Bin	(10)	0	1	5925	1
Bin	(10)	1	0	7526	1
Bin	(9)	0	1	9077	1
Bin	(9)	1	0	10678	1
Bin	(8)	0	1	5439	1
Bin	(8)	1	0	7040	1
Bin	(7)	0	1	12728	1
Bin	(7)	1	0	14329	1
Bin	(6)	0	1	8332	1
Bin	(6)	1	0	9933	1
Bin	(5)	0	1	6608	1
Bin	(5)	1	0	8209	1
Bin	(4)	0	1	6110	1
Bin	(4)	1	0	7711	1
Bin	(3)	0	1	9060	1
Bin	(3)	1	0	10661	1
Bin	(2)	0	1	9527	1
Bin	(2)	1	0	11128	1
Bin	(1)	0	1	9835	1
Bin	(1)	1	0	11436	1
Bin	(0)	0	1	13909	1
Bin	(0)	1	0	15510	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	8628	1
Bin	1	0	10229	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	6573	1
Bin	1	0	8174	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1728	1
Bin	1	0	3329	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	307	1
Bin	1	0	1908	1

Port:

TXTB_BB_PARITY_ERROR

	From	To	Count	Threshold
Bin	0	1	151	1
Bin	1	0	1752	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	8174	1
Bin	1	0	6573	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	6573	1
Bin	1	0	8174	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	5571	1
Bin	(31)	1	0	7122	1
Bin	(30)	0	1	5866	1
Bin	(30)	1	0	7417	1
Bin	(29)	0	1	5604	1
Bin	(29)	1	0	7155	1
Bin	(28)	0	1	17418	1
Bin	(28)	1	0	18925	1
Bin	(27)	0	1	14252	1
Bin	(27)	1	0	15766	1
Bin	(26)	0	1	17436	1
Bin	(26)	1	0	18947	1
Bin	(25)	0	1	14725	1
Bin	(25)	1	0	16231	1
Bin	(24)	0	1	17826	1
Bin	(24)	1	0	19337	1
Bin	(23)	0	1	15159	1
Bin	(23)	1	0	16669	1
Bin	(22)	0	1	17818	1
Bin	(22)	1	0	19320	1
Bin	(21)	0	1	15780	1
Bin	(21)	1	0	17278	1
Bin	(20)	0	1	17859	1
Bin	(20)	1	0	19373	1
Bin	(19)	0	1	15423	1
Bin	(19)	1	0	16918	1
Bin	(18)	0	1	17682	1
Bin	(18)	1	0	19183	1
Bin	(17)	0	1	9919	1
Bin	(17)	1	0	11447	1
Bin	(16)	0	1	9985	1
Bin	(16)	1	0	11519	1
Bin	(15)	0	1	9994	1
Bin	(15)	1	0	11529	1
Bin	(14)	0	1	10030	1
Bin	(14)	1	0	11564	1
Bin	(13)	0	1	9871	1
Bin	(13)	1	0	11406	1
Bin	(12)	0	1	9958	1
Bin	(12)	1	0	11493	1
Bin	(11)	0	1	9864	1
Bin	(11)	1	0	11403	1
Bin	(10)	0	1	11597	1
Bin	(10)	1	0	13059	1
Bin	(9)	0	1	19126	1
Bin	(9)	1	0	20535	1
Bin	(8)	0	1	10644	1
Bin	(8)	1	0	12178	1
Bin	(7)	0	1	24560	1
Bin	(7)	1	0	25796	1
Bin	(6)	0	1	16021	1
Bin	(6)	1	0	17439	1
Bin	(5)	0	1	13278	1
Bin	(5)	1	0	14805	1
Bin	(4)	0	1	12313	1
Bin	(4)	1	0	13845	1
Bin	(3)	0	1	19273	1
Bin	(3)	1	0	20731	1
Bin	(2)	0	1	20220	1
Bin	(2)	1	0	21656	1
Bin	(1)	0	1	20404	1
Bin	(1)	1	0	21848	1
Bin	(0)	0	1	27232	1
Bin	(0)	1	0	28510	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	307	1
Bin	1	0	1908	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	354	1
Bin	1	0	1955	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	21327	1
Bin	1	0	22928	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1734	1
Bin	1	0	3335	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1705	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	11668	1
Bin	1	0	13269	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	1830	1

Signal:

BUFFER_SKIPPED

	From	To	Count	Threshold
Bin	0	1	44	1
Bin	1	0	1645	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	273	1
Bin	1	0	1874	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	127757	1
Bin	1	0	129358	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	233855	1
Bin	1	0	235456	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	15240058	1
Bin	1	0	15241659	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1728	1
Bin	1	0	3329	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 253:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	135931	1
Bin	True	False	300	1
Bin	True	True	127757	1

"=" expression on line 253:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	144405	1
Bin	True	128057	1

"=" expression on line 253:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	8774	1
Bin	True	263688	1

"=" expression on line 266:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	66205	1
Bin	True	51522	1

"or" expression on line 276:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	240907	1
Bin	False	True	127113	1
Bin	True	False	106836	1

"=" expression on line 276:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	368020	1
Bin	True	107578	1

"=" expression on line 276:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	347743	1
Bin	True	127855	1

"=" expression on line 278:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	240259	1
Bin	True	648	1

"and" expression on lines 287 to 289:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	145393	1
Bin	True	False	1624	1
Bin	True	True	307	1

"and" expression on lines 287 to 288:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	183473	1
Bin	True	False	2053	1
Bin	True	True	1931	1

"=" expression on line 287:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	409762	1
Bin	True	3984	1

"=" expression on line 288:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	228342	1
Bin	True	185404	1

"=" expression on line 289:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	268046	1
Bin	True	145700	1

"=" expression on line 301:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"and" expression on line 312:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	5712	1
Bin	True	False	269	1
Bin	True	True	104	1

"=" expression on line 312:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	16392	1
Bin	True	373	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	10949	1
Bin	True	5816	1

"and" expression on line 315:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	6568	1
Bin	True	False	20386	1
Bin	True	True	11668	1

"=" expression on line 315:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	26657	1
Bin	True	32054	1

"=" expression on line 315:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	40475	1
Bin	True	18236	1

"and" expression on line 319:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	5851	1
Bin	True	False	1510	1
Bin	True	True	229	1

"=" expression on line 319:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	17786	1
Bin	True	1739	1

"=" expression on line 319:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	13445	1
Bin	True	6080	1

"and" expression on lines 323 to 324:

 (txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and (txtb_is_bb = '1') 
  <-----------------------LHS----------------------->       <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	131	1
Bin	True	False	20504	1
Bin	True	True	44	1

"or" expression on line 323:

 txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	25525	1
Bin	False	True	11112	1
Bin	True	False	9436	1

"=" expression on line 323:

txtb_hw_cmd.failed = '1'

	Evaluated to	Count	Threshold
Bin	False	36637	1
Bin	True	9436	1

"=" expression on line 323:

txtb_hw_cmd.valid = '1'

	Evaluated to	Count	Threshold
Bin	False	34961	1
Bin	True	11112	1

"=" expression on line 324:

txtb_is_bb = '1'

	Evaluated to	Count	Threshold
Bin	False	45898	1
Bin	True	175	1

"or" expression on line 328:

 abort_applied or buffer_skipped 
 <----LHS---->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	1874	1
Bin	'0'	'1'	44	1
Bin	'1'	'0'	229	1

"and" expression on line 333:

 txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1' 
 <-------------LHS------------->     <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	184	1
Bin	True	False	156	1
Bin	True	True	151	1

"=" expression on line 333:

txtb_parity_error_valid_i = '1'

	Evaluated to	Count	Threshold
Bin	False	5176	1
Bin	True	307	1

"=" expression on line 333:

mr_mode_txbbm = '1'

	Evaluated to	Count	Threshold
Bin	False	5148	1
Bin	True	335	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 253 to 255:

Signal assignment statement on line 253:

Signal assignment statement on line 255:

If statement on lines 266 to 268:

Signal assignment statement on line 266:

Signal assignment statement on line 268:

If statement on lines 276 to 280:

Signal assignment statement on line 276:

Signal assignment statement on line 278:

Signal assignment statement on line 280:

If statement on lines 287 to 291:

Signal assignment statement on line 287:

Signal assignment statement on line 291:

Signal assignment statement on line 293:

If statement on lines 301 to 309:

Signal assignment statement on line 302:

Signal assignment statement on line 303:

Signal assignment statement on line 304:

Signal assignment statement on line 306:

Signal assignment statement on line 307:

Signal assignment statement on line 308:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

If statement on lines 315 to 317:

Signal assignment statement on line 315:

Signal assignment statement on line 317:

If statement on lines 319 to 321:

Signal assignment statement on line 319:

Signal assignment statement on line 321:

If statement on lines 323 to 326:

Signal assignment statement on line 323:

Signal assignment statement on line 326:

Signal assignment statement on line 328:

If statement on lines 333 to 335:

Signal assignment statement on line 333:

Signal assignment statement on line 335:

Signal assignment statement on line 423:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 253:

"if" / "when" / "else" condition on line 266:

"if" / "when" / "else" condition on line 276:

"if" / "when" / "else" condition on line 278:

"if" / "when" / "else" condition on lines 287 to 289:

"if" / "when" / "else" condition on line 301:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 312:

"if" / "when" / "else" condition on line 315:

"if" / "when" / "else" condition on line 319:

"if" / "when" / "else" condition on lines 323 to 324:

"if" / "when" / "else" condition on line 333:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

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