Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| CLK_GATE_TXT_BUFFER_RAM_COMP |
100.0 % (4/4) |
100.0 % (2/2) |
100.0 % (10/10) |
100.0 % (8/8) |
N.A. |
N.A. |
100.0 % (24/24) |
| TXT_BUFFER_RAM_INST |
100.0 % (55/55) |
100.0 % (38/38) |
100.0 % (2160/2160) |
100.0 % (62/62) |
N.A. |
N.A. |
100.0 % (2315/2315) |
| TXT_BUFFER_FSM_INST |
100.0 % (79/79) |
100.0 % (94/94) |
100.0 % (70/70) |
100.0 % (151/151) |
100.0 % (16/16) |
N.A. |
100.0 % (410/410) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
254: else
255: '0'; Count: 271516
Threshold: 1
Signal assignment statement:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') Count: 127349
Threshold: 1
Signal assignment statement:
255: '0'; Count: 144167
Threshold: 1
If statement:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
267: else
268: (others => '0'); Count: 117253
Threshold: 1
Signal assignment statement:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') Count: 51078
Threshold: 1
Signal assignment statement:
268: (others => '0'); Count: 66175
Threshold: 1
If statement:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
277: else
278: '1' when (mr_tst_control_tmaena = '1')
279: else
280: '0'; Count: 472166
Threshold: 1
Signal assignment statement:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') Count: 233007
Threshold: 1
Signal assignment statement:
278: '1' when (mr_tst_control_tmaena = '1') Count: 648
Threshold: 1
Signal assignment statement:
280: '0'; Count: 238511
Threshold: 1
If statement:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID)
290: else
291: '0'; Count: 407732
Threshold: 1
Signal assignment statement:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and Count: 331
Threshold: 1
Signal assignment statement:
291: '0'; Count: 407401
Threshold: 1
If statement:
301: if (res_n = '0') then
302: mr_tx_command_txce_q <= '0';
...
308: mr_tx_command_txca_q <= mr_tx_command_txca;
309: end if; Count: 1055177083
Threshold: 1
Signal assignment statement:
302: mr_tx_command_txce_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
303: mr_tx_command_txcr_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
304: mr_tx_command_txca_q <= '0'; Count: 2418499
Threshold: 1
Signal assignment statement:
306: mr_tx_command_txce_q <= mr_tx_command_txce; Count: 526374300
Threshold: 1
Signal assignment statement:
307: mr_tx_command_txcr_q <= mr_tx_command_txcr; Count: 526374300
Threshold: 1
Signal assignment statement:
308: mr_tx_command_txca_q <= mr_tx_command_txca; Count: 526374300
Threshold: 1
If statement:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
313: else
314: '0'; Count: 16762
Threshold: 1
Signal assignment statement:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') Count: 104
Threshold: 1
Signal assignment statement:
314: '0'; Count: 16658
Threshold: 1
If statement:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
316: else
317: '0'; Count: 57820
Threshold: 1
Signal assignment statement:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') Count: 11608
Threshold: 1
Signal assignment statement:
317: '0'; Count: 46212
Threshold: 1
If statement:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
320: else
321: '0'; Count: 19522
Threshold: 1
Signal assignment statement:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') Count: 229
Threshold: 1
Signal assignment statement:
321: '0'; Count: 19293
Threshold: 1
If statement:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1'))
325: else
326: '0'; Count: 45200
Threshold: 1
Signal assignment statement:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and Count: 43
Threshold: 1
Signal assignment statement:
326: '0'; Count: 45157
Threshold: 1
Signal assignment statement:
328: abort_or_skipped <= abort_applied or buffer_skipped; Count: 3744
Threshold: 1
If statement:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
334: else
335: '0'; Count: 5528
Threshold: 1
Signal assignment statement:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') Count: 147
Threshold: 1
Signal assignment statement:
335: '0'; Count: 5381
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 127349 | 1 |
| Bin | False | 144167 | 1 |
"if" / "when" / "else" condition:
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 51078 | 1 |
| Bin | False | 66175 | 1 |
"if" / "when" / "else" condition:
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 233007 | 1 |
| Bin | False | 239159 | 1 |
"if" / "when" / "else" condition:
278: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 648 | 1 |
| Bin | False | 238511 | 1 |
"if" / "when" / "else" condition:
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 331 | 1 |
| Bin | False | 407401 | 1 |
"if" / "when" / "else" condition:
301: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 2418499 | 1 |
| Bin | False | 1052758584 | 1 |
"if" / "when" / "else" condition:
305: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 526374300 | 1 |
| Bin | False | 526384284 | 1 |
"if" / "when" / "else" condition:
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 104 | 1 |
| Bin | False | 16658 | 1 |
"if" / "when" / "else" condition:
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 11608 | 1 |
| Bin | False | 46212 | 1 |
"if" / "when" / "else" condition:
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 229 | 1 |
| Bin | False | 19293 | 1 |
"if" / "when" / "else" condition:
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1')) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 43 | 1 |
| Bin | False | 45157 | 1 |
"if" / "when" / "else" condition:
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 147 | 1 |
| Bin | False | 5381 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8082 | 1 |
| Bin | 1 | 0 | 8072 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5 | 1 |
| Bin | 1 | 0 | 1605 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15 | 1 |
| Bin | 1 | 0 | 1615 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
MR_MODE_TXBBM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33 | 1 |
| Bin | 1 | 0 | 1633 | 1 |
Port:
MR_SETTINGS_TBFBO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2533 | 1 |
| Bin | 1 | 0 | 943 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 1714 | 1 |
Port:
MR_TX_COMMAND_TXCE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXCR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20943 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXCA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 24631 | 1 |
Port:
MR_TX_COMMAND_TXBI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5627 | 1 |
| Bin | 1 | 0 | 7227 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 648 | 1 |
| Bin | 1 | 0 | 2248 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32309 | 1 |
| Bin | 1 | 0 | 35200 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3617 | 1 |
| Bin | 1 | 0 | 5217 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5031 | 1 |
| Bin | 1 | 0 | 6631 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10323 | 1 |
| Bin | 1 | 0 | 11923 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22448 | 1 |
| Bin | 1 | 0 | 24048 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44884 | 1 |
| Bin | 1 | 0 | 46484 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 235 | 1 |
| Bin | 1 | 0 | 1835 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 374 | 1 |
| Bin | 1 | 0 | 1974 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 2114 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 979 | 1 |
| Bin | 1 | 0 | 2579 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1535 | 1 |
| Bin | 1 | 0 | 3135 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1484 | 1 |
| Bin | 1 | 0 | 3084 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1491 | 1 |
| Bin | 1 | 0 | 3091 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1631 | 1 |
| Bin | 1 | 0 | 3231 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1645 | 1 |
| Bin | 1 | 0 | 3245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 3229 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1641 | 1 |
| Bin | 1 | 0 | 3241 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1713 | 1 |
| Bin | 1 | 0 | 3313 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1587 | 1 |
| Bin | 1 | 0 | 3187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1526 | 1 |
| Bin | 1 | 0 | 3126 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1560 | 1 |
| Bin | 1 | 0 | 3160 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1658 | 1 |
| Bin | 1 | 0 | 3258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1636 | 1 |
| Bin | 1 | 0 | 3236 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1632 | 1 |
| Bin | 1 | 0 | 3232 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1670 | 1 |
| Bin | 1 | 0 | 3270 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1575 | 1 |
| Bin | 1 | 0 | 3175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1501 | 1 |
| Bin | 1 | 0 | 3101 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1559 | 1 |
| Bin | 1 | 0 | 3159 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1646 | 1 |
| Bin | 1 | 0 | 3246 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1672 | 1 |
| Bin | 1 | 0 | 3272 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1681 | 1 |
| Bin | 1 | 0 | 3281 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1633 | 1 |
| Bin | 1 | 0 | 3233 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1567 | 1 |
| Bin | 1 | 0 | 3167 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1601 | 1 |
| Bin | 1 | 0 | 3201 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1637 | 1 |
| Bin | 1 | 0 | 3237 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1640 | 1 |
| Bin | 1 | 0 | 3240 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1655 | 1 |
| Bin | 1 | 0 | 3255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1656 | 1 |
| Bin | 1 | 0 | 3256 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1722 | 1 |
| Bin | 1 | 0 | 3322 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609 | 1 |
| Bin | 1 | 0 | 2209 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 594 | 1 |
| Bin | 1 | 0 | 2194 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 580 | 1 |
| Bin | 1 | 0 | 2180 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 629 | 1 |
| Bin | 1 | 0 | 2229 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 2232 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 616 | 1 |
| Bin | 1 | 0 | 2216 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 642 | 1 |
| Bin | 1 | 0 | 2242 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 635 | 1 |
| Bin | 1 | 0 | 2235 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 623 | 1 |
| Bin | 1 | 0 | 2223 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 621 | 1 |
| Bin | 1 | 0 | 2221 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 609 | 1 |
| Bin | 1 | 0 | 2209 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 631 | 1 |
| Bin | 1 | 0 | 2231 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 613 | 1 |
| Bin | 1 | 0 | 2213 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 634 | 1 |
| Bin | 1 | 0 | 2234 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 589 | 1 |
| Bin | 1 | 0 | 2189 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 613 | 1 |
| Bin | 1 | 0 | 2213 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 602 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 626 | 1 |
| Bin | 1 | 0 | 2226 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 612 | 1 |
| Bin | 1 | 0 | 2212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 601 | 1 |
| Bin | 1 | 0 | 2201 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 632 | 1 |
| Bin | 1 | 0 | 2232 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 620 | 1 |
| Bin | 1 | 0 | 2220 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 618 | 1 |
| Bin | 1 | 0 | 2218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 605 | 1 |
| Bin | 1 | 0 | 2205 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617 | 1 |
| Bin | 1 | 0 | 2217 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 611 | 1 |
| Bin | 1 | 0 | 2211 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 630 | 1 |
| Bin | 1 | 0 | 2230 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 617 | 1 |
| Bin | 1 | 0 | 2217 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61362 | 1 |
| Bin | 1 | 0 | 1030083 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 67108 | 1 |
| Bin | 1 | 0 | 1024337 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 63097 | 1 |
| Bin | 1 | 0 | 1028348 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91439 | 1 |
| Bin | 1 | 0 | 1000006 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79643 | 1 |
| Bin | 1 | 0 | 1011802 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76527 | 1 |
| Bin | 1 | 0 | 1014918 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 88276 | 1 |
| Bin | 1 | 0 | 1003169 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 78188 | 1 |
| Bin | 1 | 0 | 1013257 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 70931 | 1 |
| Bin | 1 | 0 | 1020514 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108138 | 1 |
| Bin | 1 | 0 | 983307 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 74867 | 1 |
| Bin | 1 | 0 | 1016578 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80468 | 1 |
| Bin | 1 | 0 | 1010977 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110009 | 1 |
| Bin | 1 | 0 | 981436 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 131558 | 1 |
| Bin | 1 | 0 | 959887 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123951 | 1 |
| Bin | 1 | 0 | 967494 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 193513 | 1 |
| Bin | 1 | 0 | 897932 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 72382 | 1 |
| Bin | 1 | 0 | 1019063 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 86120 | 1 |
| Bin | 1 | 0 | 1005325 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 76572 | 1 |
| Bin | 1 | 0 | 1014873 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80428 | 1 |
| Bin | 1 | 0 | 1011017 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 97296 | 1 |
| Bin | 1 | 0 | 994149 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116973 | 1 |
| Bin | 1 | 0 | 974472 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 170870 | 1 |
| Bin | 1 | 0 | 920575 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 150526 | 1 |
| Bin | 1 | 0 | 940919 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 126416 | 1 |
| Bin | 1 | 0 | 965029 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109550 | 1 |
| Bin | 1 | 0 | 981895 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 103929 | 1 |
| Bin | 1 | 0 | 987516 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162358 | 1 |
| Bin | 1 | 0 | 929087 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135873 | 1 |
| Bin | 1 | 0 | 955572 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 159944 | 1 |
| Bin | 1 | 0 | 931501 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 236123 | 1 |
| Bin | 1 | 0 | 855322 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 198401 | 1 |
| Bin | 1 | 0 | 893044 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 150105 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 328560 | 1 |
| Bin | 1 | 0 | 27467073 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576099 | 1 |
| Bin | 1 | 0 | 27219534 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 436079 | 1 |
| Bin | 1 | 0 | 27359554 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27015237 | 1 |
| Bin | 1 | 0 | 780396 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17655249 | 1 |
| Bin | 1 | 0 | 10140384 | 1 |
Port:
TXTB_PORT_A_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 127649 | 1 |
| Bin | 1 | 0 | 129249 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758245 | 1 |
| Bin | 1 | 0 | 35788 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27758627 | 1 |
| Bin | 1 | 0 | 35406 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27658880 | 1 |
| Bin | 1 | 0 | 135153 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27660120 | 1 |
| Bin | 1 | 0 | 133913 | 1 |
Port:
TXTB_STATE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4053 | 1 |
| Bin | 1 | 0 | 2453 | 1 |
Port:
TXTB_STATE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6449 | 1 |
| Bin | 1 | 0 | 8049 | 1 |
Port:
TXTB_STATE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8525 | 1 |
| Bin | 1 | 0 | 10125 | 1 |
Port:
TXTB_STATE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8417 | 1 |
| Bin | 1 | 0 | 10017 | 1 |
Port:
TXTB_IS_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 87 | 1 |
| Bin | 1 | 0 | 1687 | 1 |
Port:
TXTB_HW_CMD_INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6270 | 1 |
| Bin | 1 | 0 | 7870 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24816 | 1 |
| Bin | 1 | 0 | 26416 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4237 | 1 |
| Bin | 1 | 0 | 5837 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 455 | 1 |
| Bin | 1 | 0 | 2055 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9015 | 1 |
| Bin | 1 | 0 | 10615 | 1 |
Port:
TXTB_HW_CMD_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5600 | 1 |
| Bin | 1 | 0 | 7200 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2720 | 1 |
| Bin | 1 | 0 | 4320 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2873 | 1 |
| Bin | 1 | 0 | 4473 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2795 | 1 |
| Bin | 1 | 0 | 4395 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10078 | 1 |
| Bin | 1 | 0 | 11678 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7659 | 1 |
| Bin | 1 | 0 | 9259 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10207 | 1 |
| Bin | 1 | 0 | 11807 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7772 | 1 |
| Bin | 1 | 0 | 9372 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10265 | 1 |
| Bin | 1 | 0 | 11865 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8326 | 1 |
| Bin | 1 | 0 | 9926 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10376 | 1 |
| Bin | 1 | 0 | 11976 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8121 | 1 |
| Bin | 1 | 0 | 9721 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10361 | 1 |
| Bin | 1 | 0 | 11961 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8189 | 1 |
| Bin | 1 | 0 | 9789 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10466 | 1 |
| Bin | 1 | 0 | 12066 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4987 | 1 |
| Bin | 1 | 0 | 6587 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5177 | 1 |
| Bin | 1 | 0 | 6777 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5133 | 1 |
| Bin | 1 | 0 | 6733 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5182 | 1 |
| Bin | 1 | 0 | 6782 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4973 | 1 |
| Bin | 1 | 0 | 6573 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5173 | 1 |
| Bin | 1 | 0 | 6773 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5012 | 1 |
| Bin | 1 | 0 | 6612 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5760 | 1 |
| Bin | 1 | 0 | 7360 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9193 | 1 |
| Bin | 1 | 0 | 10793 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5608 | 1 |
| Bin | 1 | 0 | 7208 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12569 | 1 |
| Bin | 1 | 0 | 14169 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8294 | 1 |
| Bin | 1 | 0 | 9894 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6458 | 1 |
| Bin | 1 | 0 | 8058 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6051 | 1 |
| Bin | 1 | 0 | 7651 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8920 | 1 |
| Bin | 1 | 0 | 10520 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9695 | 1 |
| Bin | 1 | 0 | 11295 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9732 | 1 |
| Bin | 1 | 0 | 11332 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13690 | 1 |
| Bin | 1 | 0 | 15290 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26805 | 1 |
| Bin | 1 | 0 | 28405 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3865 | 1 |
| Bin | 1 | 0 | 5465 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45730 | 1 |
| Bin | 1 | 0 | 47330 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37881 | 1 |
| Bin | 1 | 0 | 37884 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101251 | 1 |
| Bin | 1 | 0 | 102848 | 1 |
Port:
TXTB_PORT_B_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104886 | 1 |
| Bin | 1 | 0 | 106486 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8227 | 1 |
| Bin | 1 | 0 | 8236 | 1 |
Port:
TXTB_AVAILABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8560 | 1 |
| Bin | 1 | 0 | 10160 | 1 |
Port:
TXTB_ALLOW_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6509 | 1 |
| Bin | 1 | 0 | 8109 | 1 |
Port:
TXTB_PARITY_CHECK_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 181146 | 1 |
| Bin | 1 | 0 | 182746 | 1 |
Port:
TXTB_PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1822 | 1 |
| Bin | 1 | 0 | 3422 | 1 |
Port:
TXTB_PARITY_ERROR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 331 | 1 |
| Bin | 1 | 0 | 1931 | 1 |
Port:
TXTB_BB_PARITY_ERROR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 147 | 1 |
| Bin | 1 | 0 | 1747 | 1 |
Signal:
TXTB_USER_ACCESSIBLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8109 | 1 |
| Bin | 1 | 0 | 6509 | 1 |
Signal:
TXTB_UNMASK_DATA_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6509 | 1 |
| Bin | 1 | 0 | 8109 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5911 | 1 |
| Bin | 1 | 0 | 7461 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6110 | 1 |
| Bin | 1 | 0 | 7660 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5834 | 1 |
| Bin | 1 | 0 | 7384 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17432 | 1 |
| Bin | 1 | 0 | 18943 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13971 | 1 |
| Bin | 1 | 0 | 15477 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17362 | 1 |
| Bin | 1 | 0 | 18871 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14054 | 1 |
| Bin | 1 | 0 | 15563 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17509 | 1 |
| Bin | 1 | 0 | 19012 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15147 | 1 |
| Bin | 1 | 0 | 16651 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18083 | 1 |
| Bin | 1 | 0 | 19582 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15194 | 1 |
| Bin | 1 | 0 | 16701 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17639 | 1 |
| Bin | 1 | 0 | 19138 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15448 | 1 |
| Bin | 1 | 0 | 16941 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18091 | 1 |
| Bin | 1 | 0 | 19592 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9683 | 1 |
| Bin | 1 | 0 | 11211 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10009 | 1 |
| Bin | 1 | 0 | 11537 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9772 | 1 |
| Bin | 1 | 0 | 11302 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10207 | 1 |
| Bin | 1 | 0 | 11734 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9974 | 1 |
| Bin | 1 | 0 | 11508 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10274 | 1 |
| Bin | 1 | 0 | 11806 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9752 | 1 |
| Bin | 1 | 0 | 11286 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10975 | 1 |
| Bin | 1 | 0 | 12443 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19591 | 1 |
| Bin | 1 | 0 | 21006 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10936 | 1 |
| Bin | 1 | 0 | 12467 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25055 | 1 |
| Bin | 1 | 0 | 26299 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15897 | 1 |
| Bin | 1 | 0 | 17314 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12775 | 1 |
| Bin | 1 | 0 | 14291 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11644 | 1 |
| Bin | 1 | 0 | 13169 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19107 | 1 |
| Bin | 1 | 0 | 20566 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20639 | 1 |
| Bin | 1 | 0 | 22069 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20586 | 1 |
| Bin | 1 | 0 | 22025 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26883 | 1 |
| Bin | 1 | 0 | 28179 | 1 |
Signal:
TXTB_PARITY_ERROR_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 331 | 1 |
| Bin | 1 | 0 | 1931 | 1 |
Signal:
MR_TX_COMMAND_TXCE_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 354 | 1 |
| Bin | 1 | 0 | 1954 | 1 |
Signal:
MR_TX_COMMAND_TXCR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20883 | 1 |
| Bin | 1 | 0 | 22483 | 1 |
Signal:
MR_TX_COMMAND_TXCA_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1734 | 1 |
| Bin | 1 | 0 | 3334 | 1 |
Signal:
TX_COMMAND_TXCE_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 104 | 1 |
| Bin | 1 | 0 | 1704 | 1 |
Signal:
TX_COMMAND_TXCR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11608 | 1 |
| Bin | 1 | 0 | 13208 | 1 |
Signal:
ABORT_APPLIED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 229 | 1 |
| Bin | 1 | 0 | 1829 | 1 |
Signal:
BUFFER_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 43 | 1 |
| Bin | 1 | 0 | 1643 | 1 |
Signal:
ABORT_OR_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 272 | 1 |
| Bin | 1 | 0 | 1872 | 1 |
Signal:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 127349 | 1 |
| Bin | 1 | 0 | 128949 | 1 |
Signal:
TXTB_RAM_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 232111 | 1 |
| Bin | 1 | 0 | 233711 | 1 |
Signal:
CLK_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14022469 | 1 |
| Bin | 1 | 0 | 14024069 | 1 |
Signal:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1822 | 1 |
| Bin | 1 | 0 | 3422 | 1 |
Covered expressions:
"=" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 143867 | 1 |
| Bin | True | 127649 | 1 |
"=" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 8709 | 1 |
| Bin | True | 262807 | 1 |
"and" expression
253: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
<-------LHS--------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 135458 | 1 |
| Bin | True | False | 300 | 1 |
| Bin | True | True | 127349 | 1 |
"=" expression
266: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 66175 | 1 |
| Bin | True | 51078 | 1 |
"=" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 365825 | 1 |
| Bin | True | 106341 | 1 |
"=" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 344728 | 1 |
| Bin | True | 127438 | 1 |
"or" expression
276: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 239159 | 1 |
| Bin | False | True | 126666 | 1 |
| Bin | True | False | 105569 | 1 |
"=" expression
278: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 238511 | 1 |
| Bin | True | 648 | 1 |
"=" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 403604 | 1 |
| Bin | True | 4128 | 1 |
"=" expression
288: txtb_parity_check_valid = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 224744 | 1 |
| Bin | True | 182988 | 1 |
"and" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 180905 | 1 |
| Bin | True | False | 2045 | 1 |
| Bin | True | True | 2083 | 1 |
"=" expression
289: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 262768 | 1 |
| Bin | True | 144964 | 1 |
"and" expression
287: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
288: txtb_parity_check_valid = '1' and
289: txtb_index_muxed = G_ID) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 144633 | 1 |
| Bin | True | False | 1752 | 1 |
| Bin | True | True | 331 | 1 |
"=" expression
301: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1052758584 | 1 |
| Bin | True | 2418499 | 1 |
"=" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 16389 | 1 |
| Bin | True | 373 | 1 |
"=" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 10946 | 1 |
| Bin | True | 5816 | 1 |
"and" expression
312: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 5712 | 1 |
| Bin | True | False | 269 | 1 |
| Bin | True | True | 104 | 1 |
"=" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 26201 | 1 |
| Bin | True | 31619 | 1 |
"=" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 39713 | 1 |
| Bin | True | 18107 | 1 |
"and" expression
315: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 6499 | 1 |
| Bin | True | False | 20011 | 1 |
| Bin | True | True | 11608 | 1 |
"=" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 17783 | 1 |
| Bin | True | 1739 | 1 |
"=" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 13442 | 1 |
| Bin | True | 6080 | 1 |
"and" expression
319: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 5851 | 1 |
| Bin | True | False | 1510 | 1 |
| Bin | True | True | 229 | 1 |
"=" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 36185 | 1 |
| Bin | True | 9015 | 1 |
"=" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 34102 | 1 |
| Bin | True | 11098 | 1 |
"or" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 25087 | 1 |
| Bin | False | True | 11098 | 1 |
| Bin | True | False | 9015 | 1 |
"=" expression
324: (txtb_is_bb = '1')) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 45027 | 1 |
| Bin | True | 173 | 1 |
"and" expression
323: buffer_skipped <= '1' when ((txtb_hw_cmd.failed = '1' or txtb_hw_cmd.valid = '1') and
324: (txtb_is_bb = '1')) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 130 | 1 |
| Bin | True | False | 20070 | 1 |
| Bin | True | True | 43 | 1 |
"or" expression
328: abort_or_skipped <= abort_applied or buffer_skipped;
<----LHS----> <----RHS-----> | LHS | RHS | Count | Threshold |
|---|
| Bin | '0' | '0' | 1872 | 1 |
| Bin | '0' | '1' | 43 | 1 |
| Bin | '1' | '0' | 229 | 1 |
"=" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5197 | 1 |
| Bin | True | 331 | 1 |
"=" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5201 | 1 |
| Bin | True | 327 | 1 |
"and" expression
333: txtb_bb_parity_error <= '1' when (txtb_parity_error_valid_i = '1' and mr_mode_txbbm = '1')
<-------------LHS-------------> <-------RHS-------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 180 | 1 |
| Bin | True | False | 184 | 1 |
| Bin | True | True | 147 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: