NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.SYNC_READ_GEN

File:  /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram_be.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_RAM_INST.DP_INF_RAM_BE_INST.SYNC_READ_GEN 100.0 % (2/2) 100.0 % (2/2) N.A. N.A. N.A. N.A. 100.0 % (4/4)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

197:            if (rising_edge(clk_sys)) then 
198:                data_out <= int_read_data; 
199:            end if; 
Count: 28097824
Threshold: 1

Signal assignment statement:

198:                data_out <= int_read_data; 
Count: 14047312
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

197:            if (rising_edge(clk_sys)) then 
Evaluated toCountThreshold
BinTrue140473121
BinFalse140505121

Uncovered toggles:

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Covered toggles:

Uncovered expressions:

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Covered expressions:

Uncovered FSM states:

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Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: