NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_FSM_INST	100.0 % (46/46)	100.0 % (38/38)	100.0 % (100/100)	100.0 % (33/33)	100.0 % (6/6)	N.A.	100.0 % (223/223)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

169:    tx_err_ctr_mt_erp <= '1' when (unsigned(tx_err_ctr) >= unsigned(mr_erp_erp_limit)) 
170:                             else 
171:                         '0';

Count: 32696
Threshold: 1

Signal assignment statement:

169: tx_err_ctr_mt_erp <= '1' when (unsigned(tx_err_ctr) >= unsigned(mr_erp_erp_limit))
Count: 2043
Threshold: 1

Signal assignment statement:

171: '0';
Count: 30653
Threshold: 1

If statement:

174:    rx_err_ctr_mt_erp <= '1' when (unsigned(rx_err_ctr) >= unsigned(mr_erp_erp_limit)) 
175:                             else 
176:                         '0';

Count: 27415
Threshold: 1

Signal assignment statement:

174: rx_err_ctr_mt_erp <= '1' when (unsigned(rx_err_ctr) >= unsigned(mr_erp_erp_limit))
Count: 8884
Threshold: 1

Signal assignment statement:

176: '0';
Count: 18531
Threshold: 1

If statement:

179:    tx_err_ctr_mt_255 <= '1' when (unsigned(tx_err_ctr) > 255) 
180:                             else 
181:                         '0';

Count: 32526
Threshold: 1

Signal assignment statement:

179: tx_err_ctr_mt_255 <= '1' when (unsigned(tx_err_ctr) > 255)
Count: 249
Threshold: 1

Signal assignment statement:

181: '0';
Count: 32277
Threshold: 1

If statement:

184:    tx_err_ctr_mt_ewl <= '1' when (unsigned(tx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit))) 
185:                             else 
186:                         '0';

Count: 32694
Threshold: 1

Signal assignment statement:

184: tx_err_ctr_mt_ewl <= '1' when (unsigned(tx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))
Count: 2629
Threshold: 1

Signal assignment statement:

186: '0';
Count: 30065
Threshold: 1

If statement:

189:    rx_err_ctr_mt_ewl <= '1' when (unsigned(rx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit))) 
190:                             else 
191:                         '0';

Count: 27413
Threshold: 1

Signal assignment statement:

189: rx_err_ctr_mt_ewl <= '1' when (unsigned(rx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))
Count: 9290
Threshold: 1

Signal assignment statement:

191: '0';
Count: 18123
Threshold: 1

If statement:

193:    err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1') 
194:                               else 
195:                           '0';

Count: 5193
Threshold: 1

Signal assignment statement:

193: err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1')
Count: 1202
Threshold: 1

Signal assignment statement:

195: '0';
Count: 3991
Threshold: 1

If statement:

202:        if (res_n = '0') then 
203:            err_warning_limit_q <= '0'; 
204:        elsif (rising_edge(clk_sys)) then 
205:            err_warning_limit_q <= err_warning_limit_d; 
206:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

203: err_warning_limit_q <= '0';
Count: 2418499
Threshold: 1

Signal assignment statement:

205: err_warning_limit_q <= err_warning_limit_d;
Count: 526374300
Threshold: 1

If statement:

209:    err_warning_limit_pulse <= '1' when (err_warning_limit_d /= err_warning_limit_q) 
210:                                   else 
211:                               '0';

Count: 7966
Threshold: 1

Signal assignment statement:

209: err_warning_limit_pulse <= '1' when (err_warning_limit_d /= err_warning_limit_q)
Count: 3183
Threshold: 1

Signal assignment statement:

211: '0';
Count: 4783
Threshold: 1

Signal assignment statement:

221: next_state <= curr_state;
Count: 34449
Threshold: 1

Sequential statement:

223:        case curr_state is 
224:        when s_fc_err_active => 
...
239:            end if; 
240:        end case;

Count: 34449
Threshold: 1

If statement:

225:            if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then 
226:                next_state <= s_fc_err_passive; 
227:            end if;

Count: 17598
Threshold: 1

Signal assignment statement:

226: next_state <= s_fc_err_passive;
Count: 1108
Threshold: 1

If statement:

230:            if (tx_err_ctr_mt_255 = '1') then 
231:                next_state <= s_fc_bus_off; 
232:            elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then 
233:                next_state <= s_fc_err_active; 
234:            end if;

Count: 1558
Threshold: 1

Signal assignment statement:

231: next_state <= s_fc_bus_off;
Count: 265
Threshold: 1

Signal assignment statement:

233: next_state <= s_fc_err_active;
Count: 188
Threshold: 1

If statement:

237:            if (set_err_active = '1') then 
238:                next_state <= s_fc_err_active; 
239:            end if;

Count: 15293
Threshold: 1

Signal assignment statement:

238: next_state <= s_fc_err_active;
Count: 6636
Threshold: 1

If statement:

249:        if (res_n = '0') then 
250:            curr_state <= s_fc_bus_off; 
251:        elsif (rising_edge(clk_sys)) then 
252:            curr_state <= next_state; 
253:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

250: curr_state <= s_fc_bus_off;
Count: 2418499
Threshold: 1

Signal assignment statement:

252: curr_state <= next_state;
Count: 526374300
Threshold: 1

Signal assignment statement:

261: is_err_active <= '0';
Count: 17419
Threshold: 1

Signal assignment statement:

262: is_err_passive <= '0';
Count: 17419
Threshold: 1

Signal assignment statement:

263: is_bus_off <= '0';
Count: 17419
Threshold: 1

Sequential statement:

265:        case curr_state is 
266:        when s_fc_err_active => 
...
273:            is_bus_off <= '1'; 
274:        end case;

Count: 17419
Threshold: 1

Signal assignment statement:

267: is_err_active <= '1';
Count: 8424
Threshold: 1

Signal assignment statement:

270: is_err_passive <= '1';
Count: 768
Threshold: 1

Signal assignment statement:

273: is_bus_off <= '1';
Count: 8227
Threshold: 1

If statement:

278:    fcs_changed <= '1' when (curr_state /= next_state) else 
279:                   '0';

Count: 33578
Threshold: 1

Signal assignment statement:

278: fcs_changed <= '1' when (curr_state /= next_state) else
Count: 15989
Threshold: 1

Signal assignment statement:

279: '0';
Count: 17589
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

169: tx_err_ctr_mt_erp <= '1' when (unsigned(tx_err_ctr) >= unsigned(mr_erp_erp_limit))

	Evaluated to	Count	Threshold
Bin	True	2043	1
Bin	False	30653	1

"if" / "when" / "else" condition:

174: rx_err_ctr_mt_erp <= '1' when (unsigned(rx_err_ctr) >= unsigned(mr_erp_erp_limit))

	Evaluated to	Count	Threshold
Bin	True	8884	1
Bin	False	18531	1

"if" / "when" / "else" condition:

179: tx_err_ctr_mt_255 <= '1' when (unsigned(tx_err_ctr) > 255)

	Evaluated to	Count	Threshold
Bin	True	249	1
Bin	False	32277	1

"if" / "when" / "else" condition:

184: tx_err_ctr_mt_ewl <= '1' when (unsigned(tx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))

	Evaluated to	Count	Threshold
Bin	True	2629	1
Bin	False	30065	1

"if" / "when" / "else" condition:

189: rx_err_ctr_mt_ewl <= '1' when (unsigned(rx_err_ctr) >= ('0' & unsigned(mr_ewl_ew_limit)))

	Evaluated to	Count	Threshold
Bin	True	9290	1
Bin	False	18123	1

"if" / "when" / "else" condition:

193: err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1')

	Evaluated to	Count	Threshold
Bin	True	1202	1
Bin	False	3991	1

"if" / "when" / "else" condition:

202: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

204: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

209: err_warning_limit_pulse <= '1' when (err_warning_limit_d /= err_warning_limit_q)

	Evaluated to	Count	Threshold
Bin	True	3183	1
Bin	False	4783	1

"case" / "with" / "select" choice:

224: when s_fc_err_active =>

	Choice of	Count	Threshold
Bin	`s_fc_err_active`	17598	1

"if" / "when" / "else" condition:

225: if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then

	Evaluated to	Count	Threshold
Bin	True	1108	1
Bin	False	16490	1

"case" / "with" / "select" choice:

229: when s_fc_err_passive =>

	Choice of	Count	Threshold
Bin	`s_fc_err_passive`	1558	1

"if" / "when" / "else" condition:

230: if (tx_err_ctr_mt_255 = '1') then

	Evaluated to	Count	Threshold
Bin	True	265	1
Bin	False	1293	1

"if" / "when" / "else" condition:

232: elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then

	Evaluated to	Count	Threshold
Bin	True	188	1
Bin	False	1105	1

"case" / "with" / "select" choice:

236: when s_fc_bus_off =>

	Choice of	Count	Threshold
Bin	`s_fc_bus_off`	15293	1

"if" / "when" / "else" condition:

237: if (set_err_active = '1') then

	Evaluated to	Count	Threshold
Bin	True	6636	1
Bin	False	8657	1

"if" / "when" / "else" condition:

249: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

251: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"case" / "with" / "select" choice:

266: when s_fc_err_active =>

	Choice of	Count	Threshold
Bin	`s_fc_err_active`	8424	1

"case" / "with" / "select" choice:

269: when s_fc_err_passive =>

	Choice of	Count	Threshold
Bin	`s_fc_err_passive`	768	1

"case" / "with" / "select" choice:

272: when s_fc_bus_off =>

	Choice of	Count	Threshold
Bin	`s_fc_bus_off`	8227	1

"if" / "when" / "else" condition:

278: fcs_changed <= '1' when (curr_state /= next_state) else

	Evaluated to	Count	Threshold
Bin	True	15989	1
Bin	False	17589	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

SET_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	6636	1
Bin	1	0	8236	1

Port:

MR_EWL_EW_LIMIT(7)

	From	To	Count	Threshold
Bin	0	1	78	1
Bin	1	0	1678	1

Port:

MR_EWL_EW_LIMIT(6)

	From	To	Count	Threshold
Bin	0	1	1686	1
Bin	1	0	86	1

Port:

MR_EWL_EW_LIMIT(5)

	From	To	Count	Threshold
Bin	0	1	1670	1
Bin	1	0	70	1

Port:

MR_EWL_EW_LIMIT(4)

	From	To	Count	Threshold
Bin	0	1	82	1
Bin	1	0	1682	1

Port:

MR_EWL_EW_LIMIT(3)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_EWL_EW_LIMIT(2)

	From	To	Count	Threshold
Bin	0	1	73	1
Bin	1	0	1673	1

Port:

MR_EWL_EW_LIMIT(1)

	From	To	Count	Threshold
Bin	0	1	83	1
Bin	1	0	1683	1

Port:

MR_EWL_EW_LIMIT(0)

	From	To	Count	Threshold
Bin	0	1	79	1
Bin	1	0	1679	1

Port:

MR_ERP_ERP_LIMIT(7)

	From	To	Count	Threshold
Bin	0	1	1736	1
Bin	1	0	136	1

Port:

MR_ERP_ERP_LIMIT(6)

	From	To	Count	Threshold
Bin	0	1	20	1
Bin	1	0	1620	1

Port:

MR_ERP_ERP_LIMIT(5)

	From	To	Count	Threshold
Bin	0	1	22	1
Bin	1	0	1622	1

Port:

MR_ERP_ERP_LIMIT(4)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

MR_ERP_ERP_LIMIT(3)

	From	To	Count	Threshold
Bin	0	1	26	1
Bin	1	0	1626	1

Port:

MR_ERP_ERP_LIMIT(2)

	From	To	Count	Threshold
Bin	0	1	27	1
Bin	1	0	1627	1

Port:

MR_ERP_ERP_LIMIT(1)

	From	To	Count	Threshold
Bin	0	1	29	1
Bin	1	0	1629	1

Port:

MR_ERP_ERP_LIMIT(0)

	From	To	Count	Threshold
Bin	0	1	21	1
Bin	1	0	1621	1

Port:

MR_STATUS_EWL

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	2391	1

Port:

TX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Port:

TX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	521	1
Bin	1	0	2121	1

Port:

TX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	488	1
Bin	1	0	2088	1

Port:

TX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	811	1
Bin	1	0	2411	1

Port:

TX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	1931	1
Bin	1	0	3531	1

Port:

TX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	12094	1
Bin	1	0	13694	1

Port:

TX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	2980	1
Bin	1	0	4580	1

Port:

TX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	3318	1
Bin	1	0	4918	1

Port:

TX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	3517	1
Bin	1	0	5117	1

Port:

RX_ERR_CTR(8)

	From	To	Count	Threshold
Bin	0	1	136	1
Bin	1	0	1736	1

Port:

RX_ERR_CTR(7)

	From	To	Count	Threshold
Bin	0	1	360	1
Bin	1	0	1960	1

Port:

RX_ERR_CTR(6)

	From	To	Count	Threshold
Bin	0	1	266	1
Bin	1	0	1864	1

Port:

RX_ERR_CTR(5)

	From	To	Count	Threshold
Bin	0	1	332	1
Bin	1	0	1931	1

Port:

RX_ERR_CTR(4)

	From	To	Count	Threshold
Bin	0	1	519	1
Bin	1	0	2119	1

Port:

RX_ERR_CTR(3)

	From	To	Count	Threshold
Bin	0	1	686	1
Bin	1	0	2285	1

Port:

RX_ERR_CTR(2)

	From	To	Count	Threshold
Bin	0	1	627	1
Bin	1	0	2227	1

Port:

RX_ERR_CTR(1)

	From	To	Count	Threshold
Bin	0	1	1208	1
Bin	1	0	2808	1

Port:

RX_ERR_CTR(0)

	From	To	Count	Threshold
Bin	0	1	11221	1
Bin	1	0	12815	1

Port:

IS_ERR_ACTIVE

	From	To	Count	Threshold
Bin	0	1	8424	1
Bin	1	0	8415	1

Port:

IS_ERR_PASSIVE

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8236	1

Port:

FCS_CHANGED

	From	To	Count	Threshold
Bin	0	1	15989	1
Bin	1	0	17589	1

Port:

ERR_WARNING_LIMIT_PULSE

	From	To	Count	Threshold
Bin	0	1	3183	1
Bin	1	0	4783	1

Signal:

TX_ERR_CTR_MT_ERP

	From	To	Count	Threshold
Bin	0	1	693	1
Bin	1	0	2293	1

Signal:

RX_ERR_CTR_MT_ERP

	From	To	Count	Threshold
Bin	0	1	524	1
Bin	1	0	2124	1

Signal:

TX_ERR_CTR_MT_EWL

	From	To	Count	Threshold
Bin	0	1	716	1
Bin	1	0	2316	1

Signal:

RX_ERR_CTR_MT_EWL

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	2049	1

Signal:

TX_ERR_CTR_MT_255

	From	To	Count	Threshold
Bin	0	1	249	1
Bin	1	0	1849	1

Signal:

ERR_WARNING_LIMIT_D

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	2391	1

Signal:

ERR_WARNING_LIMIT_Q

	From	To	Count	Threshold
Bin	0	1	792	1
Bin	1	0	2391	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

193: err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1')

	Evaluated to	Count	Threshold
Bin	False	4274	1
Bin	True	919	1

"=" expression

193: err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1')

	Evaluated to	Count	Threshold
Bin	False	4536	1
Bin	True	657	1

"or" expression

193:    err_warning_limit_d <= '1' when (tx_err_ctr_mt_ewl = '1' or rx_err_ctr_mt_ewl = '1') 
                                         <---------LHS--------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	3991	1
Bin	False	True	283	1
Bin	True	False	545	1

"=" expression

202: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"/=" expression

209: err_warning_limit_pulse <= '1' when (err_warning_limit_d /= err_warning_limit_q)

	Evaluated to	Count	Threshold
Bin	False	4783	1
Bin	True	3183	1

"=" expression

225: if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then

	Evaluated to	Count	Threshold
Bin	False	16799	1
Bin	True	799	1

"=" expression

225: if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then

	Evaluated to	Count	Threshold
Bin	False	16997	1
Bin	True	601	1

"or" expression

225:            if (tx_err_ctr_mt_erp = '1' or rx_err_ctr_mt_erp = '1') then 
                    <---------LHS--------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	16490	1
Bin	False	True	309	1
Bin	True	False	507	1

"=" expression

230: if (tx_err_ctr_mt_255 = '1') then

	Evaluated to	Count	Threshold
Bin	False	1293	1
Bin	True	265	1

"=" expression

232: elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then

	Evaluated to	Count	Threshold
Bin	False	796	1
Bin	True	497	1

"=" expression

232: elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then

	Evaluated to	Count	Threshold
Bin	False	622	1
Bin	True	671	1

"and" expression

232:            elsif (tx_err_ctr_mt_erp = '0' and rx_err_ctr_mt_erp = '0') then 
                       <---------LHS--------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	483	1
Bin	True	False	309	1
Bin	True	True	188	1

"=" expression

237: if (set_err_active = '1') then

	Evaluated to	Count	Threshold
Bin	False	8657	1
Bin	True	6636	1

"=" expression

249: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"/=" expression

278: fcs_changed <= '1' when (curr_state /= next_state) else

	Evaluated to	Count	Threshold
Bin	False	17589	1
Bin	True	15989	1

	State	Count	Threshold
Bin	S_FC_ERR_ACTIVE	8424	1
Bin	S_FC_ERR_PASSIVE	768	1
Bin	S_FC_BUS_OFF	8227	1

	State	Count	Threshold
Bin	S_FC_ERR_ACTIVE	8594	1
Bin	S_FC_ERR_PASSIVE	938	1
Bin	S_FC_BUS_OFF	8227	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement_fsm.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Sequential statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

Sequential statement:

Signal assignment statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"case" / "with" / "select" choice:

"if" / "when" / "else" condition: