NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_FD_SJW_FD_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (42/42)	100.0 % (6/6)	N.A.	N.A.	100.0 % (49/49)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 284254
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	31028760	1
Bin	1	0	31030360	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	61362	1
Bin	1	0	1028483	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	67108	1
Bin	1	0	1022737	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	63097	1
Bin	1	0	1026748	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	91439	1
Bin	1	0	998406	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	79643	1
Bin	1	0	1010202	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	125737	1
Bin	1	0	127337	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	6713	1
Bin	1	0	8313	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	1833	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	275	1
Bin	1	0	1872	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	929	1
Bin	1	0	2526	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	2558	1
Bin	1	0	965	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	949	1
Bin	1	0	2546	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	251	1
Bin	1	0	3885	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	289	1
Bin	1	0	3847	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	953	1
Bin	1	0	3183	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	3129	1
Bin	1	0	1007	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	961	1
Bin	1	0	3175	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	6346	1
Bin	1	0	7946	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	6713	1
Bin	'1'	'0'	135459	1
Bin	'1'	'1'	6351	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	65500	1
Bin	'1'	'0'	5	1
Bin	'1'	'1'	6346	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.BTR_FD_SJW_FD_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: