NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_WRITE_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

103: parity_tmp := G_PARITY_TYPE;
Count: 383868
Threshold: 1

Loop statement:

105:        for i in 0 to G_WIDTH-1 loop 
106:            parity_tmp := parity_tmp xor data_in(i); 
107:        end loop;

Count: 383868
Threshold: 1

Variable assignment statement:

106: parity_tmp := parity_tmp xor data_in(i);
Count: 12283776
Threshold: 1

Signal assignment statement:

109: parity <= parity_tmp;
Count: 383868
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

DATA_IN(31)

	From	To	Count	Threshold
Bin	0	1	23578	1
Bin	1	0	24238	1

Port:

DATA_IN(30)

	From	To	Count	Threshold
Bin	0	1	23912	1
Bin	1	0	24572	1

Port:

DATA_IN(29)

	From	To	Count	Threshold
Bin	0	1	25941	1
Bin	1	0	26601	1

Port:

DATA_IN(28)

	From	To	Count	Threshold
Bin	0	1	30629	1
Bin	1	0	31289	1

Port:

DATA_IN(27)

	From	To	Count	Threshold
Bin	0	1	30135	1
Bin	1	0	30795	1

Port:

DATA_IN(26)

	From	To	Count	Threshold
Bin	0	1	34313	1
Bin	1	0	34973	1

Port:

DATA_IN(25)

	From	To	Count	Threshold
Bin	0	1	38203	1
Bin	1	0	38863	1

Port:

DATA_IN(24)

	From	To	Count	Threshold
Bin	0	1	44167	1
Bin	1	0	44827	1

Port:

DATA_IN(23)

	From	To	Count	Threshold
Bin	0	1	38083	1
Bin	1	0	38743	1

Port:

DATA_IN(22)

	From	To	Count	Threshold
Bin	0	1	40371	1
Bin	1	0	41031	1

Port:

DATA_IN(21)

	From	To	Count	Threshold
Bin	0	1	41696	1
Bin	1	0	42356	1

Port:

DATA_IN(20)

	From	To	Count	Threshold
Bin	0	1	42728	1
Bin	1	0	43388	1

Port:

DATA_IN(19)

	From	To	Count	Threshold
Bin	0	1	46212	1
Bin	1	0	46872	1

Port:

DATA_IN(18)

	From	To	Count	Threshold
Bin	0	1	49045	1
Bin	1	0	49705	1

Port:

DATA_IN(17)

	From	To	Count	Threshold
Bin	0	1	47221	1
Bin	1	0	47881	1

Port:

DATA_IN(16)

	From	To	Count	Threshold
Bin	0	1	47464	1
Bin	1	0	48124	1

Port:

DATA_IN(15)

	From	To	Count	Threshold
Bin	0	1	49477	1
Bin	1	0	50137	1

Port:

DATA_IN(14)

	From	To	Count	Threshold
Bin	0	1	52829	1
Bin	1	0	53489	1

Port:

DATA_IN(13)

	From	To	Count	Threshold
Bin	0	1	52924	1
Bin	1	0	53584	1

Port:

DATA_IN(12)

	From	To	Count	Threshold
Bin	0	1	60019	1
Bin	1	0	60679	1

Port:

DATA_IN(11)

	From	To	Count	Threshold
Bin	0	1	62335	1
Bin	1	0	62995	1

Port:

DATA_IN(10)

	From	To	Count	Threshold
Bin	0	1	55143	1
Bin	1	0	55803	1

Port:

DATA_IN(9)

	From	To	Count	Threshold
Bin	0	1	56362	1
Bin	1	0	57022	1

Port:

DATA_IN(8)

	From	To	Count	Threshold
Bin	0	1	57144	1
Bin	1	0	57804	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	59293	1
Bin	1	0	59953	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	57394	1
Bin	1	0	58054	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	61325	1
Bin	1	0	61985	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	55933	1
Bin	1	0	56593	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	55677	1
Bin	1	0	56337	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	59812	1
Bin	1	0	60472	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	61791	1
Bin	1	0	62451	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	59951	1
Bin	1	0	60611	1

Port:

PARITY

	From	To	Count	Threshold
Bin	0	1	96648	1
Bin	1	0	95988	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

106:            parity_tmp := parity_tmp xor data_in(i); 
                              <--LHS--->     <--RHS--->

	LHS	RHS	Count	Threshold
Bin	'0'	'0'	3329609	1
Bin	'0'	'1'	2168018	1
Bin	'1'	'0'	4419455	1
Bin	'1'	'1'	2345574	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.PARITY_TRUE_GEN.PARITY_CALCULATOR_WRITE_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/parity_calculator.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Variable assignment statement:

Loop statement:

Variable assignment statement:

Signal assignment statement:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"xor" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: