NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_NBT_INST	100.0 % (23/23)	100.0 % (20/20)	100.0 % (114/114)	100.0 % (29/29)	N.A.	N.A.	100.0 % (186/186)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_NBT_INST

100.0 % (23/23)

100.0 % (20/20)

100.0 % (114/114)

100.0 % (29/29)

N.A.

100.0 % (186/186)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 329545906
Threshold: 1

Signal assignment statement on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 98927208
Threshold: 1

Signal assignment statement on line 157:

157: '0';
Count: 230618698
Threshold: 1

If statement on lines 165 to 168:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 573020659
Threshold: 1

Signal assignment statement on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 242003696
Threshold: 1

Signal assignment statement on line 168:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 331016963
Threshold: 1

If statement on lines 172 to 178:

172:        if (res_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 173:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2424883
Threshold: 1

If statement on lines 175 to 177:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 176:

176: tq_counter_q <= tq_counter_d;
Count: 543790077
Threshold: 1

Signal assignment statement on line 184:

184: tq_edge_i <= tq_counter_expired;
Count: 197857615
Threshold: 1

If statement on lines 189 to 190:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 363175134
Threshold: 1

Signal assignment statement on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 45593809
Threshold: 1

Signal assignment statement on line 190:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 317581325
Threshold: 1

If statement on lines 192 to 194:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 243498170
Threshold: 1

Signal assignment statement on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 138697177
Threshold: 1

Signal assignment statement on line 194:

194: '0';
Count: 104800993
Threshold: 1

If statement on lines 198 to 204:

198:        if (res_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1090018206
Threshold: 1

Signal assignment statement on line 199:

199: segm_counter_q <= (others => '0');
Count: 2424883
Threshold: 1

If statement on lines 201 to 203:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 543791678
Threshold: 1

Signal assignment statement on line 202:

202: segm_counter_q <= segm_counter_d;
Count: 317565218
Threshold: 1

Signal assignment statement on line 210:

210: segm_counter <= segm_counter_q;
Count: 317547533
Threshold: 1

Signal assignment statement on line 211:

211: tq_edge <= tq_edge_i;
Count: 197857615
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	98927208	1
Bin	False	230618698	1

"if" / "when" / "else" condition on line 166:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	242003696	1
Bin	False	331016963	1

"if" / "when" / "else" condition on line 172:

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 174:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 175:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	543790077	1
Bin	False	1601	1

"if" / "when" / "else" condition on line 189:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	45593809	1
Bin	False	317581325	1

"if" / "when" / "else" condition on line 192:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	138697177	1
Bin	False	104800993	1

"if" / "when" / "else" condition on line 198:

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2424883	1
Bin	False	1087593323	1

"if" / "when" / "else" condition on line 200:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	543791678	1
Bin	False	543801645	1

"if" / "when" / "else" condition on line 201:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	317565218	1
Bin	False	226226460	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BRP

	Element	From	To	Threshold	Excluded due to
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TQ_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BT_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

CTRS_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	98927208	1
Bin	1	0	98928806	1

Port:

SEGM_COUNTER

	Element	From	To	Count	Threshold
Bin	(7)	0	1	567762	1
Bin	(7)	1	0	569363	1
Bin	(6)	0	1	916230	1
Bin	(6)	1	0	917830	1
Bin	(5)	0	1	3211003	1
Bin	(5)	1	0	3212604	1
Bin	(4)	0	1	6924096	1
Bin	(4)	1	0	6925697	1
Bin	(3)	0	1	15395931	1
Bin	(3)	1	0	15397530	1
Bin	(2)	0	1	37654100	1
Bin	(2)	1	0	37655700	1
Bin	(1)	0	1	78939501	1
Bin	(1)	1	0	78941099	1
Bin	(0)	0	1	151143099	1
Bin	(0)	1	0	151144695	1

Signal:

TQ_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	2189	1
Bin	(7)	1	0	3790	1
Bin	(6)	0	1	4378	1
Bin	(6)	1	0	5979	1
Bin	(5)	0	1	19724	1
Bin	(5)	1	0	21325	1
Bin	(4)	0	1	54963	1
Bin	(4)	1	0	56564	1
Bin	(3)	0	1	820807	1
Bin	(3)	1	0	822408	1
Bin	(2)	0	1	65068237	1
Bin	(2)	1	0	65069835	1
Bin	(1)	0	1	106290923	1
Bin	(1)	1	0	106289328	1
Bin	(0)	0	1	172262036	1
Bin	(0)	1	0	172263633	1

Signal:

TQ_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	2189	1
Bin	(7)	1	0	3790	1
Bin	(6)	0	1	4378	1
Bin	(6)	1	0	5979	1
Bin	(5)	0	1	8756	1
Bin	(5)	1	0	10357	1
Bin	(4)	0	1	54963	1
Bin	(4)	1	0	56564	1
Bin	(3)	0	1	820788	1
Bin	(3)	1	0	822389	1
Bin	(2)	0	1	53056095	1
Bin	(2)	1	0	53057696	1
Bin	(1)	0	1	104800999	1
Bin	(1)	1	0	104802595	1
Bin	(0)	0	1	158749767	1
Bin	(0)	1	0	158748168	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	98927208	1
Bin	1	0	98928806	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	98927208	1
Bin	1	0	98928806	1

Signal:

SEGM_COUNTER_D

	Element	From	To	Count	Threshold
Bin	(7)	0	1	567788	1
Bin	(7)	1	0	569389	1
Bin	(6)	0	1	1193336	1
Bin	(6)	1	0	1194936	1
Bin	(5)	0	1	3219125	1
Bin	(5)	1	0	3220726	1
Bin	(4)	0	1	7112894	1
Bin	(4)	1	0	7114495	1
Bin	(3)	0	1	15728681	1
Bin	(3)	1	0	15730280	1
Bin	(2)	0	1	41088459	1
Bin	(2)	1	0	41090059	1
Bin	(1)	0	1	82234187	1
Bin	(1)	1	0	82235780	1
Bin	(0)	0	1	166431480	1
Bin	(0)	1	0	166429884	1

Signal:

SEGM_COUNTER_Q

	Element	From	To	Count	Threshold
Bin	(7)	0	1	567762	1
Bin	(7)	1	0	569363	1
Bin	(6)	0	1	916230	1
Bin	(6)	1	0	917830	1
Bin	(5)	0	1	3211003	1
Bin	(5)	1	0	3212604	1
Bin	(4)	0	1	6924096	1
Bin	(4)	1	0	6925697	1
Bin	(3)	0	1	15395931	1
Bin	(3)	1	0	15397530	1
Bin	(2)	0	1	37654100	1
Bin	(2)	1	0	37655700	1
Bin	(1)	0	1	78939501	1
Bin	(1)	1	0	78941099	1
Bin	(0)	0	1	151143099	1
Bin	(0)	1	0	151144695	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	104786236	1
Bin	1	0	104787834	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

 tq_counter_expired = '1' or tq_reset = '1' 
 <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	331016963	1
Bin	False	True	14329617	1
Bin	True	False	206630340	1

"=" expression on line 166:

tq_counter_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	345346580	1
Bin	True	227674079	1

"=" expression on line 166:

tq_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	537647303	1
Bin	True	35373356	1

"=" expression on line 172:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 175:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	1601	1
Bin	True	543790077	1

"=" expression on line 189:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	317581325	1
Bin	True	45593809	1

"or" expression on line 192:

 (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
  <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	104800993	1
Bin	False	True	111795178	1
Bin	True	False	9946540	1

"=" expression on line 192:

bt_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	216596171	1
Bin	True	26901999	1

"and" expression on line 192:

 tq_edge_i = '1' and ctrs_en = '1' 
 <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	114730363	1
Bin	True	False	7360	1
Bin	True	True	128750637	1

"=" expression on line 192:

tq_edge_i = '1'

	Evaluated to	Count	Threshold
Bin	False	114740173	1
Bin	True	128757997	1

"=" expression on line 192:

ctrs_en = '1'

	Evaluated to	Count	Threshold
Bin	False	17170	1
Bin	True	243481000	1

"=" expression on line 198:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1087593323	1
Bin	True	2424883	1

"=" expression on line 201:

segm_counter_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	226226460	1
Bin	True	317565218	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_NBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/prescaler.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 155 to 157:

Signal assignment statement on line 155:

Signal assignment statement on line 157:

If statement on lines 165 to 168:

Signal assignment statement on line 166:

Signal assignment statement on line 168:

If statement on lines 172 to 178:

Signal assignment statement on line 173:

If statement on lines 175 to 177:

Signal assignment statement on line 176:

Signal assignment statement on line 184:

If statement on lines 189 to 190:

Signal assignment statement on line 189:

Signal assignment statement on line 190:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 194:

If statement on lines 198 to 204:

Signal assignment statement on line 199:

If statement on lines 201 to 203:

Signal assignment statement on line 202:

Signal assignment statement on line 210:

Signal assignment statement on line 211:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 155:

"if" / "when" / "else" condition on line 166:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 175:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 200:

"if" / "when" / "else" condition on line 201:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"or" expression on line 166:

"=" expression on line 166:

"=" expression on line 166:

"=" expression on line 172:

"=" expression on line 175:

"=" expression on line 189:

"or" expression on line 192:

"=" expression on line 192:

"and" expression on line 192:

"=" expression on line 192:

"=" expression on line 192:

"=" expression on line 198:

"=" expression on line 201:

Uncovered FSM states:

Excluded FSM states: