NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_NBT_INST	100.0 % (20/20)	100.0 % (20/20)	100.0 % (114/114)	100.0 % (29/29)	N.A.	N.A.	100.0 % (183/183)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

155:    tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp)) 
156:                              else 
157:                          '0';

Count: 321839935
Threshold: 1

Signal assignment statement:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))
Count: 96725568
Threshold: 1

Signal assignment statement:

157: '0';
Count: 225114367
Threshold: 1

If statement:

165:    tq_counter_d <= 
166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
167:                                   else 
168:        std_logic_vector(unsigned(tq_counter_q) + 1);

Count: 559521663
Threshold: 1

Signal assignment statement:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')
Count: 236213424
Threshold: 1

Signal assignment statement:

168: std_logic_vector(unsigned(tq_counter_q) + 1);
Count: 323308239
Threshold: 1

If statement:

172:        if (res_n = '0') then 
173:            tq_counter_q <= std_logic_vector(C_TQ_RST); 
...
177:            end if; 
178:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

173: tq_counter_q <= std_logic_vector(C_TQ_RST);
Count: 2418499
Threshold: 1

If statement:

175:            if (ctrs_en = '1') then 
176:                tq_counter_q <= tq_counter_d; 
177:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

176: tq_counter_q <= tq_counter_d;
Count: 526372700
Threshold: 1

If statement:

189:    segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else 
190:                      std_logic_vector(unsigned(segm_counter_q) + 1);

Count: 349890012
Threshold: 1

Signal assignment statement:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else
Count: 44204459
Threshold: 1

Signal assignment statement:

190: std_logic_vector(unsigned(segm_counter_q) + 1);
Count: 305685553
Threshold: 1

If statement:

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
193:                           else 
194:                       '0';

Count: 237705127
Threshold: 1

Signal assignment statement:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')
Count: 135091302
Threshold: 1

Signal assignment statement:

194: '0';
Count: 102613825
Threshold: 1

If statement:

198:        if (res_n = '0') then 
199:            segm_counter_q <= (others => '0'); 
...
203:            end if; 
204:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

199: segm_counter_q <= (others => '0');
Count: 2418499
Threshold: 1

If statement:

201:            if (segm_counter_ce = '1') then 
202:                segm_counter_q <= segm_counter_d; 
203:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

202: segm_counter_q <= segm_counter_d;
Count: 305669394
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

155: tq_counter_expired <= '1' when (unsigned(tq_counter_q) = unsigned(brp))

	Evaluated to	Count	Threshold
Bin	True	96725568	1
Bin	False	225114367	1

"if" / "when" / "else" condition:

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	True	236213424	1
Bin	False	323308239	1

"if" / "when" / "else" condition:

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

174: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	True	526372700	1
Bin	False	1600	1

"if" / "when" / "else" condition:

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	44204459	1
Bin	False	305685553	1

"if" / "when" / "else" condition:

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	True	135091302	1
Bin	False	102613825	1

"if" / "when" / "else" condition:

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

200: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	305669394	1
Bin	False	220704906	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

BRP(7)

	From	To	Count	Threshold
Bin	0	1	13	1
Bin	1	0	1613	1

Port:

BRP(6)

	From	To	Count	Threshold
Bin	0	1	12	1
Bin	1	0	1612	1

Port:

BRP(5)

	From	To	Count	Threshold
Bin	0	1	13	1
Bin	1	0	1613	1

Port:

BRP(4)

	From	To	Count	Threshold
Bin	0	1	17	1
Bin	1	0	1617	1

Port:

BRP(3)

	From	To	Count	Threshold
Bin	0	1	4831	1
Bin	1	0	3241	1

Port:

BRP(2)

	From	To	Count	Threshold
Bin	0	1	928	1
Bin	1	0	2523	1

Port:

BRP(1)

	From	To	Count	Threshold
Bin	0	1	4762	1
Bin	1	0	3169	1

Port:

BRP(0)

	From	To	Count	Threshold
Bin	0	1	2315	1
Bin	1	0	3912	1

Port:

TQ_RESET

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Port:

BT_RESET

	From	To	Count	Threshold
Bin	0	1	22118120	1
Bin	1	0	22119720	1

Port:

CTRS_EN

	From	To	Count	Threshold
Bin	0	1	6482	1
Bin	1	0	8072	1

Port:

TQ_EDGE

	From	To	Count	Threshold
Bin	0	1	96725568	1
Bin	1	0	96727165	1

Port:

SEGM_COUNTER(7)

	From	To	Count	Threshold
Bin	0	1	539581	1
Bin	1	0	541181	1

Port:

SEGM_COUNTER(6)

	From	To	Count	Threshold
Bin	0	1	891264	1
Bin	1	0	892863	1

Port:

SEGM_COUNTER(5)

	From	To	Count	Threshold
Bin	0	1	3071222	1
Bin	1	0	3072822	1

Port:

SEGM_COUNTER(4)

	From	To	Count	Threshold
Bin	0	1	6644766	1
Bin	1	0	6646365	1

Port:

SEGM_COUNTER(3)

	From	To	Count	Threshold
Bin	0	1	14781650	1
Bin	1	0	14783248	1

Port:

SEGM_COUNTER(2)

	From	To	Count	Threshold
Bin	0	1	36114069	1
Bin	1	0	36115669	1

Port:

SEGM_COUNTER(1)

	From	To	Count	Threshold
Bin	0	1	75947170	1
Bin	1	0	75948767	1

Port:

SEGM_COUNTER(0)

	From	To	Count	Threshold
Bin	0	1	145561048	1
Bin	1	0	145562645	1

Signal:

TQ_COUNTER_D(7)

	From	To	Count	Threshold
Bin	0	1	2182	1
Bin	1	0	3782	1

Signal:

TQ_COUNTER_D(6)

	From	To	Count	Threshold
Bin	0	1	4364	1
Bin	1	0	5964	1

Signal:

TQ_COUNTER_D(5)

	From	To	Count	Threshold
Bin	0	1	16727	1
Bin	1	0	18327	1

Signal:

TQ_COUNTER_D(4)

	From	To	Count	Threshold
Bin	0	1	64384	1
Bin	1	0	65984	1

Signal:

TQ_COUNTER_D(3)

	From	To	Count	Threshold
Bin	0	1	657397	1
Bin	1	0	658997	1

Signal:

TQ_COUNTER_D(2)

	From	To	Count	Threshold
Bin	0	1	63799032	1
Bin	1	0	63800630	1

Signal:

TQ_COUNTER_D(1)

	From	To	Count	Threshold
Bin	0	1	103821176	1
Bin	1	0	103819581	1

Signal:

TQ_COUNTER_D(0)

	From	To	Count	Threshold
Bin	0	1	168366063	1
Bin	1	0	168367659	1

Signal:

TQ_COUNTER_Q(7)

	From	To	Count	Threshold
Bin	0	1	2182	1
Bin	1	0	3782	1

Signal:

TQ_COUNTER_Q(6)

	From	To	Count	Threshold
Bin	0	1	4364	1
Bin	1	0	5964	1

Signal:

TQ_COUNTER_Q(5)

	From	To	Count	Threshold
Bin	0	1	8728	1
Bin	1	0	10328	1

Signal:

TQ_COUNTER_Q(4)

	From	To	Count	Threshold
Bin	0	1	64384	1
Bin	1	0	65984	1

Signal:

TQ_COUNTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	657377	1
Bin	1	0	658977	1

Signal:

TQ_COUNTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	51851575	1
Bin	1	0	51853175	1

Signal:

TQ_COUNTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	102346812	1
Bin	1	0	102348408	1

Signal:

TQ_COUNTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	154937020	1
Bin	1	0	154935422	1

Signal:

TQ_COUNTER_EXPIRED

	From	To	Count	Threshold
Bin	0	1	96725568	1
Bin	1	0	96727165	1

Signal:

TQ_EDGE_I

	From	To	Count	Threshold
Bin	0	1	96725568	1
Bin	1	0	96727165	1

Signal:

SEGM_COUNTER_D(7)

	From	To	Count	Threshold
Bin	0	1	539611	1
Bin	1	0	541211	1

Signal:

SEGM_COUNTER_D(6)

	From	To	Count	Threshold
Bin	0	1	1158523	1
Bin	1	0	1160122	1

Signal:

SEGM_COUNTER_D(5)

	From	To	Count	Threshold
Bin	0	1	3078938	1
Bin	1	0	3080538	1

Signal:

SEGM_COUNTER_D(4)

	From	To	Count	Threshold
Bin	0	1	6834911	1
Bin	1	0	6836510	1

Signal:

SEGM_COUNTER_D(3)

	From	To	Count	Threshold
Bin	0	1	15121519	1
Bin	1	0	15123117	1

Signal:

SEGM_COUNTER_D(2)

	From	To	Count	Threshold
Bin	0	1	39572001	1
Bin	1	0	39573601	1

Signal:

SEGM_COUNTER_D(1)

	From	To	Count	Threshold
Bin	0	1	79256537	1
Bin	1	0	79258131	1

Signal:

SEGM_COUNTER_D(0)

	From	To	Count	Threshold
Bin	0	1	160117697	1
Bin	1	0	160116100	1

Signal:

SEGM_COUNTER_Q(7)

	From	To	Count	Threshold
Bin	0	1	539581	1
Bin	1	0	541181	1

Signal:

SEGM_COUNTER_Q(6)

	From	To	Count	Threshold
Bin	0	1	891264	1
Bin	1	0	892863	1

Signal:

SEGM_COUNTER_Q(5)

	From	To	Count	Threshold
Bin	0	1	3071222	1
Bin	1	0	3072822	1

Signal:

SEGM_COUNTER_Q(4)

	From	To	Count	Threshold
Bin	0	1	6644766	1
Bin	1	0	6646365	1

Signal:

SEGM_COUNTER_Q(3)

	From	To	Count	Threshold
Bin	0	1	14781650	1
Bin	1	0	14783248	1

Signal:

SEGM_COUNTER_Q(2)

	From	To	Count	Threshold
Bin	0	1	36114069	1
Bin	1	0	36115669	1

Signal:

SEGM_COUNTER_Q(1)

	From	To	Count	Threshold
Bin	0	1	75947170	1
Bin	1	0	75948767	1

Signal:

SEGM_COUNTER_Q(0)

	From	To	Count	Threshold
Bin	0	1	145561048	1
Bin	1	0	145562645	1

Signal:

SEGM_COUNTER_CE

	From	To	Count	Threshold
Bin	0	1	102599081	1
Bin	1	0	102600678	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	False	337515119	1
Bin	True	222006544	1

"=" expression

166: std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1')

	Evaluated to	Count	Threshold
Bin	False	525134867	1
Bin	True	34386796	1

"or" expression

166:        std_logic_vector(C_TQ_RST) when (tq_counter_expired = '1' or tq_reset = '1') 
                                             <---------LHS---------->    <----RHS----->

	LHS	RHS	Count	Threshold
Bin	False	False	323308239	1
Bin	False	True	14206880	1
Bin	True	False	201826628	1

"=" expression

172: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

175: if (ctrs_en = '1') then

	Evaluated to	Count	Threshold
Bin	False	1600	1
Bin	True	526372700	1

"=" expression

189: segm_counter_d <= C_BT_ZEROES when (bt_reset = '1') else

	Evaluated to	Count	Threshold
Bin	False	305685553	1
Bin	True	44204459	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	211652475	1
Bin	True	26052652	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	112413078	1
Bin	True	125292049	1

"=" expression

192: segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1')

	Evaluated to	Count	Threshold
Bin	False	17123	1
Bin	True	237688004	1

"and" expression

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
                                                         <-----LHS----->     <----RHS---->

	LHS	RHS	Count	Threshold
Bin	False	True	112403260	1
Bin	True	False	7305	1
Bin	True	True	125284744	1

"or" expression

192:    segm_counter_ce <= '1' when (bt_reset = '1') or (tq_edge_i = '1' and ctrs_en = '1') 
                                     <----LHS----->      <--------------RHS-------------->

	LHS	RHS	Count	Threshold
Bin	False	False	102613825	1
Bin	False	True	109038650	1
Bin	True	False	9806558	1

"=" expression

198: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

201: if (segm_counter_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	220704906	1
Bin	True	305669394	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.PRESCALER_INST.BIT_TIME_COUNTERS_NBT_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/prescaler/bit_time_counters.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

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Port:

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Port:

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Signal:

Signal:

Signal:

Signal:

Signal:

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Signal:

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Signal: