NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Nested Instances	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CLK_GATE_TXT_BUFFER_RAM_COMP	100.0 % (5/5)	100.0 % (2/2)	100.0 % (10/10)	100.0 % (8/8)	N.A.	N.A.	100.0 % (25/25)
TXT_BUFFER_RAM_INST	100.0 % (52/52)	100.0 % (38/38)	100.0 % (2160/2160)	93.1 % (54/58)	N.A.	N.A.	99.8 % (2304/2308)
TXT_BUFFER_FSM_INST	100.0 % (80/80)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (411/411)

Nested Instances

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CLK_GATE_TXT_BUFFER_RAM_COMP

100.0 % (5/5)

100.0 % (2/2)

100.0 % (10/10)

100.0 % (8/8)

N.A.

100.0 % (25/25)

TXT_BUFFER_RAM_INST

100.0 % (52/52)

100.0 % (38/38)

100.0 % (2160/2160)

93.1 % (54/58)

N.A.

99.8 % (2304/2308)

TXT_BUFFER_FSM_INST

100.0 % (80/80)

100.0 % (94/94)

100.0 % (70/70)

100.0 % (151/151)

100.0 % (16/16)

N.A.

100.0 % (411/411)

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST	100.0 % (32/32)	100.0 % (20/20)	100.0 % (462/462)	100.0 % (53/53)	N.A.	N.A.	100.0 % (567/567)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

100.0 % (32/32)

100.0 % (20/20)

100.0 % (462/462)

100.0 % (53/53)

N.A.

100.0 % (567/567)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

246:    txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') 
247:                             else 
248:                         '0';

Count: 94358
Threshold: 1

Signal assignment statement on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
Count: 45395
Threshold: 1

Signal assignment statement on line 248:

248: '0';
Count: 48963
Threshold: 1

If statement on lines 259 to 261:

259:    txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') 
260:                                                   else 
261:                                    (others => '0');

Count: 21376
Threshold: 1

Signal assignment statement on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
Count: 5991
Threshold: 1

Signal assignment statement on line 261:

261: (others => '0');
Count: 15385
Threshold: 1

If statement on lines 269 to 273:

269:    txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') 
270:                           else 
271:                       '1' when (mr_tst_control_tmaena = '1') 
272:                           else 
273:                       '0';

Count: 150504
Threshold: 1

Signal assignment statement on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
Count: 73296
Threshold: 1

Signal assignment statement on line 271:

271: '1' when (mr_tst_control_tmaena = '1')
Count: 636
Threshold: 1

Signal assignment statement on line 273:

273: '0';
Count: 76572
Threshold: 1

If statement on lines 280 to 284:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID) 
283:                                     else 
284:                                 '0';

Count: 145216
Threshold: 1

Signal assignment statement on line 280:

280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
Count: 415
Threshold: 1

Signal assignment statement on line 284:

284: '0';
Count: 144801
Threshold: 1

Signal assignment statement on line 286:

286: txtb_parity_error_valid <= txtb_parity_error_valid_i;
Count: 2150
Threshold: 1

If statement on lines 294 to 302:

294:        if (res_n = '0') then 
295:            mr_tx_command_txce_q <= '0'; 
...
301:            mr_tx_command_txca_q <= mr_tx_command_txca; 
302:        end if;

Count: 165318284
Threshold: 1

Signal assignment statement on line 295:

295: mr_tx_command_txce_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 296:

296: mr_tx_command_txcr_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 297:

297: mr_tx_command_txca_q <= '0';
Count: 1737682
Threshold: 1

Signal assignment statement on line 299:

299: mr_tx_command_txce_q <= mr_tx_command_txce;
Count: 81788549
Threshold: 1

Signal assignment statement on line 300:

300: mr_tx_command_txcr_q <= mr_tx_command_txcr;
Count: 81788549
Threshold: 1

Signal assignment statement on line 301:

301: mr_tx_command_txca_q <= mr_tx_command_txca;
Count: 81788549
Threshold: 1

If statement on lines 305 to 307:

305:    tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') 
306:                                 else 
307:                             '0';

Count: 3320
Threshold: 1

Signal assignment statement on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
Count: 96
Threshold: 1

Signal assignment statement on line 307:

307: '0';
Count: 3224
Threshold: 1

If statement on lines 308 to 310:

308:    tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') 
309:                                 else 
310:                             '0';

Count: 21844
Threshold: 1

Signal assignment statement on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
Count: 1102
Threshold: 1

Signal assignment statement on line 310:

310: '0';
Count: 20742
Threshold: 1

If statement on lines 312 to 314:

312:    abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') 
313:                         else 
314:                     '0';

Count: 5632
Threshold: 1

Signal assignment statement on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
Count: 181
Threshold: 1

Signal assignment statement on line 314:

314: '0';
Count: 5451
Threshold: 1

Signal assignment statement on line 317:

317: abort_or_skipped <= abort_applied;
Count: 1682
Threshold: 1

Signal assignment statement on line 405:

405: txtb_parity_mismatch <= parity_mismatch;
Count: 4590
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')

	Evaluated to	Count	Threshold
Bin	True	45395	1
Bin	False	48963	1

"if" / "when" / "else" condition on line 259:

259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')

	Evaluated to	Count	Threshold
Bin	True	5991	1
Bin	False	15385	1

"if" / "when" / "else" condition on line 269:

269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')

	Evaluated to	Count	Threshold
Bin	True	73296	1
Bin	False	77208	1

"if" / "when" / "else" condition on line 271:

271: '1' when (mr_tst_control_tmaena = '1')

	Evaluated to	Count	Threshold
Bin	True	636	1
Bin	False	76572	1

"if" / "when" / "else" condition on lines 280 to 282:

280:    txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and 
281:                                           txtb_parity_check_valid = '1' and 
282:                                           txtb_index_muxed = G_ID)

	Evaluated to	Count	Threshold
Bin	True	415	1
Bin	False	144801	1

"if" / "when" / "else" condition on line 294:

294: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	1737682	1
Bin	False	163580602	1

"if" / "when" / "else" condition on line 298:

298: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	81788549	1
Bin	False	81792053	1

"if" / "when" / "else" condition on line 305:

305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	96	1
Bin	False	3224	1

"if" / "when" / "else" condition on line 308:

308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	1102	1
Bin	False	20742	1

"if" / "when" / "else" condition on line 312:

312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')

	Evaluated to	Count	Threshold
Bin	True	181	1
Bin	False	5451	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RES_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SCAN_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_BMM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_TXBBM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXCA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TX_COMMAND_TXBI

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_TST_DEST_TST_ADDR

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_DEST_TST_MTGT

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

MR_TST_WDATA_TST_WDATA

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_DATA_IN

	Element	From	To	Threshold	Excluded due to
Bin	(31)	0	1	1	Exclude file
Bin	(31)	1	0	1	Exclude file
Bin	(30)	0	1	1	Exclude file
Bin	(30)	1	0	1	Exclude file
Bin	(29)	0	1	1	Exclude file
Bin	(29)	1	0	1	Exclude file
Bin	(28)	0	1	1	Exclude file
Bin	(28)	1	0	1	Exclude file
Bin	(27)	0	1	1	Exclude file
Bin	(27)	1	0	1	Exclude file
Bin	(26)	0	1	1	Exclude file
Bin	(26)	1	0	1	Exclude file
Bin	(25)	0	1	1	Exclude file
Bin	(25)	1	0	1	Exclude file
Bin	(24)	0	1	1	Exclude file
Bin	(24)	1	0	1	Exclude file
Bin	(23)	0	1	1	Exclude file
Bin	(23)	1	0	1	Exclude file
Bin	(22)	0	1	1	Exclude file
Bin	(22)	1	0	1	Exclude file
Bin	(21)	0	1	1	Exclude file
Bin	(21)	1	0	1	Exclude file
Bin	(20)	0	1	1	Exclude file
Bin	(20)	1	0	1	Exclude file
Bin	(19)	0	1	1	Exclude file
Bin	(19)	1	0	1	Exclude file
Bin	(18)	0	1	1	Exclude file
Bin	(18)	1	0	1	Exclude file
Bin	(17)	0	1	1	Exclude file
Bin	(17)	1	0	1	Exclude file
Bin	(16)	0	1	1	Exclude file
Bin	(16)	1	0	1	Exclude file
Bin	(15)	0	1	1	Exclude file
Bin	(15)	1	0	1	Exclude file
Bin	(14)	0	1	1	Exclude file
Bin	(14)	1	0	1	Exclude file
Bin	(13)	0	1	1	Exclude file
Bin	(13)	1	0	1	Exclude file
Bin	(12)	0	1	1	Exclude file
Bin	(12)	1	0	1	Exclude file
Bin	(11)	0	1	1	Exclude file
Bin	(11)	1	0	1	Exclude file
Bin	(10)	0	1	1	Exclude file
Bin	(10)	1	0	1	Exclude file
Bin	(9)	0	1	1	Exclude file
Bin	(9)	1	0	1	Exclude file
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_A_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_A_BE

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PORT_B_ADDRESS

	Element	From	To	Threshold	Excluded due to
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

TXTB_PORT_B_CLK_EN

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_BUS_OFF

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_PARITY_CHECK_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	493	1
Bin	(31)	1	0	1153	1
Bin	(30)	0	1	492	1
Bin	(30)	1	0	1152	1
Bin	(29)	0	1	482	1
Bin	(29)	1	0	1142	1
Bin	(28)	0	1	560	1
Bin	(28)	1	0	1220	1
Bin	(27)	0	1	533	1
Bin	(27)	1	0	1193	1
Bin	(26)	0	1	552	1
Bin	(26)	1	0	1212	1
Bin	(25)	0	1	552	1
Bin	(25)	1	0	1212	1
Bin	(24)	0	1	565	1
Bin	(24)	1	0	1225	1
Bin	(23)	0	1	572	1
Bin	(23)	1	0	1232	1
Bin	(22)	0	1	537	1
Bin	(22)	1	0	1197	1
Bin	(21)	0	1	560	1
Bin	(21)	1	0	1220	1
Bin	(20)	0	1	540	1
Bin	(20)	1	0	1200	1
Bin	(19)	0	1	573	1
Bin	(19)	1	0	1233	1
Bin	(18)	0	1	574	1
Bin	(18)	1	0	1234	1
Bin	(17)	0	1	519	1
Bin	(17)	1	0	1179	1
Bin	(16)	0	1	527	1
Bin	(16)	1	0	1187	1
Bin	(15)	0	1	525	1
Bin	(15)	1	0	1185	1
Bin	(14)	0	1	529	1
Bin	(14)	1	0	1189	1
Bin	(13)	0	1	516	1
Bin	(13)	1	0	1176	1
Bin	(12)	0	1	524	1
Bin	(12)	1	0	1184	1
Bin	(11)	0	1	525	1
Bin	(11)	1	0	1185	1
Bin	(10)	0	1	506	1
Bin	(10)	1	0	1166	1
Bin	(9)	0	1	528	1
Bin	(9)	1	0	1188	1
Bin	(8)	0	1	518	1
Bin	(8)	1	0	1178	1
Bin	(7)	0	1	573	1
Bin	(7)	1	0	1233	1
Bin	(6)	0	1	554	1
Bin	(6)	1	0	1214	1
Bin	(5)	0	1	510	1
Bin	(5)	1	0	1170	1
Bin	(4)	0	1	529	1
Bin	(4)	1	0	1189	1
Bin	(3)	0	1	536	1
Bin	(3)	1	0	1196	1
Bin	(2)	0	1	549	1
Bin	(2)	1	0	1209	1
Bin	(1)	0	1	562	1
Bin	(1)	1	0	1222	1
Bin	(0)	0	1	528	1
Bin	(0)	1	0	1188	1

Port:

TXTB_STATE

	Element	From	To	Count	Threshold
Bin	(3)	0	1	1089	1
Bin	(3)	1	0	429	1
Bin	(2)	0	1	777	1
Bin	(2)	1	0	1437	1
Bin	(1)	0	1	974	1
Bin	(1)	1	0	1634	1
Bin	(0)	0	1	966	1
Bin	(0)	1	0	1626	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	699	1
Bin	1	0	1359	1

Port:

TXTB_HW_CMD

	Element	From	To	Count	Threshold
Bin	LOCK	0	1	10075	1
Bin	LOCK	1	0	10735	1
Bin	VALID	0	1	3820	1
Bin	VALID	1	0	4480	1
Bin	ERR	0	1	1122	1
Bin	ERR	1	0	1782	1
Bin	ARBL	0	1	44	1
Bin	ARBL	1	0	704	1
Bin	FAILED	0	1	5081	1
Bin	FAILED	1	0	5741	1

Port:

TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	293	1
Bin	(31)	1	0	953	1
Bin	(30)	0	1	303	1
Bin	(30)	1	0	963	1
Bin	(29)	0	1	324	1
Bin	(29)	1	0	984	1
Bin	(28)	0	1	1079	1
Bin	(28)	1	0	1739	1
Bin	(27)	0	1	1169	1
Bin	(27)	1	0	1829	1
Bin	(26)	0	1	1203	1
Bin	(26)	1	0	1863	1
Bin	(25)	0	1	1110	1
Bin	(25)	1	0	1770	1
Bin	(24)	0	1	1153	1
Bin	(24)	1	0	1813	1
Bin	(23)	0	1	921	1
Bin	(23)	1	0	1581	1
Bin	(22)	0	1	972	1
Bin	(22)	1	0	1632	1
Bin	(21)	0	1	1154	1
Bin	(21)	1	0	1814	1
Bin	(20)	0	1	1157	1
Bin	(20)	1	0	1817	1
Bin	(19)	0	1	1184	1
Bin	(19)	1	0	1844	1
Bin	(18)	0	1	1076	1
Bin	(18)	1	0	1736	1
Bin	(17)	0	1	761	1
Bin	(17)	1	0	1421	1
Bin	(16)	0	1	796	1
Bin	(16)	1	0	1456	1
Bin	(15)	0	1	716	1
Bin	(15)	1	0	1376	1
Bin	(14)	0	1	790	1
Bin	(14)	1	0	1450	1
Bin	(13)	0	1	776	1
Bin	(13)	1	0	1436	1
Bin	(12)	0	1	797	1
Bin	(12)	1	0	1457	1
Bin	(11)	0	1	819	1
Bin	(11)	1	0	1479	1
Bin	(10)	0	1	987	1
Bin	(10)	1	0	1647	1
Bin	(9)	0	1	1086	1
Bin	(9)	1	0	1746	1
Bin	(8)	0	1	898	1
Bin	(8)	1	0	1558	1
Bin	(7)	0	1	1457	1
Bin	(7)	1	0	2117	1
Bin	(6)	0	1	1317	1
Bin	(6)	1	0	1977	1
Bin	(5)	0	1	1050	1
Bin	(5)	1	0	1710	1
Bin	(4)	0	1	934	1
Bin	(4)	1	0	1594	1
Bin	(3)	0	1	1036	1
Bin	(3)	1	0	1696	1
Bin	(2)	0	1	1115	1
Bin	(2)	1	0	1775	1
Bin	(1)	0	1	1325	1
Bin	(1)	1	0	1985	1
Bin	(0)	0	1	1212	1
Bin	(0)	1	0	1872	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	1037	1
Bin	1	0	1697	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	884	1
Bin	1	0	1544	1

Port:

TXTB_PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1635	1
Bin	1	0	2295	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	415	1
Bin	1	0	1075	1

Signal:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	1544	1
Bin	1	0	884	1

Signal:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	884	1
Bin	1	0	1544	1

Signal:

TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	1015	1
Bin	(31)	1	0	1635	1
Bin	(30)	0	1	1063	1
Bin	(30)	1	0	1683	1
Bin	(29)	0	1	977	1
Bin	(29)	1	0	1597	1
Bin	(28)	0	1	2792	1
Bin	(28)	1	0	3399	1
Bin	(27)	0	1	2892	1
Bin	(27)	1	0	3501	1
Bin	(26)	0	1	2755	1
Bin	(26)	1	0	3360	1
Bin	(25)	0	1	2709	1
Bin	(25)	1	0	3317	1
Bin	(24)	0	1	2966	1
Bin	(24)	1	0	3571	1
Bin	(23)	0	1	2592	1
Bin	(23)	1	0	3199	1
Bin	(22)	0	1	2633	1
Bin	(22)	1	0	3243	1
Bin	(21)	0	1	3175	1
Bin	(21)	1	0	3775	1
Bin	(20)	0	1	2748	1
Bin	(20)	1	0	3348	1
Bin	(19)	0	1	3251	1
Bin	(19)	1	0	3849	1
Bin	(18)	0	1	2660	1
Bin	(18)	1	0	3267	1
Bin	(17)	0	1	2228	1
Bin	(17)	1	0	2843	1
Bin	(16)	0	1	2243	1
Bin	(16)	1	0	2859	1
Bin	(15)	0	1	2054	1
Bin	(15)	1	0	2671	1
Bin	(14)	0	1	2312	1
Bin	(14)	1	0	2928	1
Bin	(13)	0	1	2251	1
Bin	(13)	1	0	2865	1
Bin	(12)	0	1	2078	1
Bin	(12)	1	0	2693	1
Bin	(11)	0	1	1928	1
Bin	(11)	1	0	2546	1
Bin	(10)	0	1	2386	1
Bin	(10)	1	0	3001	1
Bin	(9)	0	1	2720	1
Bin	(9)	1	0	3319	1
Bin	(8)	0	1	2581	1
Bin	(8)	1	0	3192	1
Bin	(7)	0	1	3743	1
Bin	(7)	1	0	4328	1
Bin	(6)	0	1	3412	1
Bin	(6)	1	0	4003	1
Bin	(5)	0	1	3212	1
Bin	(5)	1	0	3820	1
Bin	(4)	0	1	2429	1
Bin	(4)	1	0	3042	1
Bin	(3)	0	1	2837	1
Bin	(3)	1	0	3442	1
Bin	(2)	0	1	3033	1
Bin	(2)	1	0	3631	1
Bin	(1)	0	1	3175	1
Bin	(1)	1	0	3772	1
Bin	(0)	0	1	3518	1
Bin	(0)	1	0	4116	1

Signal:

TXTB_PARITY_ERROR_VALID_I

	From	To	Count	Threshold
Bin	0	1	415	1
Bin	1	0	1075	1

Signal:

MR_TX_COMMAND_TXCE_Q

	From	To	Count	Threshold
Bin	0	1	340	1
Bin	1	0	1000	1

Signal:

MR_TX_COMMAND_TXCR_Q

	From	To	Count	Threshold
Bin	0	1	9602	1
Bin	1	0	10262	1

Signal:

MR_TX_COMMAND_TXCA_Q

	From	To	Count	Threshold
Bin	0	1	1496	1
Bin	1	0	2156	1

Signal:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	96	1
Bin	1	0	756	1

Signal:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	1102	1
Bin	1	0	1762	1

Signal:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Signal:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	181	1
Bin	1	0	841	1

Signal:

TXTB_PORT_A_WRITE

	From	To	Count	Threshold
Bin	0	1	45395	1
Bin	1	0	46055	1

Signal:

TXTB_RAM_CLK_EN

	From	To	Count	Threshold
Bin	0	1	73932	1
Bin	1	0	74592	1

Signal:

CLK_RAM

	From	To	Count	Threshold
Bin	0	1	14859928	1
Bin	1	0	14860588	1

Signal:

PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	1635	1
Bin	1	0	2295	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression on line 246:

 txtb_port_a_cs = '1' and txtb_user_accessible = '1' 
 <-------LHS-------->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	46939	1
Bin	True	False	240	1
Bin	True	True	45395	1

"=" expression on line 246:

txtb_port_a_cs = '1'

	Evaluated to	Count	Threshold
Bin	False	48723	1
Bin	True	45635	1

"=" expression on line 246:

txtb_user_accessible = '1'

	Evaluated to	Count	Threshold
Bin	False	2024	1
Bin	True	92334	1

"=" expression on line 259:

txtb_unmask_data_ram = '1'

	Evaluated to	Count	Threshold
Bin	False	15385	1
Bin	True	5991	1

"or" expression on line 269:

 txtb_port_b_clk_en = '1' or txtb_port_a_write = '1' 
 <---------LHS---------->    <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	False	77208	1
Bin	False	True	45395	1
Bin	True	False	27901	1

"=" expression on line 269:

txtb_port_b_clk_en = '1'

	Evaluated to	Count	Threshold
Bin	False	122603	1
Bin	True	27901	1

"=" expression on line 269:

txtb_port_a_write = '1'

	Evaluated to	Count	Threshold
Bin	False	105109	1
Bin	True	45395	1

"=" expression on line 271:

mr_tst_control_tmaena = '1'

	Evaluated to	Count	Threshold
Bin	False	76572	1
Bin	True	636	1

"and" expression on lines 280 to 282:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' and txtb_index_muxed = G_ID 
 <-------------------------LHS------------------------->     <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	11884	1
Bin	True	False	2054	1
Bin	True	True	415	1

"and" expression on lines 280 to 281:

 parity_mismatch = '1' and txtb_parity_check_valid = '1' 
 <--------LHS-------->     <------------RHS------------>

	LHS	RHS	Count	Threshold
Bin	False	True	58904	1
Bin	True	False	2894	1
Bin	True	True	2469	1

"=" expression on line 280:

parity_mismatch = '1'

	Evaluated to	Count	Threshold
Bin	False	139853	1
Bin	True	5363	1

"=" expression on line 281:

txtb_parity_check_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	83843	1
Bin	True	61373	1

"=" expression on line 282:

txtb_index_muxed = G_ID

	Evaluated to	Count	Threshold
Bin	False	132917	1
Bin	True	12299	1

"=" expression on line 294:

res_n = '0'

	Evaluated to	Count	Threshold
Bin	False	163580602	1
Bin	True	1737682	1

"and" expression on line 305:

 mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	410	1
Bin	True	False	260	1
Bin	True	True	96	1

"=" expression on line 305:

mr_tx_command_txce_q = '1'

	Evaluated to	Count	Threshold
Bin	False	2964	1
Bin	True	356	1

"=" expression on line 305:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	2814	1
Bin	True	506	1

"and" expression on line 308:

 mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	882	1
Bin	True	False	9050	1
Bin	True	True	1102	1

"=" expression on line 308:

mr_tx_command_txcr_q = '1'

	Evaluated to	Count	Threshold
Bin	False	11692	1
Bin	True	10152	1

"=" expression on line 308:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	19860	1
Bin	True	1984	1

"and" expression on line 312:

 mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1' 
 <----------LHS----------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	511	1
Bin	True	False	1315	1
Bin	True	True	181	1

"=" expression on line 312:

mr_tx_command_txca_q = '1'

	Evaluated to	Count	Threshold
Bin	False	4136	1
Bin	True	1496	1

"=" expression on line 312:

mr_tx_command_txbi = '1'

	Evaluated to	Count	Threshold
Bin	False	4940	1
Bin	True	692	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_top_level.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 246 to 248:

Signal assignment statement on line 246:

Signal assignment statement on line 248:

If statement on lines 259 to 261:

Signal assignment statement on line 259:

Signal assignment statement on line 261:

If statement on lines 269 to 273:

Signal assignment statement on line 269:

Signal assignment statement on line 271:

Signal assignment statement on line 273:

If statement on lines 280 to 284:

Signal assignment statement on line 280:

Signal assignment statement on line 284:

Signal assignment statement on line 286:

If statement on lines 294 to 302:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Signal assignment statement on line 297:

Signal assignment statement on line 299:

Signal assignment statement on line 300:

Signal assignment statement on line 301:

If statement on lines 305 to 307:

Signal assignment statement on line 305:

Signal assignment statement on line 307:

If statement on lines 308 to 310:

Signal assignment statement on line 308:

Signal assignment statement on line 310:

If statement on lines 312 to 314:

Signal assignment statement on line 312:

Signal assignment statement on line 314:

Signal assignment statement on line 317:

Signal assignment statement on line 405:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 246:

"if" / "when" / "else" condition on line 259:

"if" / "when" / "else" condition on line 269:

"if" / "when" / "else" condition on line 271:

"if" / "when" / "else" condition on lines 280 to 282:

"if" / "when" / "else" condition on line 294:

"if" / "when" / "else" condition on line 298:

"if" / "when" / "else" condition on line 305:

"if" / "when" / "else" condition on line 308:

"if" / "when" / "else" condition on line 312:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port: