Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(2).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| CLK_GATE_TXT_BUFFER_RAM_COMP |
100.0 % (4/4) |
100.0 % (2/2) |
100.0 % (10/10) |
100.0 % (8/8) |
N.A. |
N.A. |
100.0 % (24/24) |
| TXT_BUFFER_RAM_INST |
100.0 % (51/51) |
100.0 % (38/38) |
100.0 % (2160/2160) |
100.0 % (62/62) |
N.A. |
N.A. |
100.0 % (2311/2311) |
| TXT_BUFFER_FSM_INST |
100.0 % (79/79) |
100.0 % (94/94) |
100.0 % (70/70) |
100.0 % (151/151) |
100.0 % (16/16) |
N.A. |
100.0 % (410/410) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
247: else
248: '0'; Count: 94720
Threshold: 1
Signal assignment statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') Count: 45533
Threshold: 1
Signal assignment statement:
248: '0'; Count: 49187
Threshold: 1
If statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
260: else
261: (others => '0'); Count: 21645
Threshold: 1
Signal assignment statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') Count: 6402
Threshold: 1
Signal assignment statement:
261: (others => '0'); Count: 15243
Threshold: 1
If statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
270: else
271: '1' when (mr_tst_control_tmaena = '1')
272: else
273: '0'; Count: 146400
Threshold: 1
Signal assignment statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') Count: 71244
Threshold: 1
Signal assignment statement:
271: '1' when (mr_tst_control_tmaena = '1') Count: 636
Threshold: 1
Signal assignment statement:
273: '0'; Count: 74520
Threshold: 1
If statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID)
283: else
284: '0'; Count: 138158
Threshold: 1
Signal assignment statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and Count: 396
Threshold: 1
Signal assignment statement:
284: '0'; Count: 137762
Threshold: 1
If statement:
294: if (res_n = '0') then
295: mr_tx_command_txce_q <= '0';
...
301: mr_tx_command_txca_q <= mr_tx_command_txca;
302: end if; Count: 162324562
Threshold: 1
Signal assignment statement:
295: mr_tx_command_txce_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
296: mr_tx_command_txcr_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
297: mr_tx_command_txca_q <= '0'; Count: 1737046
Threshold: 1
Signal assignment statement:
299: mr_tx_command_txce_q <= mr_tx_command_txce; Count: 80292006
Threshold: 1
Signal assignment statement:
300: mr_tx_command_txcr_q <= mr_tx_command_txcr; Count: 80292006
Threshold: 1
Signal assignment statement:
301: mr_tx_command_txca_q <= mr_tx_command_txca; Count: 80292006
Threshold: 1
If statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
306: else
307: '0'; Count: 3322
Threshold: 1
Signal assignment statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') Count: 96
Threshold: 1
Signal assignment statement:
307: '0'; Count: 3226
Threshold: 1
If statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
309: else
310: '0'; Count: 21226
Threshold: 1
Signal assignment statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') Count: 1143
Threshold: 1
Signal assignment statement:
310: '0'; Count: 20083
Threshold: 1
If statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
313: else
314: '0'; Count: 5634
Threshold: 1
Signal assignment statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') Count: 181
Threshold: 1
Signal assignment statement:
314: '0'; Count: 5453
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 45533 | 1 |
| Bin | False | 49187 | 1 |
"if" / "when" / "else" condition:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 6402 | 1 |
| Bin | False | 15243 | 1 |
"if" / "when" / "else" condition:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 71244 | 1 |
| Bin | False | 75156 | 1 |
"if" / "when" / "else" condition:
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 636 | 1 |
| Bin | False | 74520 | 1 |
"if" / "when" / "else" condition:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 396 | 1 |
| Bin | False | 137762 | 1 |
"if" / "when" / "else" condition:
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1737046 | 1 |
| Bin | False | 160587516 | 1 |
"if" / "when" / "else" condition:
298: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 80292006 | 1 |
| Bin | False | 80295510 | 1 |
"if" / "when" / "else" condition:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 96 | 1 |
| Bin | False | 3226 | 1 |
"if" / "when" / "else" condition:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1143 | 1 |
| Bin | False | 20083 | 1 |
"if" / "when" / "else" condition:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 181 | 1 |
| Bin | False | 5453 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 81158777 | 1 |
| Bin | 1 | 0 | 81159437 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2844 | 1 |
| Bin | 1 | 0 | 2844 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4 | 1 |
| Bin | 1 | 0 | 664 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12 | 1 |
| Bin | 1 | 0 | 672 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 32 | 1 |
| Bin | 1 | 0 | 692 | 1 |
Port:
MR_MODE_TXBBM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28 | 1 |
| Bin | 1 | 0 | 688 | 1 |
Port:
MR_SETTINGS_TBFBO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 784 | 1 |
| Bin | 1 | 0 | 124 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 110 | 1 |
| Bin | 1 | 0 | 770 | 1 |
Port:
MR_TX_COMMAND_TXCE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 340 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXCR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9340 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXCA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1496 | 1 |
| Bin | 1 | 0 | 11836 | 1 |
Port:
MR_TX_COMMAND_TXBI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 331 | 1 |
| Bin | 1 | 0 | 991 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 636 | 1 |
| Bin | 1 | 0 | 1296 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 31329 | 1 |
| Bin | 1 | 0 | 33257 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3406 | 1 |
| Bin | 1 | 0 | 4066 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4810 | 1 |
| Bin | 1 | 0 | 5470 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9862 | 1 |
| Bin | 1 | 0 | 10522 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21367 | 1 |
| Bin | 1 | 0 | 22027 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42723 | 1 |
| Bin | 1 | 0 | 43383 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 214 | 1 |
| Bin | 1 | 0 | 874 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 353 | 1 |
| Bin | 1 | 0 | 1013 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 472 | 1 |
| Bin | 1 | 0 | 1132 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 896 | 1 |
| Bin | 1 | 0 | 1556 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1490 | 1 |
| Bin | 1 | 0 | 2150 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1437 | 1 |
| Bin | 1 | 0 | 2097 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1448 | 1 |
| Bin | 1 | 0 | 2108 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1585 | 1 |
| Bin | 1 | 0 | 2245 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1607 | 1 |
| Bin | 1 | 0 | 2267 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1590 | 1 |
| Bin | 1 | 0 | 2250 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1603 | 1 |
| Bin | 1 | 0 | 2263 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1673 | 1 |
| Bin | 1 | 0 | 2333 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1542 | 1 |
| Bin | 1 | 0 | 2202 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1481 | 1 |
| Bin | 1 | 0 | 2141 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1519 | 1 |
| Bin | 1 | 0 | 2179 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1613 | 1 |
| Bin | 1 | 0 | 2273 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1608 | 1 |
| Bin | 1 | 0 | 2268 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1595 | 1 |
| Bin | 1 | 0 | 2255 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1591 | 1 |
| Bin | 1 | 0 | 2251 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1629 | 1 |
| Bin | 1 | 0 | 2289 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1530 | 1 |
| Bin | 1 | 0 | 2190 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1465 | 1 |
| Bin | 1 | 0 | 2125 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1515 | 1 |
| Bin | 1 | 0 | 2175 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1598 | 1 |
| Bin | 1 | 0 | 2258 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1604 | 1 |
| Bin | 1 | 0 | 2264 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1606 | 1 |
| Bin | 1 | 0 | 2266 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1630 | 1 |
| Bin | 1 | 0 | 2290 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1644 | 1 |
| Bin | 1 | 0 | 2304 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1589 | 1 |
| Bin | 1 | 0 | 2249 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1527 | 1 |
| Bin | 1 | 0 | 2187 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1554 | 1 |
| Bin | 1 | 0 | 2214 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1594 | 1 |
| Bin | 1 | 0 | 2254 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1602 | 1 |
| Bin | 1 | 0 | 2262 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1615 | 1 |
| Bin | 1 | 0 | 2275 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1616 | 1 |
| Bin | 1 | 0 | 2276 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1677 | 1 |
| Bin | 1 | 0 | 2337 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 486 | 1 |
| Bin | 1 | 0 | 1146 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 493 | 1 |
| Bin | 1 | 0 | 1153 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 469 | 1 |
| Bin | 1 | 0 | 1129 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 573 | 1 |
| Bin | 1 | 0 | 1233 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 550 | 1 |
| Bin | 1 | 0 | 1210 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 549 | 1 |
| Bin | 1 | 0 | 1209 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 558 | 1 |
| Bin | 1 | 0 | 1218 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 550 | 1 |
| Bin | 1 | 0 | 1210 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 555 | 1 |
| Bin | 1 | 0 | 1215 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 551 | 1 |
| Bin | 1 | 0 | 1211 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 562 | 1 |
| Bin | 1 | 0 | 1222 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 566 | 1 |
| Bin | 1 | 0 | 1226 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 528 | 1 |
| Bin | 1 | 0 | 1188 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 582 | 1 |
| Bin | 1 | 0 | 1242 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 520 | 1 |
| Bin | 1 | 0 | 1180 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 513 | 1 |
| Bin | 1 | 0 | 1173 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 508 | 1 |
| Bin | 1 | 0 | 1168 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 536 | 1 |
| Bin | 1 | 0 | 1196 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 516 | 1 |
| Bin | 1 | 0 | 1176 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 529 | 1 |
| Bin | 1 | 0 | 1189 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 532 | 1 |
| Bin | 1 | 0 | 1192 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 522 | 1 |
| Bin | 1 | 0 | 1182 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 534 | 1 |
| Bin | 1 | 0 | 1194 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 1174 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 552 | 1 |
| Bin | 1 | 0 | 1212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 533 | 1 |
| Bin | 1 | 0 | 1193 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 520 | 1 |
| Bin | 1 | 0 | 1180 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 546 | 1 |
| Bin | 1 | 0 | 1206 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 519 | 1 |
| Bin | 1 | 0 | 1179 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 552 | 1 |
| Bin | 1 | 0 | 1212 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 501 | 1 |
| Bin | 1 | 0 | 1161 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 545 | 1 |
| Bin | 1 | 0 | 1205 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26356 | 1 |
| Bin | 1 | 0 | 762824 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28657 | 1 |
| Bin | 1 | 0 | 760523 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 27152 | 1 |
| Bin | 1 | 0 | 762028 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44044 | 1 |
| Bin | 1 | 0 | 745136 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37637 | 1 |
| Bin | 1 | 0 | 751543 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35980 | 1 |
| Bin | 1 | 0 | 753200 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49211 | 1 |
| Bin | 1 | 0 | 739969 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36691 | 1 |
| Bin | 1 | 0 | 752489 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35471 | 1 |
| Bin | 1 | 0 | 753709 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44528 | 1 |
| Bin | 1 | 0 | 744652 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 38824 | 1 |
| Bin | 1 | 0 | 750356 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 37253 | 1 |
| Bin | 1 | 0 | 751927 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 64725 | 1 |
| Bin | 1 | 0 | 724455 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 84831 | 1 |
| Bin | 1 | 0 | 704349 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79950 | 1 |
| Bin | 1 | 0 | 709230 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141786 | 1 |
| Bin | 1 | 0 | 647394 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 33296 | 1 |
| Bin | 1 | 0 | 755884 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41814 | 1 |
| Bin | 1 | 0 | 747366 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 36216 | 1 |
| Bin | 1 | 0 | 752964 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40217 | 1 |
| Bin | 1 | 0 | 748963 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 58401 | 1 |
| Bin | 1 | 0 | 730779 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 61314 | 1 |
| Bin | 1 | 0 | 727866 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79096 | 1 |
| Bin | 1 | 0 | 710084 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 80705 | 1 |
| Bin | 1 | 0 | 708475 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 68788 | 1 |
| Bin | 1 | 0 | 720392 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 65064 | 1 |
| Bin | 1 | 0 | 724116 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 65949 | 1 |
| Bin | 1 | 0 | 723231 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83106 | 1 |
| Bin | 1 | 0 | 706074 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 90500 | 1 |
| Bin | 1 | 0 | 698680 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 100212 | 1 |
| Bin | 1 | 0 | 688968 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 165652 | 1 |
| Bin | 1 | 0 | 623528 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141015 | 1 |
| Bin | 1 | 0 | 648165 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 640015 | 1 |
| Bin | 1 | 0 | 149165 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 249017 | 1 |
| Bin | 1 | 0 | 24501565 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 396175 | 1 |
| Bin | 1 | 0 | 24354407 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 299014 | 1 |
| Bin | 1 | 0 | 24451568 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24194275 | 1 |
| Bin | 1 | 0 | 556307 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15940744 | 1 |
| Bin | 1 | 0 | 8809838 | 1 |
Port:
TXTB_PORT_A_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45773 | 1 |
| Bin | 1 | 0 | 46433 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24721305 | 1 |
| Bin | 1 | 0 | 28617 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24721613 | 1 |
| Bin | 1 | 0 | 28309 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24633047 | 1 |
| Bin | 1 | 0 | 116875 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24634059 | 1 |
| Bin | 1 | 0 | 115863 | 1 |
Port:
TXTB_STATE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1086 | 1 |
| Bin | 1 | 0 | 426 | 1 |
Port:
TXTB_STATE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 823 | 1 |
| Bin | 1 | 0 | 1483 | 1 |
Port:
TXTB_STATE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1022 | 1 |
| Bin | 1 | 0 | 1682 | 1 |
Port:
TXTB_STATE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1017 | 1 |
| Bin | 1 | 0 | 1677 | 1 |
Port:
TXTB_HW_CMD_INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 745 | 1 |
| Bin | 1 | 0 | 1405 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9751 | 1 |
| Bin | 1 | 0 | 10411 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3808 | 1 |
| Bin | 1 | 0 | 4468 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1091 | 1 |
| Bin | 1 | 0 | 1751 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44 | 1 |
| Bin | 1 | 0 | 704 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4800 | 1 |
| Bin | 1 | 0 | 5460 | 1 |
Port:
TXTB_HW_CMD_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 308 | 1 |
| Bin | 1 | 0 | 968 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 916 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 282 | 1 |
| Bin | 1 | 0 | 942 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 300 | 1 |
| Bin | 1 | 0 | 960 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1149 | 1 |
| Bin | 1 | 0 | 1809 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 941 | 1 |
| Bin | 1 | 0 | 1601 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1155 | 1 |
| Bin | 1 | 0 | 1815 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1108 | 1 |
| Bin | 1 | 0 | 1768 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1055 | 1 |
| Bin | 1 | 0 | 1715 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1182 | 1 |
| Bin | 1 | 0 | 1842 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1074 | 1 |
| Bin | 1 | 0 | 1734 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1221 | 1 |
| Bin | 1 | 0 | 1881 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1088 | 1 |
| Bin | 1 | 0 | 1748 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1225 | 1 |
| Bin | 1 | 0 | 1885 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1205 | 1 |
| Bin | 1 | 0 | 1865 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 737 | 1 |
| Bin | 1 | 0 | 1397 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 716 | 1 |
| Bin | 1 | 0 | 1376 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 614 | 1 |
| Bin | 1 | 0 | 1274 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 822 | 1 |
| Bin | 1 | 0 | 1482 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 706 | 1 |
| Bin | 1 | 0 | 1366 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 894 | 1 |
| Bin | 1 | 0 | 1554 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 792 | 1 |
| Bin | 1 | 0 | 1452 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 901 | 1 |
| Bin | 1 | 0 | 1561 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1213 | 1 |
| Bin | 1 | 0 | 1873 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 753 | 1 |
| Bin | 1 | 0 | 1413 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1502 | 1 |
| Bin | 1 | 0 | 2162 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1307 | 1 |
| Bin | 1 | 0 | 1967 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1170 | 1 |
| Bin | 1 | 0 | 1830 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 673 | 1 |
| Bin | 1 | 0 | 1333 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 994 | 1 |
| Bin | 1 | 0 | 1654 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1114 | 1 |
| Bin | 1 | 0 | 1774 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1308 | 1 |
| Bin | 1 | 0 | 1968 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1305 | 1 |
| Bin | 1 | 0 | 1965 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10515 | 1 |
| Bin | 1 | 0 | 11175 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 346 | 1 |
| Bin | 1 | 0 | 1006 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 15447 | 1 |
| Bin | 1 | 0 | 16107 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 12158 | 1 |
| Bin | 1 | 0 | 12158 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 34271 | 1 |
| Bin | 1 | 0 | 34931 | 1 |
Port:
TXTB_PORT_B_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25711 | 1 |
| Bin | 1 | 0 | 26371 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2960 | 1 |
| Bin | 1 | 0 | 2960 | 1 |
Port:
TXTB_AVAILABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1083 | 1 |
| Bin | 1 | 0 | 1743 | 1 |
Port:
TXTB_ALLOW_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 927 | 1 |
| Bin | 1 | 0 | 1587 | 1 |
Port:
TXTB_PARITY_CHECK_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56623 | 1 |
| Bin | 1 | 0 | 57283 | 1 |
Port:
TXTB_PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1580 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Port:
TXTB_PARITY_ERROR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 396 | 1 |
| Bin | 1 | 0 | 1056 | 1 |
Signal:
TXTB_USER_ACCESSIBLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1587 | 1 |
| Bin | 1 | 0 | 927 | 1 |
Signal:
TXTB_UNMASK_DATA_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 927 | 1 |
| Bin | 1 | 0 | 1587 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 973 | 1 |
| Bin | 1 | 0 | 1592 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1091 | 1 |
| Bin | 1 | 0 | 1711 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 993 | 1 |
| Bin | 1 | 0 | 1612 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2718 | 1 |
| Bin | 1 | 0 | 3327 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2695 | 1 |
| Bin | 1 | 0 | 3296 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2787 | 1 |
| Bin | 1 | 0 | 3394 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2562 | 1 |
| Bin | 1 | 0 | 3169 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2692 | 1 |
| Bin | 1 | 0 | 3300 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3012 | 1 |
| Bin | 1 | 0 | 3615 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2766 | 1 |
| Bin | 1 | 0 | 3367 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3130 | 1 |
| Bin | 1 | 0 | 3728 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2846 | 1 |
| Bin | 1 | 0 | 3450 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3322 | 1 |
| Bin | 1 | 0 | 3922 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3063 | 1 |
| Bin | 1 | 0 | 3669 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2398 | 1 |
| Bin | 1 | 0 | 3013 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2168 | 1 |
| Bin | 1 | 0 | 2784 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1899 | 1 |
| Bin | 1 | 0 | 2508 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2448 | 1 |
| Bin | 1 | 0 | 3064 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2061 | 1 |
| Bin | 1 | 0 | 2674 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2487 | 1 |
| Bin | 1 | 0 | 3100 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2085 | 1 |
| Bin | 1 | 0 | 2696 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2481 | 1 |
| Bin | 1 | 0 | 3092 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3211 | 1 |
| Bin | 1 | 0 | 3810 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2183 | 1 |
| Bin | 1 | 0 | 2793 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4011 | 1 |
| Bin | 1 | 0 | 4597 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3294 | 1 |
| Bin | 1 | 0 | 3888 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3111 | 1 |
| Bin | 1 | 0 | 3719 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1852 | 1 |
| Bin | 1 | 0 | 2466 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2671 | 1 |
| Bin | 1 | 0 | 3265 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3234 | 1 |
| Bin | 1 | 0 | 3837 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2781 | 1 |
| Bin | 1 | 0 | 3377 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3526 | 1 |
| Bin | 1 | 0 | 4121 | 1 |
Signal:
TXTB_PARITY_ERROR_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 396 | 1 |
| Bin | 1 | 0 | 1056 | 1 |
Signal:
MR_TX_COMMAND_TXCE_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 340 | 1 |
| Bin | 1 | 0 | 1000 | 1 |
Signal:
MR_TX_COMMAND_TXCR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 9292 | 1 |
| Bin | 1 | 0 | 9952 | 1 |
Signal:
MR_TX_COMMAND_TXCA_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1496 | 1 |
| Bin | 1 | 0 | 2156 | 1 |
Signal:
TX_COMMAND_TXCE_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 96 | 1 |
| Bin | 1 | 0 | 756 | 1 |
Signal:
TX_COMMAND_TXCR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1143 | 1 |
| Bin | 1 | 0 | 1803 | 1 |
Signal:
ABORT_APPLIED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 181 | 1 |
| Bin | 1 | 0 | 841 | 1 |
Signal:
ABORT_OR_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 181 | 1 |
| Bin | 1 | 0 | 841 | 1 |
Signal:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 45533 | 1 |
| Bin | 1 | 0 | 46193 | 1 |
Signal:
TXTB_RAM_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 71880 | 1 |
| Bin | 1 | 0 | 72540 | 1 |
Signal:
CLK_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 13641406 | 1 |
| Bin | 1 | 0 | 13642066 | 1 |
Signal:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1580 | 1 |
| Bin | 1 | 0 | 2240 | 1 |
Covered expressions:
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 48947 | 1 |
| Bin | True | 45773 | 1 |
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2067 | 1 |
| Bin | True | 92653 | 1 |
"and" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
<-------LHS--------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 47120 | 1 |
| Bin | True | False | 240 | 1 |
| Bin | True | True | 45533 | 1 |
"=" expression
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 15243 | 1 |
| Bin | True | 6402 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 120689 | 1 |
| Bin | True | 25711 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 100867 | 1 |
| Bin | True | 45533 | 1 |
"or" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 75156 | 1 |
| Bin | False | True | 45533 | 1 |
| Bin | True | False | 25711 | 1 |
"=" expression
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 74520 | 1 |
| Bin | True | 636 | 1 |
"=" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 132476 | 1 |
| Bin | True | 5682 | 1 |
"=" expression
281: txtb_parity_check_valid = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 80006 | 1 |
| Bin | True | 58152 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 55551 | 1 |
| Bin | True | False | 3081 | 1 |
| Bin | True | True | 2601 | 1 |
"=" expression
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 125393 | 1 |
| Bin | True | 12765 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 12369 | 1 |
| Bin | True | False | 2205 | 1 |
| Bin | True | True | 396 | 1 |
"=" expression
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 160587516 | 1 |
| Bin | True | 1737046 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2966 | 1 |
| Bin | True | 356 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2815 | 1 |
| Bin | True | 507 | 1 |
"and" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 411 | 1 |
| Bin | True | False | 260 | 1 |
| Bin | True | True | 96 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 11389 | 1 |
| Bin | True | 9837 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 19154 | 1 |
| Bin | True | 2072 | 1 |
"and" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 929 | 1 |
| Bin | True | False | 8694 | 1 |
| Bin | True | True | 1143 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4138 | 1 |
| Bin | True | 1496 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4941 | 1 |
| Bin | True | 693 | 1 |
"and" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 512 | 1 |
| Bin | True | False | 1315 | 1 |
| Bin | True | True | 181 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: