NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
PARITY_CALCULATOR_READ_INST	100.0 % (4/4)	N.A.	100.0 % (66/66)	100.0 % (4/4)	N.A.	N.A.	100.0 % (74/74)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN	100.0 % (10/10)	100.0 % (12/12)	N.A.	100.0 % (13/13)	N.A.	N.A.	100.0 % (35/35)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

225:            if (res_n = '0') then 
226:                parity_word <= (others => '0'); 
...
230:                end if; 
231:            end if;

Count: 657310
Threshold: 1

Signal assignment statement:

226: parity_word <= (others => '0');
Count: 428676
Threshold: 1

If statement:

228:                if (txtb_port_a_write = '1') then 
229:                    parity_word(to_integer(unsigned(txtb_port_a_address))) <= txtb_port_a_parity; 
230:                end if;

Count: 113791
Threshold: 1

Signal assignment statement:

229:                    parity_word(to_integer(unsigned(txtb_port_a_address))) <= txtb_port_a_parity;

Count: 1361
Threshold: 1

If statement:

254:            if (res_n = '0') then 
255:                parity_read_exp <= '0'; 
256:            elsif (rising_edge(clk_sys)) then 
257:                parity_read_exp <= parity_word(to_integer(unsigned(txtb_port_b_address))); 
258:            end if;

Count: 657310
Threshold: 1

Signal assignment statement:

255: parity_read_exp <= '0';
Count: 428676
Threshold: 1

Signal assignment statement:

257: parity_read_exp <= parity_word(to_integer(unsigned(txtb_port_b_address)));
Count: 113791
Threshold: 1

If statement:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1') 
262:                               else 
263:                           '0';

Count: 5527
Threshold: 1

Signal assignment statement:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

Count: 427
Threshold: 1

Signal assignment statement:

263: '0';
Count: 5100
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

225: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	428676	1
Bin	False	228634	1

"if" / "when" / "else" condition:

227: elsif rising_edge(clk_sys) then

	Evaluated to	Count	Threshold
Bin	True	113791	1
Bin	False	114843	1

"if" / "when" / "else" condition:

228: if (txtb_port_a_write = '1') then

	Evaluated to	Count	Threshold
Bin	True	1361	1
Bin	False	112430	1

"if" / "when" / "else" condition:

254: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	428676	1
Bin	False	228634	1

"if" / "when" / "else" condition:

256: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	113791	1
Bin	False	114843	1

"if" / "when" / "else" condition:

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	True	427	1
Bin	False	5100	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

225: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	228634	1
Bin	True	428676	1

"=" expression

228: if (txtb_port_a_write = '1') then

	Evaluated to	Count	Threshold
Bin	False	112430	1
Bin	True	1361	1

"=" expression

254: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	228634	1
Bin	True	428676	1

"/=" expression

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	False	2601	1
Bin	True	2926	1

"=" expression

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1')

	Evaluated to	Count	Threshold
Bin	False	4683	1
Bin	True	844	1

"and" expression

261:        parity_mismatch <= '1' when (parity_read_real /= parity_read_exp) and (mr_settings_pchke = '1') 
                                         <---------------LHS--------------->       <---------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	417	1
Bin	True	False	2499	1
Bin	True	True	427	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(5).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_RAM_INST.PARITY_TRUE_GEN

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_ram.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

If statement:

Signal assignment statement:

Signal assignment statement:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

"if" / "when" / "else" condition:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

"=" expression

"=" expression

"/=" expression

"=" expression

"and" expression

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: