NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST	100.0 % (79/79)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (410/410)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready)) 
178:                          else 
179:                      '0';

Count: 27448
Threshold: 1

Signal assignment statement:

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
Count: 16928
Threshold: 1

Signal assignment statement:

179: '0';
Count: 10520
Threshold: 1

If statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED) 
184:                        else 
185:                    '0';

Count: 21645
Threshold: 1

Signal assignment statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

Count: 5365
Threshold: 1

Signal assignment statement:

185: '0';
Count: 16280
Threshold: 1

If statement:

187:    txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 
188:                                 else 
189:                     (others => '0');

Count: 115241
Threshold: 1

Signal assignment statement:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
Count: 38826
Threshold: 1

Signal assignment statement:

189: (others => '0');
Count: 76415
Threshold: 1

If statement:

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
192:                   '0';

Count: 7364
Threshold: 1

Signal assignment statement:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
Count: 2082
Threshold: 1

Signal assignment statement:

192: '0';
Count: 5282
Threshold: 1

Signal assignment statement:

203: next_state <= curr_state;
Count: 101907
Threshold: 1

Sequential statement:

205:        case curr_state is 
206: 
...
360: 
361:        end case;

Count: 101907
Threshold: 1

If statement:

213:            if (tx_command_txcr_valid = '1') then 
214:                next_state <= s_txt_ready; 
215:            end if;

Count: 21751
Threshold: 1

Signal assignment statement:

214: next_state <= s_txt_ready;
Count: 4019
Threshold: 1

If statement:

223:            if (go_to_failed = '1') then 
224:                next_state <= s_txt_failed; 
...
242:                next_state <= s_txt_aborted; 
243:            end if;

Count: 28542
Threshold: 1

Signal assignment statement:

224: next_state <= s_txt_failed;
Count: 37
Threshold: 1

Signal assignment statement:

228: next_state <= s_txt_parity_err;
Count: 181
Threshold: 1

If statement:

234:                if (abort_applied = '1') then 
235:                    next_state <= s_txt_ab_prog; 
236:                else 
237:                    next_state <= s_txt_tx_prog; 
238:                end if;

Count: 8314
Threshold: 1

Signal assignment statement:

235: next_state <= s_txt_ab_prog;
Count: 5
Threshold: 1

Signal assignment statement:

237: next_state <= s_txt_tx_prog;
Count: 8309
Threshold: 1

Signal assignment statement:

242: next_state <= s_txt_aborted;
Count: 204
Threshold: 1

If statement:

251:            if (go_to_failed = '1') then 
252:                next_state <= s_txt_failed; 
...
276:                next_state <= s_txt_ab_prog; 
277:            end if;

Count: 27407
Threshold: 1

Signal assignment statement:

252: next_state <= s_txt_failed;
Count: 10
Threshold: 1

Signal assignment statement:

256: next_state <= s_txt_parity_err;
Count: 121
Threshold: 1

Signal assignment statement:

260: next_state <= s_txt_failed;
Count: 1825
Threshold: 1

Signal assignment statement:

264: next_state <= s_txt_ok;
Count: 4333
Threshold: 1

If statement:

268:                if (abort_applied = '1') then 
269:                    next_state <= s_txt_aborted; 
270:                else 
271:                    next_state <= s_txt_ready; 
272:                end if;

Count: 2051
Threshold: 1

Signal assignment statement:

269: next_state <= s_txt_aborted;
Count: 5
Threshold: 1

Signal assignment statement:

271: next_state <= s_txt_ready;
Count: 2046
Threshold: 1

Signal assignment statement:

276: next_state <= s_txt_ab_prog;
Count: 138
Threshold: 1

If statement:

285:            if (go_to_failed = '1') then 
286:                next_state <= s_txt_failed; 
...
302:                next_state <= s_txt_aborted; 
303:            end if;

Count: 302
Threshold: 1

Signal assignment statement:

286: next_state <= s_txt_failed;
Count: 5
Threshold: 1

Signal assignment statement:

290: next_state <= s_txt_parity_err;
Count: 4
Threshold: 1

Signal assignment statement:

294: next_state <= s_txt_failed;
Count: 24
Threshold: 1

Signal assignment statement:

298: next_state <= s_txt_ok;
Count: 15
Threshold: 1

Signal assignment statement:

302: next_state <= s_txt_aborted;
Count: 26
Threshold: 1

If statement:

311:            if (tx_command_txcr_valid = '1') then 
312:                next_state <= s_txt_ready; 
...
316:                next_state <= s_txt_empty; 
317:            end if;

Count: 8699
Threshold: 1

Signal assignment statement:

312: next_state <= s_txt_ready;
Count: 3320
Threshold: 1

Signal assignment statement:

316: next_state <= s_txt_empty;
Count: 25
Threshold: 1

If statement:

325:            if (tx_command_txcr_valid = '1') then 
326:                next_state <= s_txt_ready; 
...
330:                next_state <= s_txt_empty; 
331:            end if;

Count: 862
Threshold: 1

Signal assignment statement:

326: next_state <= s_txt_ready;
Count: 213
Threshold: 1

Signal assignment statement:

330: next_state <= s_txt_empty;
Count: 5
Threshold: 1

If statement:

339:            if (tx_command_txcr_valid = '1') then 
340:                next_state <= s_txt_ready; 
...
344:                next_state <= s_txt_empty; 
345:            end if;

Count: 14096
Threshold: 1

Signal assignment statement:

340: next_state <= s_txt_ready;
Count: 3737
Threshold: 1

Signal assignment statement:

344: next_state <= s_txt_empty;
Count: 55
Threshold: 1

If statement:

353:            if (tx_command_txcr_valid = '1') then 
354:                next_state <= s_txt_ready; 
...
358:                next_state <= s_txt_empty; 
359:            end if;

Count: 248
Threshold: 1

Signal assignment statement:

354: next_state <= s_txt_ready;
Count: 45
Threshold: 1

Signal assignment statement:

358: next_state <= s_txt_empty;
Count: 10
Threshold: 1

If statement:

368:    txt_fsm_ce <= '1' when (next_state /= curr_state) else 
369:                  '0';

Count: 63473
Threshold: 1

Signal assignment statement:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 30939
Threshold: 1

Signal assignment statement:

369: '0';
Count: 32534
Threshold: 1

If statement:

376:        if (res_n = '0') then 
377:            curr_state <= s_txt_empty; 
...
381:            end if; 
382:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

377: curr_state <= s_txt_empty;
Count: 2418499
Threshold: 1

If statement:

379:            if (txt_fsm_ce = '1') then 
380:                curr_state <= next_state; 
381:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

380: curr_state <= next_state;
Count: 23522
Threshold: 1

If statement:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog)) 
392:                                  else 
393:                            '1';

Count: 27448
Threshold: 1

Signal assignment statement:

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
Count: 16928
Threshold: 1

Signal assignment statement:

393: '1';
Count: 10520
Threshold: 1

If statement:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
...
406:                           else 
407:                       '0';

Count: 111122
Threshold: 1

Signal assignment statement:

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
Count: 24865
Threshold: 1

Signal assignment statement:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

Count: 44
Threshold: 1

Signal assignment statement:

407: '0';
Count: 86213
Threshold: 1

If statement:

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
412:                            else 
413:                        '0';

Count: 29506
Threshold: 1

Signal assignment statement:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
Count: 8560
Threshold: 1

Signal assignment statement:

413: '0';
Count: 20946
Threshold: 1

Sequential statement:

416:    with curr_state select txtb_state <= 
417:        TXT_RDY   when s_txt_ready, 
...
423:        TXT_ETY   when s_txt_empty, 
424:        TXT_PER   when s_txt_parity_err;

Count: 27448
Threshold: 1

Signal assignment statement:

417: TXT_RDY when s_txt_ready,
Count: 8555
Threshold: 1

Signal assignment statement:

418: TXT_TRAN when s_txt_tx_prog,
Count: 8304
Threshold: 1

Signal assignment statement:

419: TXT_ABTP when s_txt_ab_prog,
Count: 69
Threshold: 1

Signal assignment statement:

420: TXT_TOK when s_txt_ok,
Count: 4348
Threshold: 1

Signal assignment statement:

421: TXT_ERR when s_txt_failed,
Count: 1881
Threshold: 1

Signal assignment statement:

422: TXT_ABT when s_txt_aborted,
Count: 220
Threshold: 1

Signal assignment statement:

423: TXT_ETY when s_txt_empty,
Count: 4016
Threshold: 1

Signal assignment statement:

424: TXT_PER when s_txt_parity_err;
Count: 55
Threshold: 1

If statement:

432:    txtb_unmask_data_ram <= '1' when (transient_state = '1') 
433:                                else 
434:                            '0';

Count: 16218
Threshold: 1

Signal assignment statement:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
Count: 6509
Threshold: 1

Signal assignment statement:

434: '0';
Count: 9709
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	True	16928	1
Bin	False	10520	1

"if" / "when" / "else" condition:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	5365	1
Bin	False	16280	1

"if" / "when" / "else" condition:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	True	38826	1
Bin	False	76415	1

"if" / "when" / "else" condition:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	True	2082	1
Bin	False	5282	1

"case" / "with" / "select" choice:

210: when s_txt_empty =>

	Choice of	Count	Threshold
Bin	`s_txt_empty`	21751	1

"if" / "when" / "else" condition:

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4019	1
Bin	False	17732	1

"case" / "with" / "select" choice:

220: when s_txt_ready =>

	Choice of	Count	Threshold
Bin	`s_txt_ready`	28542	1

"if" / "when" / "else" condition:

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	37	1
Bin	False	28505	1

"if" / "when" / "else" condition:

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	181	1
Bin	False	28324	1

"if" / "when" / "else" condition:

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	8314	1
Bin	False	20010	1

"if" / "when" / "else" condition:

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	8309	1

"if" / "when" / "else" condition:

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	True	204	1
Bin	False	19806	1

"case" / "with" / "select" choice:

248: when s_txt_tx_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	27407	1

"if" / "when" / "else" condition:

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	27397	1

"if" / "when" / "else" condition:

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	121	1
Bin	False	27276	1

"if" / "when" / "else" condition:

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	1825	1
Bin	False	25451	1

"if" / "when" / "else" condition:

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4333	1
Bin	False	21118	1

"if" / "when" / "else" condition:

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	2051	1
Bin	False	19067	1

"if" / "when" / "else" condition:

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	2046	1

"if" / "when" / "else" condition:

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	138	1
Bin	False	18929	1

"case" / "with" / "select" choice:

282: when s_txt_ab_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	302	1

"if" / "when" / "else" condition:

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	297	1

"if" / "when" / "else" condition:

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4	1
Bin	False	293	1

"if" / "when" / "else" condition:

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	24	1
Bin	False	269	1

"if" / "when" / "else" condition:

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	15	1
Bin	False	254	1

"if" / "when" / "else" condition:

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	26	1
Bin	False	228	1

"case" / "with" / "select" choice:

308: when s_txt_failed =>

	Choice of	Count	Threshold
Bin	`s_txt_failed`	8699	1

"if" / "when" / "else" condition:

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3320	1
Bin	False	5379	1

"if" / "when" / "else" condition:

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	25	1
Bin	False	5354	1

"case" / "with" / "select" choice:

322: when s_txt_aborted =>

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	862	1

"if" / "when" / "else" condition:

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	213	1
Bin	False	649	1

"if" / "when" / "else" condition:

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	644	1

"case" / "with" / "select" choice:

336: when s_txt_ok =>

	Choice of	Count	Threshold
Bin	`s_txt_ok`	14096	1

"if" / "when" / "else" condition:

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	3737	1
Bin	False	10359	1

"if" / "when" / "else" condition:

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	55	1
Bin	False	10304	1

"case" / "with" / "select" choice:

350: when s_txt_parity_err =>

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	248	1

"if" / "when" / "else" condition:

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	45	1
Bin	False	203	1

"if" / "when" / "else" condition:

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	193	1

"if" / "when" / "else" condition:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	30939	1
Bin	False	32534	1

"if" / "when" / "else" condition:

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

378: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	23522	1
Bin	False	526350778	1

"if" / "when" / "else" condition:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	True	16928	1
Bin	False	10520	1

"if" / "when" / "else" condition:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	True	24865	1
Bin	False	86257	1

"if" / "when" / "else" condition:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	44	1
Bin	False	86213	1

"if" / "when" / "else" condition:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	True	8560	1
Bin	False	20946	1

"case" / "with" / "select" choice:

417: TXT_RDY when s_txt_ready,

	Choice of	Count	Threshold
Bin	`s_txt_ready`	8555	1

"case" / "with" / "select" choice:

418: TXT_TRAN when s_txt_tx_prog,

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	8304	1

"case" / "with" / "select" choice:

419: TXT_ABTP when s_txt_ab_prog,

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	69	1

"case" / "with" / "select" choice:

420: TXT_TOK when s_txt_ok,

	Choice of	Count	Threshold
Bin	`s_txt_ok`	4348	1

"case" / "with" / "select" choice:

421: TXT_ERR when s_txt_failed,

	Choice of	Count	Threshold
Bin	`s_txt_failed`	1881	1

"case" / "with" / "select" choice:

422: TXT_ABT when s_txt_aborted,

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	220	1

"case" / "with" / "select" choice:

423: TXT_ETY when s_txt_empty,

	Choice of	Count	Threshold
Bin	`s_txt_empty`	4016	1

"case" / "with" / "select" choice:

424: TXT_PER when s_txt_parity_err;

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	55	1

"if" / "when" / "else" condition:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	6509	1
Bin	False	9709	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_MODE_BMM

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	1615	1

Port:

MR_MODE_ROM

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1651	1

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold
Bin	0	1	2533	1
Bin	1	0	943	1

Port:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	104	1
Bin	1	0	1704	1

Port:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	11608	1
Bin	1	0	13208	1

Port:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	229	1
Bin	1	0	1829	1

Port:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	272	1
Bin	1	0	1872	1

Port:

TXTB_HW_CMD.LOCK

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

TXTB_HW_CMD.VALID

	From	To	Count	Threshold
Bin	0	1	11098	1
Bin	1	0	12698	1

Port:

TXTB_HW_CMD.ERR

	From	To	Count	Threshold
Bin	0	1	4237	1
Bin	1	0	5837	1

Port:

TXTB_HW_CMD.ARBL

	From	To	Count	Threshold
Bin	0	1	455	1
Bin	1	0	2055	1

Port:

TXTB_HW_CMD.FAILED

	From	To	Count	Threshold
Bin	0	1	9015	1
Bin	1	0	10615	1

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold
Bin	0	1	5600	1
Bin	1	0	7200	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8236	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	331	1
Bin	1	0	1931	1

Port:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	8109	1
Bin	1	0	6509	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	6509	1
Bin	1	0	8109	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	6270	1
Bin	1	0	7870	1

Port:

TXTB_STATE(3)

	From	To	Count	Threshold
Bin	0	1	4053	1
Bin	1	0	2453	1

Port:

TXTB_STATE(2)

	From	To	Count	Threshold
Bin	0	1	6449	1
Bin	1	0	8049	1

Port:

TXTB_STATE(1)

	From	To	Count	Threshold
Bin	0	1	8525	1
Bin	1	0	10125	1

Port:

TXTB_STATE(0)

	From	To	Count	Threshold
Bin	0	1	8417	1
Bin	1	0	10017	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	8560	1
Bin	1	0	10160	1

Port:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	6509	1
Bin	1	0	8109	1

Signal:

TXT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	30934	1
Bin	1	0	32534	1

Signal:

GO_TO_FAILED

	From	To	Count	Threshold
Bin	0	1	5218	1
Bin	1	0	5228	1

Signal:

TRANSIENT_STATE

	From	To	Count	Threshold
Bin	0	1	6509	1
Bin	1	0	8109	1

Port:

TXTB_HW_CMD_I.LOCK

	From	To	Count	Threshold
Bin	0	1	8309	1
Bin	1	0	9909	1

Port:

TXTB_HW_CMD_I.VALID

	From	To	Count	Threshold
Bin	0	1	4348	1
Bin	1	0	5948	1

Port:

TXTB_HW_CMD_I.ERR

	From	To	Count	Threshold
Bin	0	1	1875	1
Bin	1	0	3475	1

Port:

TXTB_HW_CMD_I.ARBL

	From	To	Count	Threshold
Bin	0	1	207	1
Bin	1	0	1807	1

Port:

TXTB_HW_CMD_I.FAILED

	From	To	Count	Threshold
Bin	0	1	1874	1
Bin	1	0	3474	1

Signal:

ARBL_OR_ERR

	From	To	Count	Threshold
Bin	0	1	2082	1
Bin	1	0	3682	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or

	Evaluated to	Count	Threshold
Bin	False	27379	1
Bin	True	69	1

"=" expression

176: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	19144	1
Bin	True	8304	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	19075	1
Bin	False	True	8304	1
Bin	True	False	69	1

"=" expression

177: (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	False	18893	1
Bin	True	8555	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	LHS	RHS	Count	Threshold
Bin	False	False	10520	1
Bin	False	True	8555	1
Bin	True	False	8373	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	10034	1
Bin	True	11611	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	13505	1
Bin	True	8140	1

"and" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
                                   <-----LHS------>     <----------------------RHS---------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	2877	1
Bin	True	False	6348	1
Bin	True	True	5263	1

"=" expression

182: mr_mode_bmm = BMM_ENABLED or

	Evaluated to	Count	Threshold
Bin	False	21595	1
Bin	True	50	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or

	LHS	RHS	Count	Threshold
Bin	False	False	16342	1
Bin	False	True	40	1
Bin	True	False	5253	1

"=" expression

183: mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	False	21548	1
Bin	True	97	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	LHS	RHS	Count	Threshold
Bin	False	False	16280	1
Bin	False	True	62	1
Bin	True	False	5268	1

"=" expression

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	False	76415	1
Bin	True	38826	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	5489	1
Bin	True	1875	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	7157	1
Bin	True	207	1

"or" expression

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
                                 <---------LHS--------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	5282	1
Bin	False	True	207	1
Bin	True	False	1875	1

"=" expression

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	17732	1
Bin	True	4019	1

"=" expression

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	28505	1
Bin	True	37	1

"=" expression

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	28324	1
Bin	True	181	1

"=" expression

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	20010	1
Bin	True	8314	1

"=" expression

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	8309	1
Bin	True	5	1

"=" expression

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	False	19806	1
Bin	True	204	1

"=" expression

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	27397	1
Bin	True	10	1

"=" expression

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	27276	1
Bin	True	121	1

"=" expression

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	25451	1
Bin	True	1825	1

"=" expression

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	21118	1
Bin	True	4333	1

"=" expression

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	19067	1
Bin	True	2051	1

"=" expression

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	2046	1
Bin	True	5	1

"=" expression

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	18929	1
Bin	True	138	1

"=" expression

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	297	1
Bin	True	5	1

"=" expression

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	293	1
Bin	True	4	1

"=" expression

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	269	1
Bin	True	24	1

"=" expression

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	254	1
Bin	True	15	1

"=" expression

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	228	1
Bin	True	26	1

"=" expression

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	5379	1
Bin	True	3320	1

"=" expression

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	5354	1
Bin	True	25	1

"=" expression

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	649	1
Bin	True	213	1

"=" expression

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	644	1
Bin	True	5	1

"=" expression

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	10359	1
Bin	True	3737	1

"=" expression

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	10304	1
Bin	True	55	1

"=" expression

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	203	1
Bin	True	45	1

"=" expression

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	193	1
Bin	True	10	1

"/=" expression

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	False	32534	1
Bin	True	30939	1

"=" expression

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526350778	1
Bin	True	23522	1

"=" expression

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or

	Evaluated to	Count	Threshold
Bin	False	18893	1
Bin	True	8555	1

"=" expression

390: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	19144	1
Bin	True	8304	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	10589	1
Bin	False	True	8304	1
Bin	True	False	8555	1

"=" expression

391: (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	False	27379	1
Bin	True	69	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	LHS	RHS	Count	Threshold
Bin	False	False	10520	1
Bin	False	True	69	1
Bin	True	False	16859	1

"=" expression

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely

	Evaluated to	Count	Threshold
Bin	False	103701	1
Bin	True	7421	1

"=" expression

397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	Evaluated to	Count	Threshold
Bin	False	93730	1
Bin	True	17392	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	LHS	RHS	Count	Threshold
Bin	False	False	86309	1
Bin	False	True	17392	1
Bin	True	False	7421	1

"=" expression

398: ((txtb_hw_cmd_i.arbl = '1' or

	Evaluated to	Count	Threshold
Bin	False	110496	1
Bin	True	626	1

"=" expression

399: txtb_hw_cmd_i.err = '1') and

	Evaluated to	Count	Threshold
Bin	False	105466	1
Bin	True	5656	1

"or" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and

	LHS	RHS	Count	Threshold
Bin	False	False	104840	1
Bin	False	True	5656	1
Bin	True	False	626	1

"=" expression

400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	False	110919	1
Bin	True	203	1

"and" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	True	151	1
Bin	True	False	6230	1
Bin	True	True	52	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	False	86257	1
Bin	False	True	52	1
Bin	True	False	24813	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	77874	1
Bin	True	8383	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	82580	1
Bin	True	3677	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
                                     <-----LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	3569	1
Bin	True	False	8275	1
Bin	True	True	108	1

"=" expression

405: transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	53691	1
Bin	True	32566	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	32522	1
Bin	True	False	64	1
Bin	True	True	44	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	20790	1
Bin	True	8716	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	2049	1
Bin	True	27457	1

"and" expression

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
                                       <---------LHS---------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	18897	1
Bin	True	False	156	1
Bin	True	True	8560	1

"=" expression

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	9709	1
Bin	True	6509	1

	State	Count	Threshold
Bin	S_TXT_EMPTY	5624	1
Bin	S_TXT_READY	13536	1
Bin	S_TXT_TX_PROG	8404	1
Bin	S_TXT_AB_PROG	74	1
Bin	S_TXT_OK	5952	1
Bin	S_TXT_FAILED	3474	1
Bin	S_TXT_ABORTED	247	1
Bin	S_TXT_PARITY_ERR	314	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(1).TXT_BUF_ODD_GEN.TXT_BUFFER_ODD_INST.TXT_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd

Sub-instances:

Current Instance:

Details:

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Uncovered statements:

Excluded statements:

Covered statements:

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