NVC code coverage report

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_INST

File:  /__w/ctu-can-regression/ctu-can-regression/test/main_tb/agents/functional_coverage_agent/func_cov_prescaler.vhd

Sub-instances:

Instance Statement Branch Toggle Expression FSM state Functional Average

Current Instance:

Instance Statement Branch Toggle Expression FSM state Functional Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.CTU_CAN_FD_VIP_INST.G_FUNC_COV.FUNC_COV_AGENT_INST.FUNC_COV_PRESCALER_INST N.A. N.A. 100.0 % (2/2) N.A. N.A. 100.0 % (25/25) 100.0 % (27/27)

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

 CLK
FromToCountThreshold
Bin015275788681
Bin105275804601

Uncovered expressions:

Excluded expressions:

Covered expressions:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage:

PSL cover point:

162:    -- psl nominal_sample_cov : cover 
163:    --  {sp_control = NOMINAL_SAMPLE}; 
Count: 395990106
Threshold: 1

PSL cover point:

165:    -- psl data_sample_cov : cover 
166:    --  {sp_control = DATA_SAMPLE}; 
Count: 122759063
Threshold: 1

PSL cover point:

168:    -- psl secondary_sample_cov : cover 
169:    --  {sp_control = SECONDARY_SAMPLE}; 
Count: 8829699
Threshold: 1

PSL cover point:

176:    -- psl minimal_bit_time_nbt_cov : cover 
177:    --  {to_integer(unsigned(tseg1_nbt)) = 5 and to_integer(unsigned(tseg2_nbt)) = 3 
178:    --   and to_integer(unsigned(brp_nbt)) = 1}; 
Count: 35185062
Threshold: 1

PSL cover point:

180:    -- psl minimal_bit_time_dbt_cov : cover 
181:    --  {to_integer(unsigned(tseg1_dbt)) = 3 and to_integer(unsigned(tseg2_dbt)) = 2 
182:    --   and to_integer(unsigned(brp_dbt)) = 1}; 
Count: 35296786
Threshold: 1

PSL cover point:

184:    -- psl maximal_bit_time_nbt_cov : cover 
185:    --  {to_integer(unsigned(tseg1_nbt)) = 191 and to_integer(unsigned(tseg2_nbt)) = 63}; 
Count: 157037866
Threshold: 1

PSL cover point:

187:    -- psl maximal_bit_time_dbt_cov : cover 
188:    --  {to_integer(unsigned(tseg1_dbt)) = 95 and to_integer(unsigned(tseg2_dbt)) = 31}; 
Count: 218434772
Threshold: 1

PSL cover point:

195:    -- psl brp_bin_1_1_cov : cover 
196:    --  {to_integer(unsigned(brp_nbt)) = 1 and to_integer(unsigned(brp_dbt)) = 1}; 
Count: 187192205
Threshold: 1

PSL cover point:

198:    -- psl brp_bin_2_1_cov : cover 
199:    --  {to_integer(unsigned(brp_nbt)) = 2 and to_integer(unsigned(brp_dbt)) = 1}; 
Count: 64994175
Threshold: 1

PSL cover point:

201:    -- psl brp_bin_3_1_cov : cover 
202:    --  {to_integer(unsigned(brp_nbt)) = 3 and to_integer(unsigned(brp_dbt)) = 1}; 
Count: 31555486
Threshold: 1

PSL cover point:

204:    -- psl brp_bin_4_1_cov : cover 
205:    --  {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 1}; 
Count: 76391326
Threshold: 1

PSL cover point:

207:    -- psl brp_bin_4_3_cov : cover 
208:    --  {to_integer(unsigned(brp_nbt)) = 4 and to_integer(unsigned(brp_dbt)) = 3}; 
Count: 3664521
Threshold: 1

PSL cover point:

215:    -- psl brp_nbt_max_cov : cover 
216:    --  {to_integer(unsigned(brp_nbt)) = 255}; 
Count: 556491
Threshold: 1

PSL cover point:

218:    -- psl brp_dbt_max_cov : cover 
219:    --  {to_integer(unsigned(brp_dbt)) = 255}; 
Count: 5863808
Threshold: 1

PSL cover point:

227:    -- psl pos_resync_in_nominal_bit_rate_cov : cover 
228:    --  {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = NOMINAL_SAMPLE}; 
Count: 302103
Threshold: 1

PSL cover point:

231:    -- psl neg_resync_in_nominal_bit_rate_cov : cover 
232:    --  {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = NOMINAL_SAMPLE}; 
Count: 10319
Threshold: 1

PSL cover point:

235:    -- psl neg_resync_in_data_bit_rate_cov : cover 
236:    --  {resync_edge_valid = '1' and is_tseg2 = '1' and sp_control = DATA_SAMPLE}; 
Count: 6429
Threshold: 1

PSL cover point:

239:    -- psl pos_resync_in_data_bit_rate_cov : cover 
240:    --  {resync_edge_valid = '1' and is_tseg1 = '1' and sp_control = DATA_SAMPLE}; 
Count: 399469
Threshold: 1

PSL cover point:

247:    -- psl h_sync_ignored_due_to_previous_sync_cov : cover 
248:    --  {sync_flag = '1' and h_sync_edge = '1'}; 
Count: 22
Threshold: 1

PSL cover point:

250:    -- psl re_sync_ignored_due_to_previous_sync_cov : cover 
251:    --  {sync_flag = '1' and resync_edge = '1'}; 
Count: 322
Threshold: 1

PSL cover point:

253:    -- psl h_sync_in_tseg_1_cov : cover 
254:    --  {h_sync_edge_valid = '1' and is_tseg1 = '1'}; 
Count: 42965
Threshold: 1

PSL cover point:

256:    -- psl h_sync_in_tseg_2_cov : cover 
257:    --  {h_sync_edge_valid = '1' and is_tseg2 = '1'}; 
Count: 7497
Threshold: 1

PSL cover point:

260:    -- psl re_sync_in_tseg_1_cov : cover 
261:    --  {resync_edge_valid = '1' and is_tseg1 = '1'}; 
Count: 701572
Threshold: 1

PSL cover point:

263:    -- psl re_sync_in_tseg_2_cov : cover 
264:    --  {resync_edge_valid = '1' and is_tseg2 = '1'}; 
Count: 16748
Threshold: 1

PSL cover point:

271:    -- psl tx_trigger_throttling_cov : cover 
272:    --  {rx_trig_req_q = '1' and tx_trig_req = '1'} 
273:    --  report "TX trigger throtlled!"; 
Count: 940
Threshold: 1