NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_FSM_INST	100.0 % (79/79)	100.0 % (94/94)	100.0 % (70/70)	100.0 % (151/151)	100.0 % (16/16)	N.A.	100.0 % (410/410)

Uncovered statements:

Excluded statements:

Covered statements:

If statement:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready)) 
178:                          else 
179:                      '0';

Count: 46139
Threshold: 1

Signal assignment statement:

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or
Count: 29018
Threshold: 1

Signal assignment statement:

179: '0';
Count: 17121
Threshold: 1

If statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED) 
184:                        else 
185:                    '0';

Count: 21645
Threshold: 1

Signal assignment statement:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

Count: 5365
Threshold: 1

Signal assignment statement:

185: '0';
Count: 16280
Threshold: 1

If statement:

187:    txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1') 
188:                                 else 
189:                     (others => '0');

Count: 115663
Threshold: 1

Signal assignment statement:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')
Count: 64794
Threshold: 1

Signal assignment statement:

189: (others => '0');
Count: 50869
Threshold: 1

If statement:

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
192:                   '0';

Count: 10518
Threshold: 1

Signal assignment statement:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else
Count: 2059
Threshold: 1

Signal assignment statement:

192: '0';
Count: 8459
Threshold: 1

Signal assignment statement:

203: next_state <= curr_state;
Count: 160273
Threshold: 1

Sequential statement:

205:        case curr_state is 
206: 
...
360: 
361:        end case;

Count: 160273
Threshold: 1

If statement:

213:            if (tx_command_txcr_valid = '1') then 
214:                next_state <= s_txt_ready; 
215:            end if;

Count: 24473
Threshold: 1

Signal assignment statement:

214: next_state <= s_txt_ready;
Count: 4581
Threshold: 1

If statement:

223:            if (go_to_failed = '1') then 
224:                next_state <= s_txt_failed; 
...
242:                next_state <= s_txt_aborted; 
243:            end if;

Count: 46242
Threshold: 1

Signal assignment statement:

224: next_state <= s_txt_failed;
Count: 97
Threshold: 1

Signal assignment statement:

228: next_state <= s_txt_parity_err;
Count: 262
Threshold: 1

If statement:

234:                if (abort_applied = '1') then 
235:                    next_state <= s_txt_ab_prog; 
236:                else 
237:                    next_state <= s_txt_tx_prog; 
238:                end if;

Count: 13951
Threshold: 1

Signal assignment statement:

235: next_state <= s_txt_ab_prog;
Count: 6
Threshold: 1

Signal assignment statement:

237: next_state <= s_txt_tx_prog;
Count: 13945
Threshold: 1

Signal assignment statement:

242: next_state <= s_txt_aborted;
Count: 266
Threshold: 1

If statement:

251:            if (go_to_failed = '1') then 
252:                next_state <= s_txt_failed; 
...
276:                next_state <= s_txt_ab_prog; 
277:            end if;

Count: 44772
Threshold: 1

Signal assignment statement:

252: next_state <= s_txt_failed;
Count: 10
Threshold: 1

Signal assignment statement:

256: next_state <= s_txt_parity_err;
Count: 102
Threshold: 1

Signal assignment statement:

260: next_state <= s_txt_failed;
Count: 6343
Threshold: 1

Signal assignment statement:

264: next_state <= s_txt_ok;
Count: 4828
Threshold: 1

If statement:

268:                if (abort_applied = '1') then 
269:                    next_state <= s_txt_aborted; 
270:                else 
271:                    next_state <= s_txt_ready; 
272:                end if;

Count: 2026
Threshold: 1

Signal assignment statement:

269: next_state <= s_txt_aborted;
Count: 5
Threshold: 1

Signal assignment statement:

271: next_state <= s_txt_ready;
Count: 2021
Threshold: 1

Signal assignment statement:

276: next_state <= s_txt_ab_prog;
Count: 1426
Threshold: 1

If statement:

285:            if (go_to_failed = '1') then 
286:                next_state <= s_txt_failed; 
...
302:                next_state <= s_txt_aborted; 
303:            end if;

Count: 2888
Threshold: 1

Signal assignment statement:

286: next_state <= s_txt_failed;
Count: 5
Threshold: 1

Signal assignment statement:

290: next_state <= s_txt_parity_err;
Count: 12
Threshold: 1

Signal assignment statement:

294: next_state <= s_txt_failed;
Count: 18
Threshold: 1

Signal assignment statement:

298: next_state <= s_txt_ok;
Count: 652
Threshold: 1

Signal assignment statement:

302: next_state <= s_txt_aborted;
Count: 32
Threshold: 1

If statement:

311:            if (tx_command_txcr_valid = '1') then 
312:                next_state <= s_txt_ready; 
...
316:                next_state <= s_txt_empty; 
317:            end if;

Count: 21948
Threshold: 1

Signal assignment statement:

312: next_state <= s_txt_ready;
Count: 7441
Threshold: 1

Signal assignment statement:

316: next_state <= s_txt_empty;
Count: 25
Threshold: 1

If statement:

325:            if (tx_command_txcr_valid = '1') then 
326:                next_state <= s_txt_ready; 
...
330:                next_state <= s_txt_empty; 
331:            end if;

Count: 1202
Threshold: 1

Signal assignment statement:

326: next_state <= s_txt_ready;
Count: 288
Threshold: 1

Signal assignment statement:

330: next_state <= s_txt_empty;
Count: 5
Threshold: 1

If statement:

339:            if (tx_command_txcr_valid = '1') then 
340:                next_state <= s_txt_ready; 
...
344:                next_state <= s_txt_empty; 
345:            end if;

Count: 18268
Threshold: 1

Signal assignment statement:

340: next_state <= s_txt_ready;
Count: 5161
Threshold: 1

Signal assignment statement:

344: next_state <= s_txt_empty;
Count: 16
Threshold: 1

If statement:

353:            if (tx_command_txcr_valid = '1') then 
354:                next_state <= s_txt_ready; 
...
358:                next_state <= s_txt_empty; 
359:            end if;

Count: 480
Threshold: 1

Signal assignment statement:

354: next_state <= s_txt_ready;
Count: 60
Threshold: 1

Signal assignment statement:

358: next_state <= s_txt_empty;
Count: 49
Threshold: 1

If statement:

368:    txt_fsm_ce <= '1' when (next_state /= curr_state) else 
369:                  '0';

Count: 101601
Threshold: 1

Signal assignment statement:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else
Count: 50003
Threshold: 1

Signal assignment statement:

369: '0';
Count: 51598
Threshold: 1

If statement:

376:        if (res_n = '0') then 
377:            curr_state <= s_txt_empty; 
...
381:            end if; 
382:        end if;

Count: 1055177083
Threshold: 1

Signal assignment statement:

377: curr_state <= s_txt_empty;
Count: 2418499
Threshold: 1

If statement:

379:            if (txt_fsm_ce = '1') then 
380:                curr_state <= next_state; 
381:            end if;

Count: 526374300
Threshold: 1

Signal assignment statement:

380: curr_state <= next_state;
Count: 41417
Threshold: 1

If statement:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog)) 
392:                                  else 
393:                            '1';

Count: 46139
Threshold: 1

Signal assignment statement:

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or
Count: 29018
Threshold: 1

Signal assignment statement:

393: '1';
Count: 17121
Threshold: 1

If statement:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
...
406:                           else 
407:                       '0';

Count: 173718
Threshold: 1

Signal assignment statement:

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely
Count: 47471
Threshold: 1

Signal assignment statement:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

Count: 34
Threshold: 1

Signal assignment statement:

407: '0';
Count: 126213
Threshold: 1

If statement:

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
412:                            else 
413:                        '0';

Count: 49707
Threshold: 1

Signal assignment statement:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))
Count: 14361
Threshold: 1

Signal assignment statement:

413: '0';
Count: 35346
Threshold: 1

Sequential statement:

416:    with curr_state select txtb_state <= 
417:        TXT_RDY   when s_txt_ready, 
...
423:        TXT_ETY   when s_txt_empty, 
424:        TXT_PER   when s_txt_parity_err;

Count: 46139
Threshold: 1

Signal assignment statement:

417: TXT_RDY when s_txt_ready,
Count: 14361
Threshold: 1

Signal assignment statement:

418: TXT_TRAN when s_txt_tx_prog,
Count: 13943
Threshold: 1

Signal assignment statement:

419: TXT_ABTP when s_txt_ab_prog,
Count: 714
Threshold: 1

Signal assignment statement:

420: TXT_TOK when s_txt_ok,
Count: 5480
Threshold: 1

Signal assignment statement:

421: TXT_ERR when s_txt_failed,
Count: 6418
Threshold: 1

Signal assignment statement:

422: TXT_ABT when s_txt_aborted,
Count: 298
Threshold: 1

Signal assignment statement:

423: TXT_ETY when s_txt_empty,
Count: 4812
Threshold: 1

Signal assignment statement:

424: TXT_PER when s_txt_parity_err;
Count: 113
Threshold: 1

If statement:

432:    txtb_unmask_data_ram <= '1' when (transient_state = '1') 
433:                                else 
434:                            '0';

Count: 27880
Threshold: 1

Signal assignment statement:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')
Count: 12340
Threshold: 1

Signal assignment statement:

434: '0';
Count: 15540
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition:

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	True	29018	1
Bin	False	17121	1

"if" / "when" / "else" condition:

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	True	5365	1
Bin	False	16280	1

"if" / "when" / "else" condition:

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	True	64794	1
Bin	False	50869	1

"if" / "when" / "else" condition:

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	True	2059	1
Bin	False	8459	1

"case" / "with" / "select" choice:

210: when s_txt_empty =>

	Choice of	Count	Threshold
Bin	`s_txt_empty`	24473	1

"if" / "when" / "else" condition:

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4581	1
Bin	False	19892	1

"case" / "with" / "select" choice:

220: when s_txt_ready =>

	Choice of	Count	Threshold
Bin	`s_txt_ready`	46242	1

"if" / "when" / "else" condition:

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	97	1
Bin	False	46145	1

"if" / "when" / "else" condition:

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	262	1
Bin	False	45883	1

"if" / "when" / "else" condition:

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	True	13951	1
Bin	False	31932	1

"if" / "when" / "else" condition:

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	6	1
Bin	False	13945	1

"if" / "when" / "else" condition:

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	True	266	1
Bin	False	31666	1

"case" / "with" / "select" choice:

248: when s_txt_tx_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	44772	1

"if" / "when" / "else" condition:

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	10	1
Bin	False	44762	1

"if" / "when" / "else" condition:

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	102	1
Bin	False	44660	1

"if" / "when" / "else" condition:

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	6343	1
Bin	False	38317	1

"if" / "when" / "else" condition:

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	4828	1
Bin	False	33489	1

"if" / "when" / "else" condition:

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	2026	1
Bin	False	31463	1

"if" / "when" / "else" condition:

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	2021	1

"if" / "when" / "else" condition:

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	True	1426	1
Bin	False	30037	1

"case" / "with" / "select" choice:

282: when s_txt_ab_prog =>

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	2888	1

"if" / "when" / "else" condition:

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	2883	1

"if" / "when" / "else" condition:

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	12	1
Bin	False	2871	1

"if" / "when" / "else" condition:

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	True	18	1
Bin	False	2853	1

"if" / "when" / "else" condition:

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	652	1
Bin	False	2201	1

"if" / "when" / "else" condition:

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	True	32	1
Bin	False	2169	1

"case" / "with" / "select" choice:

308: when s_txt_failed =>

	Choice of	Count	Threshold
Bin	`s_txt_failed`	21948	1

"if" / "when" / "else" condition:

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	7441	1
Bin	False	14507	1

"if" / "when" / "else" condition:

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	25	1
Bin	False	14482	1

"case" / "with" / "select" choice:

322: when s_txt_aborted =>

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	1202	1

"if" / "when" / "else" condition:

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	288	1
Bin	False	914	1

"if" / "when" / "else" condition:

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	5	1
Bin	False	909	1

"case" / "with" / "select" choice:

336: when s_txt_ok =>

	Choice of	Count	Threshold
Bin	`s_txt_ok`	18268	1

"if" / "when" / "else" condition:

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	5161	1
Bin	False	13107	1

"if" / "when" / "else" condition:

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	16	1
Bin	False	13091	1

"case" / "with" / "select" choice:

350: when s_txt_parity_err =>

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	480	1

"if" / "when" / "else" condition:

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	60	1
Bin	False	420	1

"if" / "when" / "else" condition:

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	True	49	1
Bin	False	371	1

"if" / "when" / "else" condition:

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	True	50003	1
Bin	False	51598	1

"if" / "when" / "else" condition:

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2418499	1
Bin	False	1052758584	1

"if" / "when" / "else" condition:

378: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	526374300	1
Bin	False	526384284	1

"if" / "when" / "else" condition:

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	41417	1
Bin	False	526332883	1

"if" / "when" / "else" condition:

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	True	29018	1
Bin	False	17121	1

"if" / "when" / "else" condition:

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	True	47471	1
Bin	False	126247	1

"if" / "when" / "else" condition:

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	34	1
Bin	False	126213	1

"if" / "when" / "else" condition:

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	True	14361	1
Bin	False	35346	1

"case" / "with" / "select" choice:

417: TXT_RDY when s_txt_ready,

	Choice of	Count	Threshold
Bin	`s_txt_ready`	14361	1

"case" / "with" / "select" choice:

418: TXT_TRAN when s_txt_tx_prog,

	Choice of	Count	Threshold
Bin	`s_txt_tx_prog`	13943	1

"case" / "with" / "select" choice:

419: TXT_ABTP when s_txt_ab_prog,

	Choice of	Count	Threshold
Bin	`s_txt_ab_prog`	714	1

"case" / "with" / "select" choice:

420: TXT_TOK when s_txt_ok,

	Choice of	Count	Threshold
Bin	`s_txt_ok`	5480	1

"case" / "with" / "select" choice:

421: TXT_ERR when s_txt_failed,

	Choice of	Count	Threshold
Bin	`s_txt_failed`	6418	1

"case" / "with" / "select" choice:

422: TXT_ABT when s_txt_aborted,

	Choice of	Count	Threshold
Bin	`s_txt_aborted`	298	1

"case" / "with" / "select" choice:

423: TXT_ETY when s_txt_empty,

	Choice of	Count	Threshold
Bin	`s_txt_empty`	4812	1

"case" / "with" / "select" choice:

424: TXT_PER when s_txt_parity_err;

	Choice of	Count	Threshold
Bin	`s_txt_parity_err`	113	1

"if" / "when" / "else" condition:

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	True	12340	1
Bin	False	15540	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	527578869	1
Bin	1	0	527580460	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	8082	1
Bin	1	0	8072	1

Port:

MR_MODE_BMM

	From	To	Count	Threshold
Bin	0	1	15	1
Bin	1	0	1615	1

Port:

MR_MODE_ROM

	From	To	Count	Threshold
Bin	0	1	51	1
Bin	1	0	1651	1

Port:

MR_SETTINGS_TBFBO

	From	To	Count	Threshold
Bin	0	1	2533	1
Bin	1	0	943	1

Port:

TX_COMMAND_TXCE_VALID

	From	To	Count	Threshold
Bin	0	1	105	1
Bin	1	0	1705	1

Port:

TX_COMMAND_TXCR_VALID

	From	To	Count	Threshold
Bin	0	1	17842	1
Bin	1	0	19442	1

Port:

ABORT_APPLIED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2584	1

Port:

ABORT_OR_SKIPPED

	From	To	Count	Threshold
Bin	0	1	984	1
Bin	1	0	2584	1

Port:

TXTB_HW_CMD.LOCK

	From	To	Count	Threshold
Bin	0	1	24816	1
Bin	1	0	26416	1

Port:

TXTB_HW_CMD.VALID

	From	To	Count	Threshold
Bin	0	1	11098	1
Bin	1	0	12698	1

Port:

TXTB_HW_CMD.ERR

	From	To	Count	Threshold
Bin	0	1	4237	1
Bin	1	0	5837	1

Port:

TXTB_HW_CMD.ARBL

	From	To	Count	Threshold
Bin	0	1	455	1
Bin	1	0	2055	1

Port:

TXTB_HW_CMD.FAILED

	From	To	Count	Threshold
Bin	0	1	9015	1
Bin	1	0	10615	1

Port:

TXTB_HW_CMD_CS

	From	To	Count	Threshold
Bin	0	1	7411	1
Bin	1	0	5811	1

Port:

IS_BUS_OFF

	From	To	Count	Threshold
Bin	0	1	8227	1
Bin	1	0	8236	1

Port:

TXTB_PARITY_ERROR_VALID

	From	To	Count	Threshold
Bin	0	1	420	1
Bin	1	0	2020	1

Port:

TXTB_USER_ACCESSIBLE

	From	To	Count	Threshold
Bin	0	1	13940	1
Bin	1	0	12340	1

Port:

TXTB_ALLOW_BB

	From	To	Count	Threshold
Bin	0	1	12340	1
Bin	1	0	13940	1

Port:

TXTB_HW_CMD_INT

	From	To	Count	Threshold
Bin	0	1	11933	1
Bin	1	0	13533	1

Port:

TXTB_STATE(3)

	From	To	Count	Threshold
Bin	0	1	4860	1
Bin	1	0	3263	1

Port:

TXTB_STATE(2)

	From	To	Count	Threshold
Bin	0	1	12196	1
Bin	1	0	13793	1

Port:

TXTB_STATE(1)

	From	To	Count	Threshold
Bin	0	1	14267	1
Bin	1	0	15867	1

Port:

TXTB_STATE(0)

	From	To	Count	Threshold
Bin	0	1	14780	1
Bin	1	0	16380	1

Port:

TXTB_AVAILABLE

	From	To	Count	Threshold
Bin	0	1	14361	1
Bin	1	0	15961	1

Port:

TXTB_UNMASK_DATA_RAM

	From	To	Count	Threshold
Bin	0	1	12340	1
Bin	1	0	13940	1

Signal:

TXT_FSM_CE

	From	To	Count	Threshold
Bin	0	1	49998	1
Bin	1	0	51598	1

Signal:

GO_TO_FAILED

	From	To	Count	Threshold
Bin	0	1	5218	1
Bin	1	0	5228	1

Signal:

TRANSIENT_STATE

	From	To	Count	Threshold
Bin	0	1	12340	1
Bin	1	0	13940	1

Port:

TXTB_HW_CMD_I.LOCK

	From	To	Count	Threshold
Bin	0	1	13949	1
Bin	1	0	17149	1

Port:

TXTB_HW_CMD_I.VALID

	From	To	Count	Threshold
Bin	0	1	5480	1
Bin	1	0	8680	1

Port:

TXTB_HW_CMD_I.ERR

	From	To	Count	Threshold
Bin	0	1	1823	1
Bin	1	0	5023	1

Port:

TXTB_HW_CMD_I.ARBL

	From	To	Count	Threshold
Bin	0	1	236	1
Bin	1	0	3436	1

Port:

TXTB_HW_CMD_I.FAILED

	From	To	Count	Threshold
Bin	0	1	6404	1
Bin	1	0	9604	1

Signal:

ARBL_OR_ERR

	From	To	Count	Threshold
Bin	0	1	2059	1
Bin	1	0	3659	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression

175: transient_state <= '1' when ((curr_state = s_txt_ab_prog) or

	Evaluated to	Count	Threshold
Bin	False	45425	1
Bin	True	714	1

"=" expression

176: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	32196	1
Bin	True	13943	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	31482	1
Bin	False	True	13943	1
Bin	True	False	714	1

"=" expression

177: (curr_state = s_txt_ready))

	Evaluated to	Count	Threshold
Bin	False	31778	1
Bin	True	14361	1

"or" expression

175:    transient_state <= '1' when ((curr_state = s_txt_ab_prog) or 
176:                                 (curr_state = s_txt_tx_prog) or 
177:                                 (curr_state = s_txt_ready))

	LHS	RHS	Count	Threshold
Bin	False	False	17121	1
Bin	False	True	14361	1
Bin	True	False	14657	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	10034	1
Bin	True	11611	1

"=" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or

	Evaluated to	Count	Threshold
Bin	False	13505	1
Bin	True	8140	1

"and" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
                                   <-----LHS------>     <----------------------RHS---------------------->

	LHS	RHS	Count	Threshold
Bin	False	True	2877	1
Bin	True	False	6348	1
Bin	True	True	5263	1

"=" expression

182: mr_mode_bmm = BMM_ENABLED or

	Evaluated to	Count	Threshold
Bin	False	21595	1
Bin	True	50	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or

	LHS	RHS	Count	Threshold
Bin	False	False	16342	1
Bin	False	True	40	1
Bin	True	False	5253	1

"=" expression

183: mr_mode_rom = ROM_ENABLED)

	Evaluated to	Count	Threshold
Bin	False	21548	1
Bin	True	97	1

"or" expression

181:    go_to_failed <= '1' when ((is_bus_off = '1' and mr_settings_tbfbo = TXTBUF_FAILED_BUS_OFF_ENABLED) or 
182:                              mr_mode_bmm = BMM_ENABLED or 
183:                              mr_mode_rom = ROM_ENABLED)

	LHS	RHS	Count	Threshold
Bin	False	False	16280	1
Bin	False	True	62	1
Bin	True	False	5268	1

"=" expression

187: txtb_hw_cmd_i <= txtb_hw_cmd when (txtb_hw_cmd_cs = '1')

	Evaluated to	Count	Threshold
Bin	False	50869	1
Bin	True	64794	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	8695	1
Bin	True	1823	1

"=" expression

191: arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else

	Evaluated to	Count	Threshold
Bin	False	10282	1
Bin	True	236	1

"or" expression

191:    arbl_or_err <= '1' when (txtb_hw_cmd_i.err = '1' or txtb_hw_cmd_i.arbl = '1') else 
                                 <---------LHS--------->    <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	False	8459	1
Bin	False	True	236	1
Bin	True	False	1823	1

"=" expression

213: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	19892	1
Bin	True	4581	1

"=" expression

223: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	46145	1
Bin	True	97	1

"=" expression

227: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	45883	1
Bin	True	262	1

"=" expression

231: elsif (txtb_hw_cmd_i.lock = '1') then

	Evaluated to	Count	Threshold
Bin	False	31932	1
Bin	True	13951	1

"=" expression

234: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	13945	1
Bin	True	6	1

"=" expression

241: elsif (abort_or_skipped = '1') then

	Evaluated to	Count	Threshold
Bin	False	31666	1
Bin	True	266	1

"=" expression

251: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	44762	1
Bin	True	10	1

"=" expression

255: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	44660	1
Bin	True	102	1

"=" expression

259: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	38317	1
Bin	True	6343	1

"=" expression

263: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	33489	1
Bin	True	4828	1

"=" expression

267: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	31463	1
Bin	True	2026	1

"=" expression

268: if (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	2021	1
Bin	True	5	1

"=" expression

275: elsif (abort_applied = '1') then

	Evaluated to	Count	Threshold
Bin	False	30037	1
Bin	True	1426	1

"=" expression

285: if (go_to_failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	2883	1
Bin	True	5	1

"=" expression

289: elsif (txtb_parity_error_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	2871	1
Bin	True	12	1

"=" expression

293: elsif (txtb_hw_cmd_i.failed = '1') then

	Evaluated to	Count	Threshold
Bin	False	2853	1
Bin	True	18	1

"=" expression

297: elsif (txtb_hw_cmd_i.valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	2201	1
Bin	True	652	1

"=" expression

301: elsif (arbl_or_err = '1') then

	Evaluated to	Count	Threshold
Bin	False	2169	1
Bin	True	32	1

"=" expression

311: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	14507	1
Bin	True	7441	1

"=" expression

315: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	14482	1
Bin	True	25	1

"=" expression

325: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	914	1
Bin	True	288	1

"=" expression

329: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	909	1
Bin	True	5	1

"=" expression

339: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	13107	1
Bin	True	5161	1

"=" expression

343: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	13091	1
Bin	True	16	1

"=" expression

353: if (tx_command_txcr_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	420	1
Bin	True	60	1

"=" expression

357: elsif (tx_command_txce_valid = '1') then

	Evaluated to	Count	Threshold
Bin	False	371	1
Bin	True	49	1

"/=" expression

368: txt_fsm_ce <= '1' when (next_state /= curr_state) else

	Evaluated to	Count	Threshold
Bin	False	51598	1
Bin	True	50003	1

"=" expression

376: if (res_n = '0') then

	Evaluated to	Count	Threshold
Bin	False	1052758584	1
Bin	True	2418499	1

"=" expression

379: if (txt_fsm_ce = '1') then

	Evaluated to	Count	Threshold
Bin	False	526332883	1
Bin	True	41417	1

"=" expression

389: txtb_user_accessible <= '0' when ((curr_state = s_txt_ready) or

	Evaluated to	Count	Threshold
Bin	False	31778	1
Bin	True	14361	1

"=" expression

390: (curr_state = s_txt_tx_prog) or

	Evaluated to	Count	Threshold
Bin	False	32196	1
Bin	True	13943	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or

	LHS	RHS	Count	Threshold
Bin	False	False	17835	1
Bin	False	True	13943	1
Bin	True	False	14361	1

"=" expression

391: (curr_state = s_txt_ab_prog))

	Evaluated to	Count	Threshold
Bin	False	45425	1
Bin	True	714	1

"or" expression

389:    txtb_user_accessible <= '0' when ((curr_state = s_txt_ready)   or 
390:                                      (curr_state = s_txt_tx_prog) or 
391:                                      (curr_state = s_txt_ab_prog))

	LHS	RHS	Count	Threshold
Bin	False	False	17121	1
Bin	False	True	714	1
Bin	True	False	28304	1

"=" expression

396: txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or -- Fail transition completely

	Evaluated to	Count	Threshold
Bin	False	148231	1
Bin	True	25487	1

"=" expression

397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	Evaluated to	Count	Threshold
Bin	False	151798	1
Bin	True	21920	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK

	LHS	RHS	Count	Threshold
Bin	False	False	126311	1
Bin	False	True	21920	1
Bin	True	False	25487	1

"=" expression

398: ((txtb_hw_cmd_i.arbl = '1' or

	Evaluated to	Count	Threshold
Bin	False	173005	1
Bin	True	713	1

"=" expression

399: txtb_hw_cmd_i.err = '1') and

	Evaluated to	Count	Threshold
Bin	False	168219	1
Bin	True	5499	1

"or" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and

	LHS	RHS	Count	Threshold
Bin	False	False	167506	1
Bin	False	True	5499	1
Bin	True	False	713	1

"=" expression

400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	Evaluated to	Count	Threshold
Bin	False	171588	1
Bin	True	2130	1

"and" expression

398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	True	2066	1
Bin	True	False	6148	1
Bin	True	True	64	1

"or" expression

396:    txtb_hw_cmd_int <= '1' when (txtb_hw_cmd_i.failed = '1') or  -- Fail transition completely 
397:                                (txtb_hw_cmd_i.valid = '1') or   -- Finish transition OK 
398:                                ((txtb_hw_cmd_i.arbl = '1' or 
399:                                  txtb_hw_cmd_i.err = '1') and 
400:                                 (curr_state = s_txt_ab_prog))   -- Not failed completely, but already in

	LHS	RHS	Count	Threshold
Bin	False	False	126247	1
Bin	False	True	64	1
Bin	True	False	47407	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	117824	1
Bin	True	8423	1

"=" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and

	Evaluated to	Count	Threshold
Bin	False	117394	1
Bin	True	8853	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
                                     <-----LHS------>     <----------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	8760	1
Bin	True	False	8330	1
Bin	True	True	93	1

"=" expression

405: transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	75045	1
Bin	True	51202	1

"and" expression

404:                       '1' when (is_bus_off = '1' and next_state = s_txt_failed and 
405:                                 transient_state = '1')

	LHS	RHS	Count	Threshold
Bin	False	True	51168	1
Bin	True	False	59	1
Bin	True	True	34	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	35079	1
Bin	True	14628	1

"=" expression

411: txtb_available <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0'))

	Evaluated to	Count	Threshold
Bin	False	3564	1
Bin	True	46143	1

"and" expression

411:    txtb_available   <= '1' when ((curr_state = s_txt_ready) and (abort_applied = '0')) 
                                       <---------LHS---------->       <-------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	31782	1
Bin	True	False	267	1
Bin	True	True	14361	1

"=" expression

432: txtb_unmask_data_ram <= '1' when (transient_state = '1')

	Evaluated to	Count	Threshold
Bin	False	15540	1
Bin	True	12340	1

	State	Count	Threshold
Bin	S_TXT_EMPTY	6183	1
Bin	S_TXT_READY	19745	1
Bin	S_TXT_TX_PROG	14013	1
Bin	S_TXT_AB_PROG	719	1
Bin	S_TXT_OK	7606	1
Bin	S_TXT_FAILED	8100	1
Bin	S_TXT_ABORTED	308	1
Bin	S_TXT_PARITY_ERR	388	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(0).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST.TXT_BUFFER_FSM_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/txt_buffer/txt_buffer_fsm.vhd

Sub-instances:

Current Instance:

Details:

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Uncovered statements:

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