Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.TXT_BUF_COMP_GEN(4).TXT_BUF_EVEN_GEN.TXT_BUFFER_EVEN_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
| CLK_GATE_TXT_BUFFER_RAM_COMP |
100.0 % (3/3) |
100.0 % (2/2) |
100.0 % (10/10) |
100.0 % (8/8) |
N.A. |
N.A. |
100.0 % (23/23) |
| TXT_BUFFER_RAM_INST |
100.0 % (51/51) |
100.0 % (38/38) |
100.0 % (2160/2160) |
100.0 % (62/62) |
N.A. |
N.A. |
100.0 % (2311/2311) |
| TXT_BUFFER_FSM_INST |
100.0 % (79/79) |
100.0 % (94/94) |
100.0 % (70/70) |
100.0 % (151/151) |
100.0 % (16/16) |
N.A. |
100.0 % (410/410) |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
247: else
248: '0'; Count: 23336
Threshold: 1
Signal assignment statement:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') Count: 11227
Threshold: 1
Signal assignment statement:
248: '0'; Count: 12109
Threshold: 1
If statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1')
260: else
261: (others => '0'); Count: 6279
Threshold: 1
Signal assignment statement:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') Count: 1382
Threshold: 1
Signal assignment statement:
261: (others => '0'); Count: 4897
Threshold: 1
If statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
270: else
271: '1' when (mr_tst_control_tmaena = '1')
272: else
273: '0'; Count: 40728
Threshold: 1
Signal assignment statement:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') Count: 19794
Threshold: 1
Signal assignment statement:
271: '1' when (mr_tst_control_tmaena = '1') Count: 240
Threshold: 1
Signal assignment statement:
273: '0'; Count: 20694
Threshold: 1
If statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID)
283: else
284: '0'; Count: 43783
Threshold: 1
Signal assignment statement:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and Count: 95
Threshold: 1
Signal assignment statement:
284: '0'; Count: 43688
Threshold: 1
If statement:
294: if (res_n = '0') then
295: mr_tx_command_txce_q <= '0';
...
301: mr_tx_command_txca_q <= mr_tx_command_txca;
302: end if; Count: 35370646
Threshold: 1
Signal assignment statement:
295: mr_tx_command_txce_q <= '0'; Count: 760516
Threshold: 1
Signal assignment statement:
296: mr_tx_command_txcr_q <= '0'; Count: 760516
Threshold: 1
Signal assignment statement:
297: mr_tx_command_txca_q <= '0'; Count: 760516
Threshold: 1
Signal assignment statement:
299: mr_tx_command_txce_q <= mr_tx_command_txce; Count: 17304621
Threshold: 1
Signal assignment statement:
300: mr_tx_command_txcr_q <= mr_tx_command_txcr; Count: 17304621
Threshold: 1
Signal assignment statement:
301: mr_tx_command_txca_q <= mr_tx_command_txca; Count: 17304621
Threshold: 1
If statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
306: else
307: '0'; Count: 929
Threshold: 1
Signal assignment statement:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') Count: 24
Threshold: 1
Signal assignment statement:
307: '0'; Count: 905
Threshold: 1
If statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
309: else
310: '0'; Count: 6205
Threshold: 1
Signal assignment statement:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') Count: 271
Threshold: 1
Signal assignment statement:
310: '0'; Count: 5934
Threshold: 1
If statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
313: else
314: '0'; Count: 1681
Threshold: 1
Signal assignment statement:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') Count: 46
Threshold: 1
Signal assignment statement:
314: '0'; Count: 1635
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 11227 | 1 |
| Bin | False | 12109 | 1 |
"if" / "when" / "else" condition:
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1382 | 1 |
| Bin | False | 4897 | 1 |
"if" / "when" / "else" condition:
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 19794 | 1 |
| Bin | False | 20934 | 1 |
"if" / "when" / "else" condition:
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 240 | 1 |
| Bin | False | 20694 | 1 |
"if" / "when" / "else" condition:
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 95 | 1 |
| Bin | False | 43688 | 1 |
"if" / "when" / "else" condition:
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 760516 | 1 |
| Bin | False | 34610130 | 1 |
"if" / "when" / "else" condition:
298: elsif (rising_edge(clk_sys)) then | Evaluated to | Count | Threshold |
|---|
| Bin | True | 17304621 | 1 |
| Bin | False | 17305509 | 1 |
"if" / "when" / "else" condition:
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 24 | 1 |
| Bin | False | 905 | 1 |
"if" / "when" / "else" condition:
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 271 | 1 |
| Bin | False | 5934 | 1 |
"if" / "when" / "else" condition:
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 46 | 1 |
| Bin | False | 1635 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17684435 | 1 |
| Bin | 1 | 0 | 17684600 | 1 |
Port:
RES_N | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 723 | 1 |
| Bin | 1 | 0 | 723 | 1 |
Port:
SCAN_ENABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1 | 1 |
| Bin | 1 | 0 | 166 | 1 |
Port:
MR_MODE_BMM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3 | 1 |
| Bin | 1 | 0 | 168 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8 | 1 |
| Bin | 1 | 0 | 173 | 1 |
Port:
MR_MODE_TXBBM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 7 | 1 |
| Bin | 1 | 0 | 172 | 1 |
Port:
MR_SETTINGS_TBFBO | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 199 | 1 |
| Bin | 1 | 0 | 34 | 1 |
Port:
MR_SETTINGS_PCHKE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35 | 1 |
| Bin | 1 | 0 | 200 | 1 |
Port:
MR_TX_COMMAND_TXCE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 3599 | 1 |
Port:
MR_TX_COMMAND_TXCR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2786 | 1 |
| Bin | 1 | 0 | 3599 | 1 |
Port:
MR_TX_COMMAND_TXCA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 512 | 1 |
| Bin | 1 | 0 | 3599 | 1 |
Port:
MR_TX_COMMAND_TXBI | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 81 | 1 |
| Bin | 1 | 0 | 246 | 1 |
Port:
MR_TST_CONTROL_TMAENA | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 240 | 1 |
| Bin | 1 | 0 | 405 | 1 |
Port:
MR_TST_CONTROL_TWRSTB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24019 | 1 |
| Bin | 1 | 0 | 24663 | 1 |
Port:
MR_TST_DEST_TST_ADDR(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2083 | 1 |
| Bin | 1 | 0 | 2248 | 1 |
Port:
MR_TST_DEST_TST_ADDR(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3365 | 1 |
| Bin | 1 | 0 | 3530 | 1 |
Port:
MR_TST_DEST_TST_ADDR(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 6817 | 1 |
| Bin | 1 | 0 | 6982 | 1 |
Port:
MR_TST_DEST_TST_ADDR(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14296 | 1 |
| Bin | 1 | 0 | 14461 | 1 |
Port:
MR_TST_DEST_TST_ADDR(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 28591 | 1 |
| Bin | 1 | 0 | 28756 | 1 |
Port:
MR_TST_DEST_TST_MTGT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 91 | 1 |
| Bin | 1 | 0 | 256 | 1 |
Port:
MR_TST_DEST_TST_MTGT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133 | 1 |
| Bin | 1 | 0 | 298 | 1 |
Port:
MR_TST_DEST_TST_MTGT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 349 | 1 |
Port:
MR_TST_DEST_TST_MTGT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 350 | 1 |
| Bin | 1 | 0 | 515 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1168 | 1 |
| Bin | 1 | 0 | 1333 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1113 | 1 |
| Bin | 1 | 0 | 1278 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1143 | 1 |
| Bin | 1 | 0 | 1308 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1221 | 1 |
| Bin | 1 | 0 | 1386 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1247 | 1 |
| Bin | 1 | 0 | 1412 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1230 | 1 |
| Bin | 1 | 0 | 1395 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1246 | 1 |
| Bin | 1 | 0 | 1411 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1287 | 1 |
| Bin | 1 | 0 | 1452 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1175 | 1 |
| Bin | 1 | 0 | 1340 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1117 | 1 |
| Bin | 1 | 0 | 1282 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1148 | 1 |
| Bin | 1 | 0 | 1313 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1239 | 1 |
| Bin | 1 | 0 | 1404 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1248 | 1 |
| Bin | 1 | 0 | 1413 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1231 | 1 |
| Bin | 1 | 0 | 1396 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1250 | 1 |
| Bin | 1 | 0 | 1415 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1284 | 1 |
| Bin | 1 | 0 | 1449 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1176 | 1 |
| Bin | 1 | 0 | 1341 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1126 | 1 |
| Bin | 1 | 0 | 1291 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1163 | 1 |
| Bin | 1 | 0 | 1328 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1236 | 1 |
| Bin | 1 | 0 | 1401 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1236 | 1 |
| Bin | 1 | 0 | 1401 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1235 | 1 |
| Bin | 1 | 0 | 1400 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1254 | 1 |
| Bin | 1 | 0 | 1419 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1290 | 1 |
| Bin | 1 | 0 | 1455 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1188 | 1 |
| Bin | 1 | 0 | 1353 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1144 | 1 |
| Bin | 1 | 0 | 1309 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1178 | 1 |
| Bin | 1 | 0 | 1343 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1229 | 1 |
| Bin | 1 | 0 | 1394 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1251 | 1 |
| Bin | 1 | 0 | 1416 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1239 | 1 |
| Bin | 1 | 0 | 1404 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1252 | 1 |
| Bin | 1 | 0 | 1417 | 1 |
Port:
MR_TST_WDATA_TST_WDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1297 | 1 |
| Bin | 1 | 0 | 1462 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123 | 1 |
| Bin | 1 | 0 | 288 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133 | 1 |
| Bin | 1 | 0 | 298 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 125 | 1 |
| Bin | 1 | 0 | 290 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 139 | 1 |
| Bin | 1 | 0 | 304 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 146 | 1 |
| Bin | 1 | 0 | 311 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 137 | 1 |
| Bin | 1 | 0 | 302 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 137 | 1 |
| Bin | 1 | 0 | 302 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 139 | 1 |
| Bin | 1 | 0 | 304 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 134 | 1 |
| Bin | 1 | 0 | 299 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 146 | 1 |
| Bin | 1 | 0 | 311 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 137 | 1 |
| Bin | 1 | 0 | 302 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 134 | 1 |
| Bin | 1 | 0 | 299 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 143 | 1 |
| Bin | 1 | 0 | 308 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 147 | 1 |
| Bin | 1 | 0 | 312 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 295 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 120 | 1 |
| Bin | 1 | 0 | 285 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 127 | 1 |
| Bin | 1 | 0 | 292 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 289 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 128 | 1 |
| Bin | 1 | 0 | 293 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 295 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 294 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 131 | 1 |
| Bin | 1 | 0 | 296 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 133 | 1 |
| Bin | 1 | 0 | 298 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 301 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 129 | 1 |
| Bin | 1 | 0 | 294 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 143 | 1 |
| Bin | 1 | 0 | 308 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135 | 1 |
| Bin | 1 | 0 | 300 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 280 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 301 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 141 | 1 |
| Bin | 1 | 0 | 306 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 134 | 1 |
| Bin | 1 | 0 | 299 | 1 |
Port:
MR_TST_RDATA_TST_RDATA(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 134 | 1 |
| Bin | 1 | 0 | 299 | 1 |
Port:
TXTB_PORT_A_DATA_IN(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16808 | 1 |
| Bin | 1 | 0 | 322174 | 1 |
Port:
TXTB_PORT_A_DATA_IN(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18868 | 1 |
| Bin | 1 | 0 | 320114 | 1 |
Port:
TXTB_PORT_A_DATA_IN(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 16474 | 1 |
| Bin | 1 | 0 | 322508 | 1 |
Port:
TXTB_PORT_A_DATA_IN(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 25047 | 1 |
| Bin | 1 | 0 | 313935 | 1 |
Port:
TXTB_PORT_A_DATA_IN(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19169 | 1 |
| Bin | 1 | 0 | 319813 | 1 |
Port:
TXTB_PORT_A_DATA_IN(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21501 | 1 |
| Bin | 1 | 0 | 317481 | 1 |
Port:
TXTB_PORT_A_DATA_IN(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26436 | 1 |
| Bin | 1 | 0 | 312546 | 1 |
Port:
TXTB_PORT_A_DATA_IN(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21343 | 1 |
| Bin | 1 | 0 | 317639 | 1 |
Port:
TXTB_PORT_A_DATA_IN(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20412 | 1 |
| Bin | 1 | 0 | 318570 | 1 |
Port:
TXTB_PORT_A_DATA_IN(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 23917 | 1 |
| Bin | 1 | 0 | 315065 | 1 |
Port:
TXTB_PORT_A_DATA_IN(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22658 | 1 |
| Bin | 1 | 0 | 316324 | 1 |
Port:
TXTB_PORT_A_DATA_IN(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20997 | 1 |
| Bin | 1 | 0 | 317985 | 1 |
Port:
TXTB_PORT_A_DATA_IN(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 35338 | 1 |
| Bin | 1 | 0 | 303644 | 1 |
Port:
TXTB_PORT_A_DATA_IN(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 43965 | 1 |
| Bin | 1 | 0 | 295017 | 1 |
Port:
TXTB_PORT_A_DATA_IN(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41196 | 1 |
| Bin | 1 | 0 | 297786 | 1 |
Port:
TXTB_PORT_A_DATA_IN(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 84963 | 1 |
| Bin | 1 | 0 | 254019 | 1 |
Port:
TXTB_PORT_A_DATA_IN(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 18507 | 1 |
| Bin | 1 | 0 | 320475 | 1 |
Port:
TXTB_PORT_A_DATA_IN(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 21922 | 1 |
| Bin | 1 | 0 | 317060 | 1 |
Port:
TXTB_PORT_A_DATA_IN(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19202 | 1 |
| Bin | 1 | 0 | 319780 | 1 |
Port:
TXTB_PORT_A_DATA_IN(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22335 | 1 |
| Bin | 1 | 0 | 316647 | 1 |
Port:
TXTB_PORT_A_DATA_IN(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 40384 | 1 |
| Bin | 1 | 0 | 298598 | 1 |
Port:
TXTB_PORT_A_DATA_IN(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 41708 | 1 |
| Bin | 1 | 0 | 297274 | 1 |
Port:
TXTB_PORT_A_DATA_IN(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49733 | 1 |
| Bin | 1 | 0 | 289249 | 1 |
Port:
TXTB_PORT_A_DATA_IN(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50881 | 1 |
| Bin | 1 | 0 | 288101 | 1 |
Port:
TXTB_PORT_A_DATA_IN(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44637 | 1 |
| Bin | 1 | 0 | 294345 | 1 |
Port:
TXTB_PORT_A_DATA_IN(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 42583 | 1 |
| Bin | 1 | 0 | 296399 | 1 |
Port:
TXTB_PORT_A_DATA_IN(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44992 | 1 |
| Bin | 1 | 0 | 293990 | 1 |
Port:
TXTB_PORT_A_DATA_IN(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 49747 | 1 |
| Bin | 1 | 0 | 289235 | 1 |
Port:
TXTB_PORT_A_DATA_IN(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 53414 | 1 |
| Bin | 1 | 0 | 285568 | 1 |
Port:
TXTB_PORT_A_DATA_IN(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 56312 | 1 |
| Bin | 1 | 0 | 282670 | 1 |
Port:
TXTB_PORT_A_DATA_IN(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 97154 | 1 |
| Bin | 1 | 0 | 241828 | 1 |
Port:
TXTB_PORT_A_DATA_IN(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 84031 | 1 |
| Bin | 1 | 0 | 254951 | 1 |
Port:
TXTB_PORT_A_PARITY | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 270660 | 1 |
| Bin | 1 | 0 | 68322 | 1 |
Port:
TXTB_PORT_A_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 101760 | 1 |
| Bin | 1 | 0 | 4959695 | 1 |
Port:
TXTB_PORT_A_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 128188 | 1 |
| Bin | 1 | 0 | 4933267 | 1 |
Port:
TXTB_PORT_A_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 109822 | 1 |
| Bin | 1 | 0 | 4951633 | 1 |
Port:
TXTB_PORT_A_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4817393 | 1 |
| Bin | 1 | 0 | 244062 | 1 |
Port:
TXTB_PORT_A_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3627605 | 1 |
| Bin | 1 | 0 | 1433850 | 1 |
Port:
TXTB_PORT_A_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11287 | 1 |
| Bin | 1 | 0 | 11452 | 1 |
Port:
TXTB_PORT_A_BE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5053365 | 1 |
| Bin | 1 | 0 | 7925 | 1 |
Port:
TXTB_PORT_A_BE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5053445 | 1 |
| Bin | 1 | 0 | 7845 | 1 |
Port:
TXTB_PORT_A_BE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5039204 | 1 |
| Bin | 1 | 0 | 22086 | 1 |
Port:
TXTB_PORT_A_BE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 5039488 | 1 |
| Bin | 1 | 0 | 21802 | 1 |
Port:
TXTB_STATE(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 274 | 1 |
| Bin | 1 | 0 | 109 | 1 |
Port:
TXTB_STATE(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 189 | 1 |
| Bin | 1 | 0 | 354 | 1 |
Port:
TXTB_STATE(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 245 | 1 |
| Bin | 1 | 0 | 410 | 1 |
Port:
TXTB_STATE(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 242 | 1 |
| Bin | 1 | 0 | 407 | 1 |
Port:
TXTB_HW_CMD_INT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 166 | 1 |
| Bin | 1 | 0 | 331 | 1 |
Port:
TXTB_HW_CMD.LOCK | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2959 | 1 |
| Bin | 1 | 0 | 3124 | 1 |
Port:
TXTB_HW_CMD.VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1153 | 1 |
| Bin | 1 | 0 | 1318 | 1 |
Port:
TXTB_HW_CMD.ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 403 | 1 |
| Bin | 1 | 0 | 568 | 1 |
Port:
TXTB_HW_CMD.ARBL | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17 | 1 |
| Bin | 1 | 0 | 182 | 1 |
Port:
TXTB_HW_CMD.FAILED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1384 | 1 |
| Bin | 1 | 0 | 1549 | 1 |
Port:
TXTB_HW_CMD_CS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 75 | 1 |
| Bin | 1 | 0 | 240 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 50 | 1 |
| Bin | 1 | 0 | 215 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 57 | 1 |
| Bin | 1 | 0 | 222 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 216 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 243 | 1 |
| Bin | 1 | 0 | 408 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 200 | 1 |
| Bin | 1 | 0 | 365 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 233 | 1 |
| Bin | 1 | 0 | 398 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 162 | 1 |
| Bin | 1 | 0 | 327 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 247 | 1 |
| Bin | 1 | 0 | 412 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 284 | 1 |
| Bin | 1 | 0 | 449 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 266 | 1 |
| Bin | 1 | 0 | 431 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 176 | 1 |
| Bin | 1 | 0 | 341 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 232 | 1 |
| Bin | 1 | 0 | 397 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 258 | 1 |
| Bin | 1 | 0 | 423 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 225 | 1 |
| Bin | 1 | 0 | 390 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 279 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 83 | 1 |
| Bin | 1 | 0 | 248 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 108 | 1 |
| Bin | 1 | 0 | 273 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 116 | 1 |
| Bin | 1 | 0 | 281 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 115 | 1 |
| Bin | 1 | 0 | 280 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 119 | 1 |
| Bin | 1 | 0 | 284 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 130 | 1 |
| Bin | 1 | 0 | 295 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 124 | 1 |
| Bin | 1 | 0 | 289 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 256 | 1 |
| Bin | 1 | 0 | 421 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 135 | 1 |
| Bin | 1 | 0 | 300 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 325 | 1 |
| Bin | 1 | 0 | 490 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 183 | 1 |
| Bin | 1 | 0 | 348 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 215 | 1 |
| Bin | 1 | 0 | 380 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 134 | 1 |
| Bin | 1 | 0 | 299 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 188 | 1 |
| Bin | 1 | 0 | 353 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 184 | 1 |
| Bin | 1 | 0 | 349 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 221 | 1 |
| Bin | 1 | 0 | 386 | 1 |
Port:
TXTB_PORT_B_DATA_OUT(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 294 | 1 |
| Bin | 1 | 0 | 459 | 1 |
Port:
TXTB_PORT_B_ADDRESS(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3193 | 1 |
| Bin | 1 | 0 | 3358 | 1 |
Port:
TXTB_PORT_B_ADDRESS(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 114 | 1 |
| Bin | 1 | 0 | 279 | 1 |
Port:
TXTB_PORT_B_ADDRESS(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 4926 | 1 |
| Bin | 1 | 0 | 5091 | 1 |
Port:
TXTB_PORT_B_ADDRESS(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 3696 | 1 |
| Bin | 1 | 0 | 3696 | 1 |
Port:
TXTB_PORT_B_ADDRESS(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 10610 | 1 |
| Bin | 1 | 0 | 10775 | 1 |
Port:
TXTB_PORT_B_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8567 | 1 |
| Bin | 1 | 0 | 8732 | 1 |
Port:
IS_BUS_OFF | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 758 | 1 |
| Bin | 1 | 0 | 758 | 1 |
Port:
TXTB_AVAILABLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 263 | 1 |
| Bin | 1 | 0 | 428 | 1 |
Port:
TXTB_ALLOW_BB | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 381 | 1 |
Port:
TXTB_PARITY_CHECK_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 17909 | 1 |
| Bin | 1 | 0 | 18074 | 1 |
Port:
TXTB_PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 553 | 1 |
| Bin | 1 | 0 | 718 | 1 |
Port:
TXTB_PARITY_ERROR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 260 | 1 |
Signal:
TXTB_USER_ACCESSIBLE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 381 | 1 |
| Bin | 1 | 0 | 216 | 1 |
Signal:
TXTB_UNMASK_DATA_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 216 | 1 |
| Bin | 1 | 0 | 381 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(31) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 227 | 1 |
| Bin | 1 | 0 | 382 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(30) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 331 | 1 |
| Bin | 1 | 0 | 486 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(29) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 303 | 1 |
| Bin | 1 | 0 | 458 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(28) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 599 | 1 |
| Bin | 1 | 0 | 748 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(27) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 775 | 1 |
| Bin | 1 | 0 | 925 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(26) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 786 | 1 |
| Bin | 1 | 0 | 936 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(25) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 749 | 1 |
| Bin | 1 | 0 | 900 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(24) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 798 | 1 |
| Bin | 1 | 0 | 950 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(23) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 925 | 1 |
| Bin | 1 | 0 | 1072 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(22) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 925 | 1 |
| Bin | 1 | 0 | 1075 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(21) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 802 | 1 |
| Bin | 1 | 0 | 951 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(20) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 732 | 1 |
| Bin | 1 | 0 | 884 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(19) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 905 | 1 |
| Bin | 1 | 0 | 1056 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(18) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 765 | 1 |
| Bin | 1 | 0 | 915 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(17) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 506 | 1 |
| Bin | 1 | 0 | 660 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(16) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 545 | 1 |
| Bin | 1 | 0 | 700 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(15) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 513 | 1 |
| Bin | 1 | 0 | 667 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(14) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 656 | 1 |
| Bin | 1 | 0 | 809 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(13) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 653 | 1 |
| Bin | 1 | 0 | 806 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(12) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 514 | 1 |
| Bin | 1 | 0 | 666 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(11) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 576 | 1 |
| Bin | 1 | 0 | 729 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(10) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 479 | 1 |
| Bin | 1 | 0 | 633 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(9) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1027 | 1 |
| Bin | 1 | 0 | 1175 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(8) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 716 | 1 |
| Bin | 1 | 0 | 870 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(7) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1322 | 1 |
| Bin | 1 | 0 | 1467 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(6) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 998 | 1 |
| Bin | 1 | 0 | 1144 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(5) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 936 | 1 |
| Bin | 1 | 0 | 1086 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(4) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 671 | 1 |
| Bin | 1 | 0 | 824 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(3) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 701 | 1 |
| Bin | 1 | 0 | 851 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(2) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 945 | 1 |
| Bin | 1 | 0 | 1093 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(1) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 882 | 1 |
| Bin | 1 | 0 | 1032 | 1 |
Signal:
TXTB_PORT_B_DATA_OUT_I(0) | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 1119 | 1 |
| Bin | 1 | 0 | 1264 | 1 |
Signal:
TXTB_PARITY_ERROR_VALID_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 95 | 1 |
| Bin | 1 | 0 | 260 | 1 |
Signal:
MR_TX_COMMAND_TXCE_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 136 | 1 |
| Bin | 1 | 0 | 301 | 1 |
Signal:
MR_TX_COMMAND_TXCR_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 2774 | 1 |
| Bin | 1 | 0 | 2939 | 1 |
Signal:
MR_TX_COMMAND_TXCA_Q | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 512 | 1 |
| Bin | 1 | 0 | 677 | 1 |
Signal:
TX_COMMAND_TXCE_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 24 | 1 |
| Bin | 1 | 0 | 189 | 1 |
Signal:
TX_COMMAND_TXCR_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 271 | 1 |
| Bin | 1 | 0 | 436 | 1 |
Signal:
ABORT_APPLIED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 211 | 1 |
Signal:
ABORT_OR_SKIPPED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 46 | 1 |
| Bin | 1 | 0 | 211 | 1 |
Signal:
TXTB_PORT_A_WRITE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11227 | 1 |
| Bin | 1 | 0 | 11392 | 1 |
Signal:
TXTB_RAM_CLK_EN | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 20034 | 1 |
| Bin | 1 | 0 | 20199 | 1 |
Signal:
CLK_RAM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 327637 | 1 |
| Bin | 1 | 0 | 327802 | 1 |
Signal:
PARITY_MISMATCH | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 553 | 1 |
| Bin | 1 | 0 | 718 | 1 |
Covered expressions:
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 12049 | 1 |
| Bin | True | 11287 | 1 |
"=" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 501 | 1 |
| Bin | True | 22835 | 1 |
"and" expression
246: txtb_port_a_write <= '1' when (txtb_port_a_cs = '1' and txtb_user_accessible = '1')
<-------LHS--------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 11608 | 1 |
| Bin | True | False | 60 | 1 |
| Bin | True | True | 11227 | 1 |
"=" expression
259: txtb_port_b_data_out <= txtb_port_b_data_out_i when (txtb_unmask_data_ram = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 4897 | 1 |
| Bin | True | 1382 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 32161 | 1 |
| Bin | True | 8567 | 1 |
"=" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 29501 | 1 |
| Bin | True | 11227 | 1 |
"or" expression
269: txtb_ram_clk_en <= '1' when (txtb_port_b_clk_en = '1' or txtb_port_a_write = '1')
<---------LHS----------> <---------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 20934 | 1 |
| Bin | False | True | 11227 | 1 |
| Bin | True | False | 8567 | 1 |
"=" expression
271: '1' when (mr_tst_control_tmaena = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 20694 | 1 |
| Bin | True | 240 | 1 |
"=" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 41626 | 1 |
| Bin | True | 2157 | 1 |
"=" expression
281: txtb_parity_check_valid = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 25230 | 1 |
| Bin | True | 18553 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 17506 | 1 |
| Bin | True | False | 1110 | 1 |
| Bin | True | True | 1047 | 1 |
"=" expression
282: txtb_index_muxed = G_ID) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 40851 | 1 |
| Bin | True | 2932 | 1 |
"and" expression
280: txtb_parity_error_valid_i <= '1' when (parity_mismatch = '1' and
281: txtb_parity_check_valid = '1' and
282: txtb_index_muxed = G_ID) | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 2837 | 1 |
| Bin | True | False | 952 | 1 |
| Bin | True | True | 95 | 1 |
"=" expression
294: if (res_n = '0') then | Evaluated to | Count | Threshold |
|---|
| Bin | False | 34610130 | 1 |
| Bin | True | 760516 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 789 | 1 |
| Bin | True | 140 | 1 |
"=" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 804 | 1 |
| Bin | True | 125 | 1 |
"and" expression
305: tx_command_txce_valid <= '1' when (mr_tx_command_txce_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 101 | 1 |
| Bin | True | False | 116 | 1 |
| Bin | True | True | 24 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 3297 | 1 |
| Bin | True | 2908 | 1 |
"=" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 5716 | 1 |
| Bin | True | 489 | 1 |
"and" expression
308: tx_command_txcr_valid <= '1' when (mr_tx_command_txcr_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 218 | 1 |
| Bin | True | False | 2637 | 1 |
| Bin | True | True | 271 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1169 | 1 |
| Bin | True | 512 | 1 |
"=" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 1508 | 1 |
| Bin | True | 173 | 1 |
"and" expression
312: abort_applied <= '1' when (mr_tx_command_txca_q = '1' and mr_tx_command_txbi = '1')
<----------LHS-----------> <---------RHS----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 127 | 1 |
| Bin | True | False | 466 | 1 |
| Bin | True | True | 46 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: