NVC code coverage report

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
BIT_GEN(0)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(1)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(2)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(3)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(4)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(5)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(6)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)
BIT_GEN(7)	100.0 % (4/4)	100.0 % (6/6)	N.A.	100.0 % (4/4)	N.A.	N.A.	100.0 % (14/14)

Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.CTR_PRES_CTPV_SLICE_1_REG_COMP	100.0 % (1/1)	N.A.	100.0 % (60/60)	100.0 % (6/6)	N.A.	N.A.	100.0 % (67/67)

Uncovered statements:

Excluded statements:

Covered statements:

Signal assignment statement:

145: wr_en <= write and cs and (not lock);
Count: 380409
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

Uncovered toggles:

Excluded toggles:

Covered toggles:

Port:

CLK_SYS

	From	To	Count	Threshold
Bin	0	1	31028760	1
Bin	1	0	31030360	1

Port:

RES_N

	From	To	Count	Threshold
Bin	0	1	9642	1
Bin	1	0	8042	1

Port:

DATA_IN(7)

	From	To	Count	Threshold
Bin	0	1	126416	1
Bin	1	0	963429	1

Port:

DATA_IN(6)

	From	To	Count	Threshold
Bin	0	1	109550	1
Bin	1	0	980295	1

Port:

DATA_IN(5)

	From	To	Count	Threshold
Bin	0	1	103929	1
Bin	1	0	985916	1

Port:

DATA_IN(4)

	From	To	Count	Threshold
Bin	0	1	162358	1
Bin	1	0	927487	1

Port:

DATA_IN(3)

	From	To	Count	Threshold
Bin	0	1	135873	1
Bin	1	0	953972	1

Port:

DATA_IN(2)

	From	To	Count	Threshold
Bin	0	1	159944	1
Bin	1	0	929901	1

Port:

DATA_IN(1)

	From	To	Count	Threshold
Bin	0	1	236123	1
Bin	1	0	853722	1

Port:

DATA_IN(0)

	From	To	Count	Threshold
Bin	0	1	198401	1
Bin	1	0	891444	1

Port:

WRITE

	From	To	Count	Threshold
Bin	0	1	144497	1
Bin	1	0	146097	1

Port:

CS

	From	To	Count	Threshold
Bin	0	1	41481	1
Bin	1	0	43081	1

Port:

LOCK

	From	To	Count	Threshold
Bin	0	1	2626	1
Bin	1	0	1027	1

Port:

REG_VALUE(7)

	From	To	Count	Threshold
Bin	0	1	2166	1
Bin	1	0	3766	1

Port:

REG_VALUE(6)

	From	To	Count	Threshold
Bin	0	1	683	1
Bin	1	0	2283	1

Port:

REG_VALUE(5)

	From	To	Count	Threshold
Bin	0	1	2181	1
Bin	1	0	3781	1

Port:

REG_VALUE(4)

	From	To	Count	Threshold
Bin	0	1	2332	1
Bin	1	0	3932	1

Port:

REG_VALUE(3)

	From	To	Count	Threshold
Bin	0	1	919	1
Bin	1	0	2519	1

Port:

REG_VALUE(2)

	From	To	Count	Threshold
Bin	0	1	2414	1
Bin	1	0	4014	1

Port:

REG_VALUE(1)

	From	To	Count	Threshold
Bin	0	1	1008	1
Bin	1	0	2608	1

Port:

REG_VALUE(0)

	From	To	Count	Threshold
Bin	0	1	768	1
Bin	1	0	2368	1

Signal:

REG_VALUE_R(7)

	From	To	Count	Threshold
Bin	0	1	2315	1
Bin	1	0	5711	1

Signal:

REG_VALUE_R(6)

	From	To	Count	Threshold
Bin	0	1	819	1
Bin	1	0	7207	1

Signal:

REG_VALUE_R(5)

	From	To	Count	Threshold
Bin	0	1	2371	1
Bin	1	0	5655	1

Signal:

REG_VALUE_R(4)

	From	To	Count	Threshold
Bin	0	1	2510	1
Bin	1	0	5516	1

Signal:

REG_VALUE_R(3)

	From	To	Count	Threshold
Bin	0	1	1122	1
Bin	1	0	6904	1

Signal:

REG_VALUE_R(2)

	From	To	Count	Threshold
Bin	0	1	2610	1
Bin	1	0	5416	1

Signal:

REG_VALUE_R(1)

	From	To	Count	Threshold
Bin	0	1	1220	1
Bin	1	0	6806	1

Signal:

REG_VALUE_R(0)

	From	To	Count	Threshold
Bin	0	1	992	1
Bin	1	0	7034	1

Signal:

WR_EN

	From	To	Count	Threshold
Bin	0	1	41271	1
Bin	1	0	42871	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <LHS>    RHS

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	41481	1
Bin	'1'	'0'	145671	1
Bin	'1'	'1'	41471	1

"and" expression

145:    wr_en <= write and cs and (not lock); 
                 <---LHS---->      <-RHS-->

	LHS	RHS	Count	Threshold
Bin	'0'	'1'	190366	1
Bin	'1'	'0'	200	1
Bin	'1'	'1'	41271	1

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.MEMORY_REGISTERS_INST.CONTROL_REGISTERS_REG_MAP_COMP.CTR_PRES_CTPV_SLICE_1_REG_COMP

File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/memory_reg_rw_lock.vhd

Sub-instances:

Current Instance:

Details:

The limit of printed items was reached (5000). Total 261615 items are not displayed.

Uncovered statements:

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Covered statements:

Signal assignment statement:

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Signal:

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Uncovered expressions:

Excluded expressions:

Covered expressions:

"and" expression

"and" expression

Uncovered FSM states:

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Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: