NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/dp_inf_ram.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.DP_INF_RAM_INST.RAM_RST_FALSE_GEN	100.0 % (3/3)	100.0 % (4/4)	N.A.	100.0 % (2/2)	N.A.	N.A.	100.0 % (9/9)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.RX_BUFFER_INST.RX_BUFFER_RAM_INST.DP_INF_RAM_INST.RAM_RST_FALSE_GEN

100.0 % (3/3)

100.0 % (4/4)

N.A.

100.0 % (2/2)

N.A.

100.0 % (9/9)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 144 to 148:

144:            if (rising_edge(clk_sys)) then 
145:                if (write = '1') then 
146:                    ram_memory(to_integer(unsigned(addr_A))) <= data_in; 
147:                end if; 
148:            end if;

Count: 29501474
Threshold: 1

If statement on lines 145 to 147:

145:                if (write = '1') then 
146:                    ram_memory(to_integer(unsigned(addr_A))) <= data_in; 
147:                end if;

Count: 14749136
Threshold: 1

Signal assignment statement on line 146:

146: ram_memory(to_integer(unsigned(addr_A))) <= data_in;
Count: 241779
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 144:

144: if (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	14749136	1
Bin	False	14752338	1

"if" / "when" / "else" condition on line 145:

145: if (write = '1') then

	Evaluated to	Count	Threshold
Bin	True	241779	1
Bin	False	14507357	1

Uncovered toggles:

Excluded toggles:

Covered toggles:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 145:

write = '1'

	Evaluated to	Count	Threshold
Bin	False	14507357	1
Bin	True	241779	1