NVC code coverage report

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_RULES_INST	100.0 % (18/18)	100.0 % (16/16)	100.0 % (34/34)	98.4 % (65/66)	N.A.	N.A.	99.2 % (133/134)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_RULES_INST

100.0 % (18/18)

100.0 % (16/16)

100.0 % (34/34)

98.4 % (65/66)

N.A.

99.2 % (133/134)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 164 to 166:

164:    inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') 
165:                     else 
166:                 '0';

Count: 354712
Threshold: 1

Signal assignment statement on line 164:

164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
Count: 52223
Threshold: 1

Signal assignment statement on line 166:

166: '0';
Count: 302489
Threshold: 1

If statement on lines 178 to 184:

178:    inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else 
179:                   '1' when (act_err_ovr_flag = '1' and err_detected = '1') else 
...
183:                   '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else 
184:                   '0';

Count: 441563
Threshold: 1

Signal assignment statement on line 178:

178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else
Count: 8004
Threshold: 1

Signal assignment statement on line 179:

179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else
Count: 1544
Threshold: 1

Signal assignment statement on line 180:

180: '1' when (is_transmitter = '1' and
Count: 70767
Threshold: 1

Signal assignment statement on line 183:

183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else
Count: 398
Threshold: 1

Signal assignment statement on line 184:

184: '0';
Count: 360850
Threshold: 1

If statement on lines 189 to 191:

189:    dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') 
190:                   else 
191:               '0';

Count: 56989
Threshold: 1

Signal assignment statement on line 189:

189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')
Count: 26093
Threshold: 1

Signal assignment statement on line 191:

191: '0';
Count: 30896
Threshold: 1

If statement on lines 197 to 199:

197:    inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) 
198:                   else 
199:               '0';

Count: 109351
Threshold: 1

Signal assignment statement on line 197:

197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)
Count: 44810
Threshold: 1

Signal assignment statement on line 199:

199: '0';
Count: 64541
Threshold: 1

If statement on lines 200 to 202:

200:    inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) 
201:                     else 
202:                 '0';

Count: 166267
Threshold: 1

Signal assignment statement on line 200:

200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
Count: 80681
Threshold: 1

Signal assignment statement on line 202:

202: '0';
Count: 85586
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 164:

164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')

	Evaluated to	Count	Threshold
Bin	True	52223	1
Bin	False	302489	1

"if" / "when" / "else" condition on line 178:

178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else

	Evaluated to	Count	Threshold
Bin	True	8004	1
Bin	False	433559	1

"if" / "when" / "else" condition on line 179:

179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else

	Evaluated to	Count	Threshold
Bin	True	1544	1
Bin	False	432015	1

"if" / "when" / "else" condition on lines 180 to 182:

180:                   '1' when (is_transmitter = '1' and 
181:                             err_detected = '1' and 
182:                             err_ctrs_unchanged = '0') else

	Evaluated to	Count	Threshold
Bin	True	70767	1
Bin	False	361248	1

"if" / "when" / "else" condition on line 183:

183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else

	Evaluated to	Count	Threshold
Bin	True	398	1
Bin	False	360850	1

"if" / "when" / "else" condition on line 189:

189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')

	Evaluated to	Count	Threshold
Bin	True	26093	1
Bin	False	30896	1

"if" / "when" / "else" condition on line 197:

197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)

	Evaluated to	Count	Threshold
Bin	True	44810	1
Bin	False	64541	1

"if" / "when" / "else" condition on line 200:

200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)

	Evaluated to	Count	Threshold
Bin	True	80681	1
Bin	False	85586	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_TRANSMITTER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

IS_RECEIVER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DETECTED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_CTRS_UNCHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

PRIMARY_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ACT_ERR_OVR_FLAG

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

ERR_DELIM_LATE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TRAN_VALID

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DECREMENT_REC

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BIT_ERR_AFTER_ACK_ERR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_MODE_ROM

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

INC_ONE

	From	To	Count	Threshold
Bin	0	1	44810	1
Bin	1	0	46411	1

Port:

INC_EIGHT

	From	To	Count	Threshold
Bin	0	1	80681	1
Bin	1	0	82282	1

Port:

DEC_ONE

	From	To	Count	Threshold
Bin	0	1	26093	1
Bin	1	0	27694	1

Signal:

INC_ONE_I

	From	To	Count	Threshold
Bin	0	1	52223	1
Bin	1	0	53824	1

Signal:

INC_EIGHT_I

	From	To	Count	Threshold
Bin	0	1	80681	1
Bin	1	0	82282	1

Uncovered expressions:

"and" expression on line 200:

 inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED 
 <------LHS------>     <----------RHS----------->

	LHS	RHS	Count	Threshold	Exclude Command
Bin	True	False	0	1

Excluded expressions:

Covered expressions:

"and" expression on line 164:

 err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1' 
 <--------------------LHS-------------------->     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	99774	1
Bin	True	False	70767	1
Bin	True	True	52223	1

"and" expression on line 164:

 err_detected = '1' and act_err_ovr_flag = '0' 
 <------LHS------->     <--------RHS--------->

	LHS	RHS	Count	Threshold
Bin	False	True	207505	1
Bin	True	False	1544	1
Bin	True	True	122990	1

"=" expression on line 164:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	230178	1
Bin	True	124534	1

"=" expression on line 164:

act_err_ovr_flag = '0'

	Evaluated to	Count	Threshold
Bin	False	24217	1
Bin	True	330495	1

"=" expression on line 164:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	202715	1
Bin	True	151997	1

"and" expression on line 178:

 primary_err = '1' and is_receiver = '1' 
 <------LHS------>     <------RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	160161	1
Bin	True	False	14766	1
Bin	True	True	8004	1

"=" expression on line 178:

primary_err = '1'

	Evaluated to	Count	Threshold
Bin	False	418793	1
Bin	True	22770	1

"=" expression on line 178:

is_receiver = '1'

	Evaluated to	Count	Threshold
Bin	False	273398	1
Bin	True	168165	1

"and" expression on line 179:

 act_err_ovr_flag = '1' and err_detected = '1' 
 <--------LHS--------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	123471	1
Bin	True	False	21072	1
Bin	True	True	1544	1

"=" expression on line 179:

act_err_ovr_flag = '1'

	Evaluated to	Count	Threshold
Bin	False	410943	1
Bin	True	22616	1

"=" expression on line 179:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	308544	1
Bin	True	125015	1

"and" expression on lines 180 to 182:

 is_transmitter = '1' and err_detected = '1' and err_ctrs_unchanged = '0' 
 <-------------------LHS------------------->     <---------RHS---------->

	LHS	RHS	Count	Threshold
Bin	False	True	358371	1
Bin	True	False	481	1
Bin	True	True	70767	1

"and" expression on lines 180 to 181:

 is_transmitter = '1' and err_detected = '1' 
 <-------LHS-------->     <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	True	52223	1
Bin	True	False	146038	1
Bin	True	True	71248	1

"=" expression on line 180:

is_transmitter = '1'

	Evaluated to	Count	Threshold
Bin	False	214729	1
Bin	True	217286	1

"=" expression on line 181:

err_detected = '1'

	Evaluated to	Count	Threshold
Bin	False	308544	1
Bin	True	123471	1

"=" expression on line 182:

err_ctrs_unchanged = '0'

	Evaluated to	Count	Threshold
Bin	False	2877	1
Bin	True	429138	1

"or" expression on line 183:

 err_delim_late = '1' or bit_err_after_ack_err = '1' 
 <-------LHS-------->    <-----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	False	360850	1
Bin	False	True	8	1
Bin	True	False	390	1

"=" expression on line 183:

err_delim_late = '1'

	Evaluated to	Count	Threshold
Bin	False	360858	1
Bin	True	390	1

"=" expression on line 183:

bit_err_after_ack_err = '1'

	Evaluated to	Count	Threshold
Bin	False	361240	1
Bin	True	8	1

"or" expression on line 189:

 decrement_rec = '1' or tran_valid = '1' 
 <-------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	False	30896	1
Bin	False	True	11112	1
Bin	True	False	14981	1

"=" expression on line 189:

decrement_rec = '1'

	Evaluated to	Count	Threshold
Bin	False	42008	1
Bin	True	14981	1

"=" expression on line 189:

tran_valid = '1'

	Evaluated to	Count	Threshold
Bin	False	45877	1
Bin	True	11112	1

"and" expression on line 197:

 inc_one_i = '1' and mr_mode_rom = ROM_DISABLED 
 <-----LHS----->     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	46462	1
Bin	True	False	7413	1
Bin	True	True	44810	1

"=" expression on line 197:

inc_one_i = '1'

	Evaluated to	Count	Threshold
Bin	False	57128	1
Bin	True	52223	1

"=" expression on line 197:

mr_mode_rom = ROM_DISABLED

	Evaluated to	Count	Threshold
Bin	False	18079	1
Bin	True	91272	1

"and" expression on line 200:

 inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED 
 <------LHS------>     <----------RHS----------->

	LHS	RHS	Count	Threshold
Bin	False	True	82333	1
Bin	True	True	80681	1

"=" expression on line 200:

inc_eight_i = '1'

	Evaluated to	Count	Threshold
Bin	False	85586	1
Bin	True	80681	1

"=" expression on line 200:

mr_mode_rom = ROM_DISABLED

	Evaluated to	Count	Threshold
Bin	False	3253	1
Bin	True	163014	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_RULES_INST

File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/fault_confinement.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 164 to 166:

Signal assignment statement on line 164:

Signal assignment statement on line 166:

If statement on lines 178 to 184:

Signal assignment statement on line 178:

Signal assignment statement on line 179:

Signal assignment statement on line 180:

Signal assignment statement on line 183:

Signal assignment statement on line 184:

If statement on lines 189 to 191:

Signal assignment statement on line 189:

Signal assignment statement on line 191:

If statement on lines 197 to 199:

Signal assignment statement on line 197:

Signal assignment statement on line 199:

If statement on lines 200 to 202:

Signal assignment statement on line 200:

Signal assignment statement on line 202:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 164:

"if" / "when" / "else" condition on line 178:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on lines 180 to 182:

"if" / "when" / "else" condition on line 183:

"if" / "when" / "else" condition on line 189:

"if" / "when" / "else" condition on line 197:

"if" / "when" / "else" condition on line 200:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Port:

Signal:

Signal:

Uncovered expressions:

"and" expression on line 200:

Excluded expressions:

Covered expressions:

"and" expression on line 164:

"and" expression on line 164:

"=" expression on line 164:

"=" expression on line 164:

"=" expression on line 164:

"and" expression on line 178:

"=" expression on line 178:

"=" expression on line 178:

"and" expression on line 179:

"=" expression on line 179:

"=" expression on line 179:

"and" expression on lines 180 to 182:

"and" expression on lines 180 to 181:

"=" expression on line 180:

"=" expression on line 181:

"=" expression on line 182:

"or" expression on line 183:

"=" expression on line 183:

"=" expression on line 183: