Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.FAULT_CONFINEMENT_RULES_INST
Sub-instances:
| Instance |
Statement |
Branch |
Toggle |
Expression |
FSM state |
Functional |
Average |
Current Instance:
Details:
The limit of printed items was reached (5000). Total 261615 items are not displayed.
Covered statements:
If statement:
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
165: else
166: '0'; Count: 352246
Threshold: 1
Signal assignment statement:
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') Count: 52292
Threshold: 1
Signal assignment statement:
166: '0'; Count: 299954
Threshold: 1
If statement:
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else
...
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else
184: '0'; Count: 438019
Threshold: 1
Signal assignment statement:
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else Count: 7990
Threshold: 1
Signal assignment statement:
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else Count: 1510
Threshold: 1
Signal assignment statement:
180: '1' when (is_transmitter = '1' and Count: 69504
Threshold: 1
Signal assignment statement:
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else Count: 398
Threshold: 1
Signal assignment statement:
184: '0'; Count: 358617
Threshold: 1
If statement:
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')
190: else
191: '0'; Count: 56960
Threshold: 1
Signal assignment statement:
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') Count: 26080
Threshold: 1
Signal assignment statement:
191: '0'; Count: 30880
Threshold: 1
If statement:
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)
198: else
199: '0'; Count: 109486
Threshold: 1
Signal assignment statement:
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) Count: 44878
Threshold: 1
Signal assignment statement:
199: '0'; Count: 64608
Threshold: 1
If statement:
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
201: else
202: '0'; Count: 163642
Threshold: 1
Signal assignment statement:
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) Count: 79370
Threshold: 1
Signal assignment statement:
202: '0'; Count: 84272
Threshold: 1
Covered branches:
"if" / "when" / "else" condition:
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 52292 | 1 |
| Bin | False | 299954 | 1 |
"if" / "when" / "else" condition:
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 7990 | 1 |
| Bin | False | 430029 | 1 |
"if" / "when" / "else" condition:
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 1510 | 1 |
| Bin | False | 428519 | 1 |
"if" / "when" / "else" condition:
180: '1' when (is_transmitter = '1' and
181: err_detected = '1' and
182: err_ctrs_unchanged = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 69504 | 1 |
| Bin | False | 359015 | 1 |
"if" / "when" / "else" condition:
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | True | 398 | 1 |
| Bin | False | 358617 | 1 |
"if" / "when" / "else" condition:
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | True | 26080 | 1 |
| Bin | False | 30880 | 1 |
"if" / "when" / "else" condition:
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 44878 | 1 |
| Bin | False | 64608 | 1 |
"if" / "when" / "else" condition:
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | True | 79370 | 1 |
| Bin | False | 84272 | 1 |
Covered toggles:
Port:
CLK_SYS | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 527578869 | 1 |
| Bin | 1 | 0 | 527580460 | 1 |
Port:
IS_TRANSMITTER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19892 | 1 |
| Bin | 1 | 0 | 21492 | 1 |
Port:
IS_RECEIVER | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 30888 | 1 |
| Bin | 1 | 0 | 32482 | 1 |
Port:
ERR_DETECTED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 123242 | 1 |
| Bin | 1 | 0 | 124842 | 1 |
Port:
ERR_CTRS_UNCHANGED | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 791 | 1 |
| Bin | 1 | 0 | 2391 | 1 |
Port:
PRIMARY_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 22658 | 1 |
| Bin | 1 | 0 | 24258 | 1 |
Port:
ACT_ERR_OVR_FLAG | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 19607 | 1 |
| Bin | 1 | 0 | 21205 | 1 |
Port:
ERR_DELIM_LATE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 390 | 1 |
| Bin | 1 | 0 | 1990 | 1 |
Port:
TRAN_VALID | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 11098 | 1 |
| Bin | 1 | 0 | 12698 | 1 |
Port:
DECREMENT_REC | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 14982 | 1 |
| Bin | 1 | 0 | 16582 | 1 |
Port:
BIT_ERR_AFTER_ACK_ERR | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 8 | 1 |
| Bin | 1 | 0 | 1608 | 1 |
Port:
MR_MODE_ROM | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 51 | 1 |
| Bin | 1 | 0 | 1651 | 1 |
Port:
INC_ONE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 44878 | 1 |
| Bin | 1 | 0 | 46478 | 1 |
Port:
INC_EIGHT | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79370 | 1 |
| Bin | 1 | 0 | 80970 | 1 |
Port:
DEC_ONE | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 26080 | 1 |
| Bin | 1 | 0 | 27680 | 1 |
Signal:
INC_ONE_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 52292 | 1 |
| Bin | 1 | 0 | 53892 | 1 |
Signal:
INC_EIGHT_I | From | To | Count | Threshold |
|---|
| Bin | 0 | 1 | 79370 | 1 |
| Bin | 1 | 0 | 80970 | 1 |
Excluded expressions:
"and" expression
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
<------LHS------> <----------RHS-----------> | LHS | RHS | Count | Threshold | Excluded due to |
|---|
| Bin | True | False | 0 | 1 | Exclude file |
Covered expressions:
"=" expression
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 228940 | 1 |
| Bin | True | 123306 | 1 |
"=" expression
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 24163 | 1 |
| Bin | True | 328083 | 1 |
"and" expression
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
<------LHS-------> <--------RHS---------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 206287 | 1 |
| Bin | True | False | 1510 | 1 |
| Bin | True | True | 121796 | 1 |
"=" expression
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 200188 | 1 |
| Bin | True | 152058 | 1 |
"and" expression
164: inc_one_i <= '1' when (err_detected = '1' and act_err_ovr_flag = '0' and is_receiver = '1')
<--------------------LHS--------------------> <------RHS------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 99766 | 1 |
| Bin | True | False | 69504 | 1 |
| Bin | True | True | 52292 | 1 |
"=" expression
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 415361 | 1 |
| Bin | True | 22658 | 1 |
"=" expression
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 269821 | 1 |
| Bin | True | 168198 | 1 |
"and" expression
178: inc_eight_i <= '1' when (primary_err = '1' and is_receiver = '1') else
<------LHS------> <------RHS------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 160208 | 1 |
| Bin | True | False | 14668 | 1 |
| Bin | True | True | 7990 | 1 |
"=" expression
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 407466 | 1 |
| Bin | True | 22563 | 1 |
"=" expression
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 306245 | 1 |
| Bin | True | 123784 | 1 |
"and" expression
179: '1' when (act_err_ovr_flag = '1' and err_detected = '1') else
<--------LHS---------> <------RHS-------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 122274 | 1 |
| Bin | True | False | 21053 | 1 |
| Bin | True | True | 1510 | 1 |
"=" expression
180: '1' when (is_transmitter = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 214341 | 1 |
| Bin | True | 214178 | 1 |
"=" expression
181: err_detected = '1' and | Evaluated to | Count | Threshold |
|---|
| Bin | False | 306245 | 1 |
| Bin | True | 122274 | 1 |
"and" expression
180: '1' when (is_transmitter = '1' and
181: err_detected = '1' and | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 52292 | 1 |
| Bin | True | False | 144196 | 1 |
| Bin | True | True | 69982 | 1 |
"=" expression
182: err_ctrs_unchanged = '0') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 2869 | 1 |
| Bin | True | 425650 | 1 |
"and" expression
180: '1' when (is_transmitter = '1' and
181: err_detected = '1' and
182: err_ctrs_unchanged = '0') else | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 356146 | 1 |
| Bin | True | False | 478 | 1 |
| Bin | True | True | 69504 | 1 |
"=" expression
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 358625 | 1 |
| Bin | True | 390 | 1 |
"=" expression
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else | Evaluated to | Count | Threshold |
|---|
| Bin | False | 359007 | 1 |
| Bin | True | 8 | 1 |
"or" expression
183: '1' when (err_delim_late = '1' or bit_err_after_ack_err = '1') else
<-------LHS--------> <-----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 358617 | 1 |
| Bin | False | True | 8 | 1 |
| Bin | True | False | 390 | 1 |
"=" expression
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 41978 | 1 |
| Bin | True | 14982 | 1 |
"=" expression
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1') | Evaluated to | Count | Threshold |
|---|
| Bin | False | 45862 | 1 |
| Bin | True | 11098 | 1 |
"or" expression
189: dec_one <= '1' when (decrement_rec = '1' or tran_valid = '1')
<-------LHS-------> <-----RHS------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | False | 30880 | 1 |
| Bin | False | True | 11098 | 1 |
| Bin | True | False | 14982 | 1 |
"=" expression
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 57194 | 1 |
| Bin | True | 52292 | 1 |
"=" expression
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 18079 | 1 |
| Bin | True | 91407 | 1 |
"and" expression
197: inc_one <= '1' when (inc_one_i = '1' and mr_mode_rom = ROM_DISABLED)
<-----LHS-----> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 46529 | 1 |
| Bin | True | False | 7414 | 1 |
| Bin | True | True | 44878 | 1 |
"=" expression
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 84272 | 1 |
| Bin | True | 79370 | 1 |
"=" expression
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED) | Evaluated to | Count | Threshold |
|---|
| Bin | False | 3251 | 1 |
| Bin | True | 160391 | 1 |
"and" expression
200: inc_eight <= '1' when (inc_eight_i = '1' and mr_mode_rom = ROM_DISABLED)
<------LHS------> <----------RHS-----------> | LHS | RHS | Count | Threshold |
|---|
| Bin | False | True | 81021 | 1 |
| Bin | True | True | 79370 | 1 |
Uncovered functional coverage:
Excluded functional coverage:
Covered functional coverage: