File: /__w/ctu-can-regression/ctu-can-regression/src/memory_registers/generated/test_registers_reg_map.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Register map implementation of: Test_registers
70: --------------------------------------------------------------------------------
71: -- This file is autogenerated, DO NOT EDIT!
72:
73: Library ieee;
74: use ieee.std_logic_1164.all;
75:
76: Library ctu_can_fd_rtl;
77: use ctu_can_fd_rtl.can_registers_pkg.all;
78: use ctu_can_fd_rtl.cmn_reg_map_pkg.all;
79:
80: entity test_registers_reg_map is
81: generic (
82: constant DATA_WIDTH : natural := 32;
83: constant ADDRESS_WIDTH : natural := 8;
84: constant REGISTERED_READ : boolean := true;
85: constant CLEAR_READ_DATA : boolean := true
86: );
87: port (
88: signal clk_sys :in std_logic;
89: signal res_n :in std_logic;
90: signal address :in std_logic_vector(address_width - 1 downto 0);
91: signal w_data :in std_logic_vector(data_width - 1 downto 0);
92: signal r_data :out std_logic_vector(data_width - 1 downto 0);
93: signal cs :in std_logic;
94: signal read :in std_logic;
95: signal write :in std_logic;
96: signal be :in std_logic_vector(data_width / 8 - 1 downto 0);
97: signal lock_1 :in std_logic;
98: signal lock_2 :in std_logic;
99: signal test_registers_out :out Test_registers_out_t;
100: signal test_registers_in :in Test_registers_in_t
101: );
102: end entity test_registers_reg_map;
103:
104:
105: architecture rtl of test_registers_reg_map is
106: signal reg_sel : std_logic_vector(3 downto 0);
107: constant ADDR_VECT
108: : std_logic_vector(23 downto 0) := "000011000010000001000000";
109: signal r_data_comb : std_logic_vector(31 downto 0);
110: signal read_data_mask_n : std_logic_vector(31 downto 0);
111: signal test_registers_out_i : Test_registers_out_t;
112: signal write_en : std_logic_vector(3 downto 0);
113: begin
114:
115: write_en <= be when (write = '1' and cs = '1') else (others => '0');
116:
117: ----------------------------------------------------------------------------
118: -- Write address to One-hot decoder
119: ----------------------------------------------------------------------------
120:
121: address_decoder_test_registers_comp : address_decoder
122: generic map(
123: address_width => 6 ,
124: address_entries => 4 ,
125: addr_vect => ADDR_VECT ,
126: registered_out => false
127: )
128: port map(
129: clk_sys => clk_sys ,-- in
130: res_n => res_n ,-- in
131: address => address(7 downto 2) ,-- in
132: enable => cs ,-- in
133: addr_dec => reg_sel -- out
134: );
135:
136: ----------------------------------------------------------------------------
137: -- TST_CONTROL[TMAENA]
138: ----------------------------------------------------------------------------
139:
140: tst_control_tmaena_reg_comp : memory_reg_rw_lock
141: generic map(
142: data_width => 1 ,
143: reset_value => "0"
144: )
145: port map(
146: clk_sys => clk_sys ,-- in
147: res_n => res_n ,-- in
148: data_in => w_data(0 downto 0) ,-- in
149: write => write_en(0) ,-- in
150: cs => reg_sel(0) ,-- in
151: lock => lock_1 ,-- in
152: reg_value(0) => test_registers_out_i.tst_control_tmaena -- out
153: );
154:
155: ----------------------------------------------------------------------------
156: -- TST_CONTROL[TWRSTB]
157: ----------------------------------------------------------------------------
158:
159: tst_control_twrstb_reg_comp : memory_reg_os_lock
160: generic map(
161: data_width => 1 ,
162: reset_value => "0"
163: )
164: port map(
165: clk_sys => clk_sys ,-- in
166: res_n => res_n ,-- in
167: data_in => w_data(1 downto 1) ,-- in
168: write => write_en(0) ,-- in
169: cs => reg_sel(0) ,-- in
170: lock => lock_1 ,-- in
171: reg_value(0) => test_registers_out_i.tst_control_twrstb -- out
172: );
173:
174: ----------------------------------------------------------------------------
175: -- TST_DEST[TST_ADDR_SLICE_1]
176: ----------------------------------------------------------------------------
177:
178: tst_dest_tst_addr_slice_1_reg_comp : memory_reg_rw_lock
179: generic map(
180: data_width => 8 ,
181: reset_value => "00000000"
182: )
183: port map(
184: clk_sys => clk_sys ,-- in
185: res_n => res_n ,-- in
186: data_in => w_data(7 downto 0) ,-- in
187: write => write_en(0) ,-- in
188: cs => reg_sel(1) ,-- in
189: lock => lock_1 ,-- in
190: reg_value => test_registers_out_i.tst_dest_tst_addr(7 downto 0) -- out
191: );
192:
193: ----------------------------------------------------------------------------
194: -- TST_DEST[TST_ADDR_SLICE_2]
195: ----------------------------------------------------------------------------
196:
197: tst_dest_tst_addr_slice_2_reg_comp : memory_reg_rw_lock
198: generic map(
199: data_width => 8 ,
200: reset_value => "00000000"
201: )
202: port map(
203: clk_sys => clk_sys ,-- in
204: res_n => res_n ,-- in
205: data_in => w_data(15 downto 8) ,-- in
206: write => write_en(1) ,-- in
207: cs => reg_sel(1) ,-- in
208: lock => lock_1 ,-- in
209: reg_value => test_registers_out_i.tst_dest_tst_addr(15 downto 8) -- out
210: );
211:
212: ----------------------------------------------------------------------------
213: -- TST_DEST[TST_MTGT]
214: ----------------------------------------------------------------------------
215:
216: tst_dest_tst_mtgt_reg_comp : memory_reg_rw_lock
217: generic map(
218: data_width => 4 ,
219: reset_value => "0000"
220: )
221: port map(
222: clk_sys => clk_sys ,-- in
223: res_n => res_n ,-- in
224: data_in => w_data(19 downto 16) ,-- in
225: write => write_en(2) ,-- in
226: cs => reg_sel(1) ,-- in
227: lock => lock_1 ,-- in
228: reg_value => test_registers_out_i.tst_dest_tst_mtgt -- out
229: );
230:
231: ----------------------------------------------------------------------------
232: -- TST_WDATA[TST_WDATA_SLICE_1]
233: ----------------------------------------------------------------------------
234:
235: tst_wdata_tst_wdata_slice_1_reg_comp : memory_reg_rw_lock
236: generic map(
237: data_width => 8 ,
238: reset_value => "00000000"
239: )
240: port map(
241: clk_sys => clk_sys ,-- in
242: res_n => res_n ,-- in
243: data_in => w_data(7 downto 0) ,-- in
244: write => write_en(0) ,-- in
245: cs => reg_sel(2) ,-- in
246: lock => lock_1 ,-- in
247: reg_value => test_registers_out_i.tst_wdata_tst_wdata(7 downto 0) -- out
248: );
249:
250: ----------------------------------------------------------------------------
251: -- TST_WDATA[TST_WDATA_SLICE_2]
252: ----------------------------------------------------------------------------
253:
254: tst_wdata_tst_wdata_slice_2_reg_comp : memory_reg_rw_lock
255: generic map(
256: data_width => 8 ,
257: reset_value => "00000000"
258: )
259: port map(
260: clk_sys => clk_sys ,-- in
261: res_n => res_n ,-- in
262: data_in => w_data(15 downto 8) ,-- in
263: write => write_en(1) ,-- in
264: cs => reg_sel(2) ,-- in
265: lock => lock_1 ,-- in
266: reg_value => test_registers_out_i.tst_wdata_tst_wdata(15 downto 8) -- out
267: );
268:
269: ----------------------------------------------------------------------------
270: -- TST_WDATA[TST_WDATA_SLICE_3]
271: ----------------------------------------------------------------------------
272:
273: tst_wdata_tst_wdata_slice_3_reg_comp : memory_reg_rw_lock
274: generic map(
275: data_width => 8 ,
276: reset_value => "00000000"
277: )
278: port map(
279: clk_sys => clk_sys ,-- in
280: res_n => res_n ,-- in
281: data_in => w_data(23 downto 16) ,-- in
282: write => write_en(2) ,-- in
283: cs => reg_sel(2) ,-- in
284: lock => lock_1 ,-- in
285: reg_value => test_registers_out_i.tst_wdata_tst_wdata(23 downto 16) -- out
286: );
287:
288: ----------------------------------------------------------------------------
289: -- TST_WDATA[TST_WDATA_SLICE_4]
290: ----------------------------------------------------------------------------
291:
292: tst_wdata_tst_wdata_slice_4_reg_comp : memory_reg_rw_lock
293: generic map(
294: data_width => 8 ,
295: reset_value => "00000000"
296: )
297: port map(
298: clk_sys => clk_sys ,-- in
299: res_n => res_n ,-- in
300: data_in => w_data(31 downto 24) ,-- in
301: write => write_en(3) ,-- in
302: cs => reg_sel(2) ,-- in
303: lock => lock_1 ,-- in
304: reg_value => test_registers_out_i.tst_wdata_tst_wdata(31 downto 24) -- out
305: );
306:
307: ----------------------------------------------------------------------------
308: -- Read data multiplexor
309: ----------------------------------------------------------------------------
310: with address(7 downto 2) select r_data_comb <=
311: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
312: test_registers_out_i.tst_control_twrstb &
313: test_registers_out_i.tst_control_tmaena when "000000",
314: '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' &
315: test_registers_out_i.tst_dest_tst_mtgt &
316: test_registers_out_i.tst_dest_tst_addr when "000001",
317: test_registers_out_i.tst_wdata_tst_wdata when "000010",
318: test_registers_in.tst_rdata_tst_rdata when "000011",
319: (others => '0') when others;
320:
321: ----------------------------------------------------------------------------
322: -- Output register
323: ----------------------------------------------------------------------------
324: read_data_reg_proc : process(res_n, clk_sys)
325: begin
326: if (res_n = '0') then
327: r_data <= (others => '0');
328: elsif (rising_edge(clk_sys)) then
329: if (cs = '1' and read = '1') then
330: r_data <= r_data_comb and read_data_mask_n;
331: end if;
332: end if;
333: end process;
334:
335: ----------------------------------------------------------------------------
336: -- Read data mask - Byte enables
337: ----------------------------------------------------------------------------
338: read_data_mask_n <=
339: be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) & be(3) &
340: be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) & be(2) &
341: be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) & be(1) &
342: be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) & be(0) ;
343:
344: Test_registers_out <= Test_registers_out_i;
345:
346: -- <RELEASE_OFF>
347: ----------------------------------------------------------------------------
348: -- Functional coverage
349: ----------------------------------------------------------------------------
350: -- psl default clock is rising_edge(clk_sys);
351: -- psl tst_control_write_access_cov : cover
352: -- {((cs='1') and (write='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
353:
354: -- psl tst_control_read_access_cov : cover
355: -- {((cs='1') and (read='1') and (reg_sel(0)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
356:
357: -- psl tst_dest_write_access_cov : cover
358: -- {((cs='1') and (write='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
359:
360: -- psl tst_dest_read_access_cov : cover
361: -- {((cs='1') and (read='1') and (reg_sel(1)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
362:
363: -- psl tst_wdata_write_access_cov : cover
364: -- {((cs='1') and (write='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
365:
366: -- psl tst_wdata_read_access_cov : cover
367: -- {((cs='1') and (read='1') and (reg_sel(2)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
368:
369: -- psl tst_rdata_read_access_cov : cover
370: -- {((cs='1') and (read='1') and (reg_sel(3)='1') and ((be(0)='1') or (be(1)='1') or (be(2)='1') or (be(3)='1')))};
371:
372: -- <RELEASE_ON>
373:
374: end architecture rtl;