File: /__w/ctu-can-regression/ctu-can-regression/src/bus_sampling/bus_sampling.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Bus sampling
71: --
72: -- Sub-modules:
73: -- 1. CAN RX synchronisation chain
74: -- 2. Transceiver Delay measurement
75: -- 3. Data edge detector
76: -- 4. Secondary sampling point shift register.
77: -- 5. TX Data cache.
78: -- 6. Bit Error detector.
79: -- 7. Sample multiplexor.
80: --------------------------------------------------------------------------------
81:
82: Library ieee;
83: use ieee.std_logic_1164.all;
84: use ieee.numeric_std.ALL;
85:
86: Library ctu_can_fd_rtl;
87: use ctu_can_fd_rtl.can_constants_pkg.all;
88: use ctu_can_fd_rtl.can_types_pkg.all;
89:
90: use ctu_can_fd_rtl.CAN_FD_register_map.all;
91: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
92:
93: entity bus_sampling is
94: generic (
95: -- Secondary sampling point Shift registers length
96: G_SSP_DELAY_SAT_VAL : natural;
97:
98: -- Depth of FIFO Cache for TX Data
99: G_TX_CACHE_DEPTH : natural;
100:
101: -- Size of TX Data cache pointer
102: G_TX_CACHE_PTR_WIDTH : natural;
103:
104: -- Width (number of bits) in transceiver delay measurement counter
105: G_TRV_CTR_WIDTH : natural;
106:
107: -- Width of SSP position
108: G_SSP_POS_WIDTH : natural;
109:
110: -- Width of SSP offset
111: G_SSP_OFFSET_WIDTH : natural;
112:
113: -- Width of SSP generator counters (BTMC, SSPC)
114: G_SSP_CTRS_WIDTH : natural
115: );
116: port (
117: -------------------------------------------------------------------------------------------
118: -- Clock and Async reset
119: -------------------------------------------------------------------------------------------
120: clk_sys :in std_logic;
121: res_n :in std_logic;
122:
123: -------------------------------------------------------------------------------------------
124: -- DFT support
125: -------------------------------------------------------------------------------------------
126: scan_enable :in std_logic;
127:
128: -------------------------------------------------------------------------------------------
129: -- Physical layer interface
130: -------------------------------------------------------------------------------------------
131: -- CAN serial stream output
132: can_rx :in std_logic;
133:
134: -- CAN serial stream input
135: can_tx :out std_logic;
136:
137: -------------------------------------------------------------------------------------------
138: -- Memory registers interface
139: -------------------------------------------------------------------------------------------
140: mr_settings_ena :in std_logic;
141: mr_ssp_cfg_ssp_offset :in std_logic_vector(7 downto 0);
142: mr_ssp_cfg_ssp_src :in std_logic_vector(1 downto 0);
143:
144: -- Measured Transceiver delay
145: trv_delay :out std_logic_vector(G_TRV_CTR_WIDTH - 1 downto 0);
146:
147: -------------------------------------------------------------------------------------------
148: -- Prescaler interface
149: -------------------------------------------------------------------------------------------
150: -- RX Trigger
151: rx_trigger :in std_logic;
152:
153: -- TX Trigger
154: tx_trigger :in std_logic;
155:
156: -- Valid synchronisation edge appeared (Recessive to Dominant)
157: sync_edge :out std_logic;
158:
159: -- Time quanta edge
160: tq_edge :in std_logic;
161:
162: -------------------------------------------------------------------------------------------
163: -- CAN Core Interface
164: -------------------------------------------------------------------------------------------
165: -- TX data
166: tx_data_wbs :in std_logic;
167:
168: -- RX data
169: rx_data_wbs :out std_logic;
170:
171: -- Sample control
172: sp_control :in std_logic_vector(1 downto 0);
173:
174: -- Reset for Secondary Sampling point Shift register.
175: ssp_reset :in std_logic;
176:
177: -- Measure transmitter delay
178: tran_delay_meas :in std_logic;
179:
180: -- Bit error detected
181: bit_err :out std_logic;
182:
183: -- Reset Bit time measurement counter
184: btmc_reset :in std_logic;
185:
186: -- Start Measurement of data bit time (in TX Trigger)
187: dbt_measure_start :in std_logic;
188:
189: -- First SSP generated (in ESI bit)
190: gen_first_ssp :in std_logic;
191:
192: -- Bit error detection is enabled
193: bit_err_enable :in std_logic
194: );
195: end entity;
196:
197: architecture rtl of bus_sampling is
198:
199: -------------------------------------------------------------------------------------------
200: -- Internal registers and signals
201: -------------------------------------------------------------------------------------------
202: -- CAN RX Data (Synchronised)
203: signal data_rx_synced : std_logic;
204:
205: -- Bus sampling and edge detection, Previously sampled value on CAN bus
206: signal prev_sample : std_logic;
207:
208: -- Secondary sampling signal (sampling with transciever delay compensation)
209: signal sample_sec : std_logic;
210:
211: -- Delayed TX Data from TX Data shift register at position of secondary
212: -- sampling point.
213: signal data_tx_delayed : std_logic;
214:
215: -- Appropriate edge appeared at recieved data
216: signal edge_rx_valid : std_logic;
217:
218: -- Edge appeared at transcieved data
219: signal edge_tx_valid : std_logic;
220:
221: --Note: Bit Error is set up at sample point for whole bit
222: -- time until next sample point!!!!!
223:
224: -- SSP delay. Calculated from trv_delay either directly or by offseting
225: -- by ssp_offset.
226: signal ssp_delay : std_logic_vector(G_SSP_POS_WIDTH - 1 downto 0);
227:
228: -- TX Trigger delayed by 1 clock cycle
229: signal tx_trigger_q : std_logic;
230:
231: -- TX Trigger (used for SSP)
232: signal tx_trigger_ssp : std_logic;
233:
234: -------------------------------------------------------------------------------------------
235: -- Reset for shift registers. This is used instead of shift register with preload to lower
236: -- the resource usage! Resetting and preloading to the same value can be merged into just
237: -- resetting by OR of sources.
238: -------------------------------------------------------------------------------------------
239: signal shift_regs_res_d : std_logic;
240: signal shift_regs_res_q_scan : std_logic;
241:
242: -- Enable for secondary sampling point shift register
243: signal ssp_enable : std_logic;
244:
245: begin
246:
247: -------------------------------------------------------------------------------------------
248: -- Synchronisation chain for input signal
249: -------------------------------------------------------------------------------------------
250: can_rx_sig_sync_inst : entity ctu_can_fd_rtl.sig_sync
251: generic map (
252: G_RESET_POLARITY => '0',
253: G_RESET_VALUE => RECESSIVE
254: )
255: port map(
256: arst => res_n, -- IN
257: clk => clk_sys, -- IN
258: async => can_rx, -- IN
259:
260: sync => data_rx_synced -- OUT
261: );
262:
263: -------------------------------------------------------------------------------------------
264: -- Unit for measurement of transceiver delay and calculation of secondary sampling point.
265: -------------------------------------------------------------------------------------------
266: trv_delay_measurement_inst : entity ctu_can_fd_rtl.trv_delay_measurement
267: generic map (
268: G_TRV_CTR_WIDTH => G_TRV_CTR_WIDTH,
269: G_SSP_POS_WIDTH => G_SSP_POS_WIDTH,
270: G_SSP_OFFSET_WIDTH => G_SSP_OFFSET_WIDTH,
271: G_SSP_SATURATION_LVL => G_SSP_DELAY_SAT_VAL
272: )
273: port map (
274: clk_sys => clk_sys, -- IN
275: res_n => res_n, -- IN
276:
277: scan_enable => scan_enable, -- IN
278:
279: edge_tx_valid => edge_tx_valid, -- IN
280: edge_rx_valid => edge_rx_valid, -- IN
281: tran_delay_meas => tran_delay_meas, -- IN
282: mr_ssp_cfg_ssp_offset => mr_ssp_cfg_ssp_offset, -- IN
283: mr_ssp_cfg_ssp_src => mr_ssp_cfg_ssp_src, -- IN
284:
285: trv_delay_shadowed => trv_delay, -- OUT
286: ssp_delay_shadowed => ssp_delay -- OUT
287: );
288:
289:
290:
291: -------------------------------------------------------------------------------------------
292: -- Edge detector on TX, RX Data
293: -------------------------------------------------------------------------------------------
294: data_edge_detector_inst : entity ctu_can_fd_rtl.data_edge_detector
295: port map (
296: clk_sys => clk_sys, -- IN
297: res_n => res_n, -- IN
298: tx_data => tx_data_wbs, -- IN
299: rx_data => data_rx_synced, -- IN
300: prev_rx_sample => prev_sample, -- IN
301: tq_edge => tq_edge, -- IN
302:
303: tx_edge => edge_tx_valid, -- OUT
304: rx_edge => edge_rx_valid, -- OUT
305: sync_edge => sync_edge -- OUT
306: );
307:
308:
309: -------------------------------------------------------------------------------------------
310: -- Reset for shift registers for secondary sampling point
311: -------------------------------------------------------------------------------------------
312: shift_regs_res_d <= '0' when (ssp_reset = '1') else
313: '1';
314:
315: -------------------------------------------------------------------------------------------
316: -- Pipeline reset for shift registers to avoid glitches!
317: -------------------------------------------------------------------------------------------
318: shift_regs_rst_reg_inst : entity ctu_can_fd_rtl.rst_reg
319: generic map (
320: G_RESET_POLARITY => '0'
321: )
322: port map (
323: -- Clock and Reset
324: clk => clk_sys, -- IN
325: arst => res_n, -- IN
326:
327: -- Flip flop input / output
328: d => shift_regs_res_d, -- IN
329: q => shift_regs_res_q_scan, -- OUT
330:
331: -- Scan mode control
332: scan_enable => scan_enable -- IN
333: );
334:
335: -------------------------------------------------------------------------------------------
336: -- Create delayed TX Trigger one clock cycle after Stuff pipeline stage.
337: -------------------------------------------------------------------------------------------
338: tx_trigger_reg_inst : entity ctu_can_fd_rtl.dff_arst
339: generic map (
340: G_RESET_POLARITY => '0',
341: G_RST_VAL => '0'
342: )
343: port map (
344: arst => res_n, -- IN
345: clk => clk_sys, -- IN
346: reg_d => tx_trigger, -- IN
347:
348: reg_q => tx_trigger_q -- OUT
349: );
350:
351: -------------------------------------------------------------------------------------------
352: -- Generator of secondary sampling point
353: -------------------------------------------------------------------------------------------
354: ssp_generator_inst : entity ctu_can_fd_rtl.ssp_generator
355: generic map (
356: G_SSP_CTRS_WIDTH => G_SSP_CTRS_WIDTH,
357: G_SSP_POS_WIDTH => G_SSP_POS_WIDTH
358: )
359: port map (
360: -- Clock and Async reset
361: clk_sys => clk_sys, -- (IN)
362: res_n => res_n, -- (IN)
363:
364: -- Control signals
365: btmc_reset => btmc_reset, -- (IN)
366: dbt_measure_start => dbt_measure_start, -- (IN)
367: gen_first_ssp => gen_first_ssp, -- (IN)
368: ssp_delay => ssp_delay, -- (IN)
369: ssp_enable => ssp_enable, -- (IN)
370:
371: -- Trigger signals
372: tx_trigger => tx_trigger, -- (IN)
373: sample_sec => sample_sec -- (OUT)
374: );
375:
376: -- Secondary sampling point shift register clock enable
377: ssp_enable <= '1' when (sp_control = SECONDARY_SAMPLE) else
378: '0';
379:
380: -------------------------------------------------------------------------------------------
381: -- Secondary sampling point input: Delayed TX Trigger gated and available only during
382: -- secondary sampling! TX trigger for storing data to TX cache must be delayed since TX
383: -- data will be one output of Bit Stuffing only one clock cycle after TX Trigger!
384: -------------------------------------------------------------------------------------------
385: tx_trigger_ssp <= '1' when (tx_trigger_q = '1' and sp_control = SECONDARY_SAMPLE)
386: else
387: '0';
388:
389: -------------------------------------------------------------------------------------------
390: -- TX DATA Cache. Stores TX Data when Sample point enters the SSP shift register and reads
391: -- data when Sample point steps out of shift register. This gets the TX data which
392: -- correspond to the RX Bit in Secondary sampling point.
393: -------------------------------------------------------------------------------------------
394: tx_data_cache_inst : entity ctu_can_fd_rtl.tx_data_cache
395: generic map (
396: G_TX_CACHE_DEPTH => G_TX_CACHE_DEPTH,
397: G_TX_CACHE_RST_VAL => RECESSIVE,
398: G_TX_CACHE_PTR_WIDTH => G_TX_CACHE_PTR_WIDTH
399: )
400: port map (
401: clk_sys => clk_sys, -- IN
402: res_n => shift_regs_res_q_scan, -- IN
403: write => tx_trigger_ssp, -- IN
404: read => sample_sec, -- IN
405: data_in => tx_data_wbs, -- IN
406:
407: data_out => data_tx_delayed -- OUT
408: );
409:
410:
411: -------------------------------------------------------------------------------------------
412: -- Bit error detector
413: -------------------------------------------------------------------------------------------
414: bit_err_detector_inst : entity ctu_can_fd_rtl.bit_err_detector
415: port map (
416: clk_sys => clk_sys, -- IN
417: res_n => res_n, -- IN
418: mr_settings_ena => mr_settings_ena, -- IN
419: sp_control => sp_control, -- IN
420: rx_trigger => rx_trigger, -- IN
421: sample_sec => sample_sec, -- IN
422: bit_err_enable => bit_err_enable, -- IN
423: data_tx => tx_data_wbs, -- IN
424: data_tx_delayed => data_tx_delayed, -- IN
425: data_rx_synced => data_rx_synced, -- IN
426:
427: bit_err => bit_err -- OUT
428: );
429:
430: -------------------------------------------------------------------------------------------
431: -- Sampling of bus value
432: -------------------------------------------------------------------------------------------
433: sample_mux_inst : entity ctu_can_fd_rtl.sample_mux
434: port map (
435: clk_sys => clk_sys, -- IN
436: res_n => res_n, -- IN
437: mr_settings_ena => mr_settings_ena, -- IN
438: sp_control => sp_control, -- IN
439: rx_trigger => rx_trigger, -- IN
440: sample_sec => sample_sec, -- IN
441: data_rx_synced => data_rx_synced, -- IN
442:
443: prev_sample => prev_sample -- OUT
444: );
445:
446: -- Output data propagation - Pipe directly - no delay
447: can_tx <= tx_data_wbs;
448:
449: -- RX Data for bit destuffing - Output of re-synchroniser.
450: rx_data_wbs <= data_rx_synced;
451:
452: end architecture;