File: /__w/ctu-can-regression/ctu-can-regression/src/common_blocks/rst_reg.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Register which is used to drive asynchronous reset of another flip-flop.
71: --
72: -- Output is driven by input reset in scan mode
73: --------------------------------------------------------------------------------
74:
75: Library ieee;
76: use ieee.std_logic_1164.all;
77:
78: Library ctu_can_fd_rtl;
79: use ctu_can_fd_rtl.can_constants_pkg.all;
80:
81: entity rst_reg is
82: generic (
83: G_RESET_POLARITY : std_logic
84: );
85: port (
86: -------------------------------------------------------------------------------------------
87: -- Clock and Reset
88: -------------------------------------------------------------------------------------------
89: clk : in std_logic;
90: arst : in std_logic;
91:
92: -------------------------------------------------------------------------------------------
93: -- Flip flop input / output
94: -------------------------------------------------------------------------------------------
95: d : in std_logic;
96: q : out std_logic;
97:
98: -------------------------------------------------------------------------------------------
99: -- Scan mode control
100: -------------------------------------------------------------------------------------------
101: scan_enable : in std_logic
102: );
103: end rst_reg;
104:
105: architecture rtl of rst_reg is
106:
107: signal q_i : std_logic;
108:
109: begin
110:
111: rx_shift_res_reg_inst : entity ctu_can_fd_rtl.dff_arst
112: generic map (
113: G_RESET_POLARITY => G_RESET_POLARITY,
114:
115: -- Reset to the same value as is polarity of reset so that other DFFs which are reset by
116: -- output of this one will be reset too!
117: G_RST_VAL => G_RESET_POLARITY
118: )
119: port map (
120: arst => arst, -- IN
121: clk => clk, -- IN
122: reg_d => d, -- IN
123:
124: reg_q => q_i -- OUT
125: );
126:
127: mux2_res_tst_inst : entity ctu_can_fd_rtl.mux2
128: port map (
129: a => q_i,
130: b => arst,
131: sel => scan_enable,
132:
133: -- Output
134: z => q
135: );
136:
137: end rtl;