File: /__w/ctu-can-regression/ctu-can-regression/test/main_tb/ctu_can_fd_vip.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- @Purpose:
70: -- CTU CAN FD VIP - Main verification component, encapsulates all test
71: -- functionality.
72: --
73: --------------------------------------------------------------------------------
74: -- Revision History:
75: -- 26.1.2021 Created file
76: --------------------------------------------------------------------------------
77:
78: Library ctu_can_fd_tb;
79: context ctu_can_fd_tb.ieee_context;
80: context ctu_can_fd_tb.tb_common_context;
81: context ctu_can_fd_tb.tb_agents_context;
82: context ctu_can_fd_tb.rtl_context;
83:
84: use ctu_can_fd_tb.tb_shared_vars_pkg.all;
85:
86: entity ctu_can_fd_vip is
87: generic(
88: -- Test details
89: test_name : string;
90: test_type : string;
91: func_cov_en : boolean;
92:
93: -- DUT configuration
94: rx_buffer_size : natural;
95: txt_buffer_count : natural range 2 to 8 := 8;
96:
97: -- DUT Clock period
98: cfg_sys_clk_period : string;
99:
100: -- Finish on report Error
101: finish_on_error : natural;
102:
103: -- Bit timing cofnig used in; compliance tests
104: cfg_brp : natural;
105: cfg_prop : natural;
106: cfg_ph_1 : natural;
107: cfg_ph_2 : natural;
108: cfg_sjw : natural;
109: cfg_brp_fd : natural;
110: cfg_prop_fd : natural;
111: cfg_ph_1_fd : natural;
112: cfg_ph_2_fd : natural;
113: cfg_sjw_fd : natural;
114:
115: -- Secondary sample point config
116: cfg_ssp_src : natural;
117: cfg_ssp_offset : natural;
118:
119: -- Seed
120: seed : natural := 0;
121:
122: -- Reference test iterations
123: reference_iterations : natural range 1 to 1000 := 1000
124: );
125: port(
126: -- Test control
127: test_start : in std_logic;
128: test_done : out std_logic := '0';
129: test_success : out std_logic := '0';
130:
131: -- DUT interface
132: clk_sys : out std_logic;
133: res_n : out std_logic;
134:
135: -- DFT support
136: scan_enable : out std_logic;
137:
138: write_data : out std_logic_vector(31 DOWNTO 0);
139: read_data : in std_logic_vector(31 DOWNTO 0);
140: adress : out std_logic_vector(15 DOWNTO 0);
141: scs : out std_logic;
142: srd : out std_logic;
143: swr : out std_logic;
144: sbe : out std_logic_vector(3 DOWNTO 0);
145:
146: int : in std_logic;
147:
148: can_tx : in std_logic;
149: can_rx : out std_logic;
150:
151: test_probe : in t_ctu_can_fd_test_probe;
152: timestamp : out std_logic_vector(63 DOWNTO 0)
153: );
154: end entity;
155:
156:
157: architecture behav of ctu_can_fd_vip is
158:
159: signal clk_sys_i : std_logic;
160: signal clk_sys_clock_agent : std_logic;
161:
162: -- RX signals on CAN bus, as driven by various agents.
163: -- TX signal is unique (driven by DUT)
164: signal can_rx_compliance_agent : std_logic := '1';
165: signal can_rx_feature_agent : std_logic := '1';
166:
167: ---------------------------------------------------------------------------
168: -- Internal chip selects:
169: -- 0 - DUT - out of VIP
170: -- 1 - Test node of feature tests
171: ---------------------------------------------------------------------------
172: signal scs_i : std_logic_vector(1 downto 0);
173: signal scs_i_reg : std_logic_vector(1 downto 0);
174:
175: signal read_data_test_node : std_logic_vector(31 downto 0);
176: signal read_data_muxed : std_logic_vector(31 downto 0);
177:
178: signal res_n_i : std_logic;
179:
180:
181: -- PLI interface for communication with compliance test library
182: signal pli_clk : std_logic;
183: signal pli_req : std_logic;
184: signal pli_ack : std_logic := '0';
185: signal pli_cmd : std_logic_vector(7 downto 0);
186: signal pli_dest : std_logic_vector(7 downto 0);
187: signal pli_data_in : std_logic_vector(63 downto 0);
188: signal pli_data_in_2 : std_logic_vector(63 downto 0);
189: signal pli_str_buf_in : std_logic_vector(511 downto 0);
190: signal pli_data_out : std_logic_vector(63 downto 0);
191:
192: -- PLI interface for giving test control to compliance test library
193: signal pli_control_req : std_logic := '0';
194: signal pli_control_gnt : std_logic;
195:
196: signal pli_test_name_array : std_logic_vector((test_name'length * 8) - 1 downto 0)
197: := (OTHERS => '0');
198:
199: -- Test probe of Test node in feature tests
200: signal test_node_test_probe : t_ctu_can_fd_test_probe;
201:
202: -- DFT control for test node
203: signal test_node_scan_enable : std_logic;
204:
205: begin
206:
207: ---------------------------------------------------------------------------
208: -- Reset agent - Asserts reset
209: ---------------------------------------------------------------------------
210: reset_agent_inst : reset_agent
211: port map (
212: reset => res_n_i
213: );
214:
215: ---------------------------------------------------------------------------
216: -- Clock agent - Generates clock
217: ---------------------------------------------------------------------------
218: clk_gen_agent_inst : clk_gen_agent
219: port map(
220: clock_out => clk_sys_clock_agent,
221: clock_in => clk_sys_i
222: );
223:
224: ---------------------------------------------------------------------------
225: -- Memory bus agent - Executes memory accesses
226: ---------------------------------------------------------------------------
227: mem_bus_agent_inst : mem_bus_agent
228: generic map(
229: G_ACCESS_FIFO_DEPTH => 32,
230: G_NUM_SLAVES => 2
231: )
232: port map(
233: clk => clk_sys_i,
234: scs => scs_i,
235: swr => swr,
236: srd => srd,
237: sbe => sbe,
238: write_data => write_data,
239: read_data => read_data_muxed,
240: address => adress
241: );
242:
243: ---------------------------------------------------------------------------
244: -- Interrupt agent - Checks interrupt pin
245: ---------------------------------------------------------------------------
246: interrupt_agent_inst : interrupt_agent
247: port map(
248: int => int
249: );
250:
251: ---------------------------------------------------------------------------
252: -- Timestamp agent - generates timestamp for DUT
253: ---------------------------------------------------------------------------
254: timestamp_agent_inst : timestamp_agent
255: port map(
256: clk_sys => clk_sys_i,
257: timestamp => timestamp
258: );
259:
260: ---------------------------------------------------------------------------
261: -- Test probe agent - allows peeking signals brought to test-probe.
262: ---------------------------------------------------------------------------
263: test_probe_agent_inst : test_probe_agent
264: port map(
265: dut_test_probe => test_probe,
266: test_node_test_probe => test_node_test_probe,
267:
268: dut_scan_enable => scan_enable,
269: test_node_scan_enable=> test_node_scan_enable
270: );
271:
272: ---------------------------------------------------------------------------
273: -- Test controller agent - controls simulation
274: ---------------------------------------------------------------------------
275: test_controller_agent_inst : test_controller_agent
276: generic map(
277: test_name => test_name,
278: test_type => test_type,
279: seed => seed,
280:
281: -- DUT configuration
282: cfg_sys_clk_period => cfg_sys_clk_period,
283: cfg_brp => cfg_brp,
284: cfg_prop => cfg_prop,
285: cfg_ph_1 => cfg_ph_1,
286: cfg_ph_2 => cfg_ph_2,
287: cfg_sjw => cfg_sjw,
288: cfg_brp_fd => cfg_brp_fd,
289: cfg_prop_fd => cfg_prop_fd,
290: cfg_ph_1_fd => cfg_ph_1_fd,
291: cfg_ph_2_fd => cfg_ph_2_fd,
292: cfg_sjw_fd => cfg_sjw_fd
293: )
294: port map(
295: -- Test control interface (to VIP top)
296: test_start => test_start,
297: test_done => test_done,
298: test_success => test_success,
299:
300: -- PLI communication interface
301: pli_clk => pli_clk,
302: pli_req => pli_req,
303: pli_ack => pli_ack,
304: pli_cmd => pli_cmd,
305: pli_dest => pli_dest,
306: pli_data_in => pli_data_in,
307: pli_data_in_2 => pli_data_in_2,
308: pli_str_buf_in => pli_str_buf_in,
309: pli_data_out => pli_data_out,
310:
311: -- PLI interface for giving test control to compliance test library
312: pli_control_req => pli_control_req,
313: pli_control_gnt => pli_control_gnt
314: );
315:
316:
317: ---------------------------------------------------------------------------
318: ---------------------------------------------------------------------------
319: -- Test type specific agents
320: ---------------------------------------------------------------------------
321: ---------------------------------------------------------------------------
322:
323: ---------------------------------------------------------------------------
324: -- Compliance tests agent (CAN agent of ISO compliance library).
325: --
326: -- Used by compliance tests and reference tests.
327: ---------------------------------------------------------------------------
328: can_agent_gen : if (test_type = "compliance" or test_type = "reference") generate
329: compliance_agent_inst : can_agent
330: generic map(
331: G_DRIVER_FIFO_DEPTH => 2048,
332: G_MONITOR_FIFO_DEPTH => 2048
333: )
334: port map(
335: can_tx => can_tx,
336: can_rx => can_rx_compliance_agent
337: );
338: end generate;
339:
340: ---------------------------------------------------------------------------
341: -- Feature test agent. Used only by feature tests.
342: ---------------------------------------------------------------------------
343: feature_test_agent_gen : if (test_type = "feature") generate
344: feature_test_agent_inst : feature_test_agent
345: generic map(
346: -- Test details
347: test_name => test_name,
348: test_type => test_type,
349:
350: -- DUT configuration
351: cfg_sys_clk_period => cfg_sys_clk_period,
352:
353: cfg_brp => cfg_brp,
354: cfg_prop => cfg_prop,
355: cfg_ph_1 => cfg_ph_1,
356: cfg_ph_2 => cfg_ph_2,
357: cfg_sjw => cfg_sjw,
358: cfg_brp_fd => cfg_brp_fd,
359: cfg_prop_fd => cfg_prop_fd,
360: cfg_ph_1_fd => cfg_ph_1_fd,
361: cfg_ph_2_fd => cfg_ph_2_fd,
362: cfg_sjw_fd => cfg_sjw_fd,
363: cfg_ssp_src => cfg_ssp_src,
364: cfg_ssp_offset => cfg_ssp_offset
365: )
366: port map (
367: -- Test node connections
368: clk_sys => clk_sys_i,
369: res_n => res_n_i,
370:
371: write_data => write_data,
372: read_data => read_data_test_node,
373: adress => adress,
374: scs => scs_i(1),
375: srd => srd,
376: swr => swr,
377: sbe => sbe,
378:
379: -- CAN bus from/to DUT
380: dut_can_tx => can_tx,
381: dut_can_rx => can_rx_feature_agent,
382:
383: test_node_test_probe => test_node_test_probe,
384: test_node_scan_enable => test_node_scan_enable
385: );
386: end generate;
387:
388: ---------------------------------------------------------------------------
389: -- Reference test agent
390: ---------------------------------------------------------------------------
391: reference_test_agent_inst : reference_test_agent
392: generic map(
393: test_name => test_name,
394: test_type => test_type,
395: reference_iterations => reference_iterations
396: );
397:
398: ---------------------------------------------------------------------------
399: -- Functional coverage agent
400: ---------------------------------------------------------------------------
401: g_func_cov : if (func_cov_en) generate
402:
403: func_cov_agent_inst : func_cov_agent
404: generic map (
405: G_RX_BUFF_SIZE => rx_buffer_size,
406: G_TXT_BUFFER_COUNT => txt_buffer_count
407: )
408: port map (
409: clk => clk_sys_i
410: );
411:
412: end generate;
413:
414: ---------------------------------------------------------------------------
415: ---------------------------------------------------------------------------
416: -- Other common stuff
417: ---------------------------------------------------------------------------
418: ---------------------------------------------------------------------------
419:
420: clk_sys_i <= clk_sys_clock_agent;
421: clk_sys <= clk_sys_clock_agent;
422: res_n <= res_n_i;
423:
424: ---------------------------------------------------------------------------
425: -- CAN bus connection
426: --
427: -- Realize wired-AND by multiple agents. If agents are not active, they
428: -- drive high, therfore they dont affect the bus!
429: ---------------------------------------------------------------------------
430: can_rx <= can_rx_compliance_agent AND can_rx_feature_agent;
431:
432: ---------------------------------------------------------------------------
433: -- DUT Memory bus routing
434: ---------------------------------------------------------------------------
435: scs <= scs_i(0);
436:
437: scs_reg_proc : process(ALL)
438: begin
439: if (rising_edge(clk_sys_i)) then
440: scs_i_reg <= scs_i;
441: end if;
442: end process;
443:
444: read_data_muxed <= read_data when (scs_i_reg(0) = '1') else
445: read_data_test_node when (scs_i_reg(1) = '1') else
446: (OTHERS => '0');
447:
448: ---------------------------------------------------------------------------
449: -- Write test name from generic to PLI interface signal
450: ---------------------------------------------------------------------------
451: test_proc : process
452: begin
453: pli_str_to_logic_vector(test_name, pli_test_name_array);
454: wait;
455: end process;
456:
457: ---------------------------------------------------------------------------
458: -- Test specific deposits
459: ---------------------------------------------------------------------------
460: process
461: begin
462: wait for 5 ns;
463:
464: if (tb_force.something_to_force) then
465:
466: if (tb_force.is_forced_tx_counter) then
467: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST.tx_frame_ctr_i : std_logic_vector(31 downto 0) >> <= force tb_force.get_tx_counter_force_val;
468: end if;
469:
470: if (tb_force.is_forced_rx_counter) then
471: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST.rx_frame_ctr_i : std_logic_vector(31 downto 0) >> <= force tb_force.get_rx_counter_force_val;
472: end if;
473:
474: if (tb_force.is_forced_err_norm) then
475: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.nom_err_ctr_q : unsigned(15 downto 0) >> <= force unsigned(tb_force.get_err_norm_force_val);
476: end if;
477:
478: if (tb_force.is_forced_err_fd) then
479: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.data_err_ctr_q : unsigned(15 downto 0) >> <= force unsigned(tb_force.get_err_fd_force_val);
480: end if;
481:
482: end if;
483:
484: if (tb_force.something_to_release) then
485:
486: if (tb_force.is_released_tx_counter) then
487: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST.tx_frame_ctr_i : std_logic_vector(31 downto 0) >> <= release;
488: end if;
489:
490: if (tb_force.is_released_rx_counter) then
491: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.BUS_TRAFFIC_CTRS_GEN.BUS_TRAFFIC_COUNTERS_INST.rx_frame_ctr_i : std_logic_vector(31 downto 0) >> <= release;
492: end if;
493:
494: if (tb_force.is_released_err_norm) then
495: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.nom_err_ctr_q : unsigned(15 downto 0) >> <= release;
496: end if;
497:
498: if (tb_force.is_released_err_fd) then
499: <<signal .TB_TOP_CTU_CAN_FD.DUT.CAN_CORE_INST.FAULT_CONFINEMENT_INST.ERR_COUNTERS_INST.data_err_ctr_q : unsigned(15 downto 0) >> <= release;
500: end if;
501:
502: end if;
503: end process;
504:
505: ---------------------------------------------------------------------------
506: -- Propagate finish config
507: ---------------------------------------------------------------------------
508: finish_on_error_proc : process
509: begin
510: if (finish_on_error > 0) then
511: finish_on_error_i.set(true);
512: else
513: finish_on_error_i.set(false);
514: end if;
515: wait;
516: end process;
517:
518: ---------------------------------------------------------------------------
519: -- Checks
520: ---------------------------------------------------------------------------
521: assert test_type = "feature" or test_type = "compliance" or test_type = "reference"
522: report "Unsupported test type: " & test_type & ", choose one of: feature, compliance, reference"
523: severity failure;
524:
525: end architecture;