File: /__w/ctu-can-regression/ctu-can-regression/src/frame_filters/frame_filters.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Frame filters for CAN RX frame.
71: --
72: -- Purpose:
73: -- Filters out commands for RX Buffer based on value of received CAN Identifier.
74: -- Filter identifier type, frame type are controlled by Driving Bus.
75: -- 11 bit and 29 bit filters can be compared. If 13 bit filters are compared,
76: -- then MSB 18 bits in Received Identifier has to be zeros. Also mask for the
77: -- filter in case of 16-bit filter HAS to have 16 uppest bits equal to zero!
78: -- Filters A,B,C and Range are present. If input identifier matches at least one
79: -- it is considered as valid. Frame type (CAN Basic, CAN Extended, CAN FD Basic)
80: -- are also selectable for filtering. Filters can be optionally left out from
81: -- synthesis or disabled in runtime. If filters are disabled, no frame is
82: -- filtered out.
83: --------------------------------------------------------------------------------
84:
85: Library ieee;
86: use ieee.std_logic_1164.all;
87: use ieee.numeric_std.ALL;
88:
89: Library ctu_can_fd_rtl;
90: use ctu_can_fd_rtl.can_constants_pkg.all;
91: use ctu_can_fd_rtl.can_types_pkg.all;
92:
93: use ctu_can_fd_rtl.CAN_FD_register_map.all;
94: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
95:
96: entity frame_filters is
97: generic (
98: -- Support filter A
99: G_SUP_FILTA : boolean := true;
100:
101: -- Support filter B
102: G_SUP_FILTB : boolean := true;
103:
104: -- Support filter C
105: G_SUP_FILTC : boolean := true;
106:
107: -- Support range filter
108: G_SUP_RANGE : boolean := true
109: );
110: port (
111: -------------------------------------------------------------------------------------------
112: -- Clock an Asynchronous reset
113: -------------------------------------------------------------------------------------------
114: clk_sys : in std_logic;
115: res_n : in std_logic;
116:
117: -------------------------------------------------------------------------------------------
118: -- Memory registers interface
119: -------------------------------------------------------------------------------------------
120: mr_filter_control_fafe : in std_logic;
121: mr_filter_control_fafb : in std_logic;
122: mr_filter_control_fane : in std_logic;
123: mr_filter_control_fanb : in std_logic;
124:
125: mr_filter_control_fbfe : in std_logic;
126: mr_filter_control_fbfb : in std_logic;
127: mr_filter_control_fbne : in std_logic;
128: mr_filter_control_fbnb : in std_logic;
129:
130: mr_filter_control_fcfe : in std_logic;
131: mr_filter_control_fcfb : in std_logic;
132: mr_filter_control_fcne : in std_logic;
133: mr_filter_control_fcnb : in std_logic;
134:
135: mr_filter_control_frfe : in std_logic;
136: mr_filter_control_frfb : in std_logic;
137: mr_filter_control_frne : in std_logic;
138: mr_filter_control_frnb : in std_logic;
139:
140: mr_filter_a_mask_bit_mask_a_val : in std_logic_vector(28 downto 0);
141: mr_filter_a_val_bit_val_a_val : in std_logic_vector(28 downto 0);
142: mr_filter_b_mask_bit_mask_b_val : in std_logic_vector(28 downto 0);
143: mr_filter_b_val_bit_val_b_val : in std_logic_vector(28 downto 0);
144: mr_filter_c_mask_bit_mask_c_val : in std_logic_vector(28 downto 0);
145: mr_filter_c_val_bit_val_c_val : in std_logic_vector(28 downto 0);
146: mr_filter_ran_high_bit_ran_high_val : in std_logic_vector(28 downto 0);
147: mr_filter_ran_low_bit_ran_low_val : in std_logic_vector(28 downto 0);
148:
149: mr_settings_fdrf : in std_logic;
150: mr_mode_afm : in std_logic;
151:
152: -------------------------------------------------------------------------------------------
153: -- CAN Core interface
154: -------------------------------------------------------------------------------------------
155: -- Receieved CAN ID
156: rec_ident : in std_logic_vector(28 downto 0);
157:
158: -- Received CAN ID type (0-Base Format, 1-Extended Format);
159: rec_ident_type : in std_logic;
160:
161: -- Input frame type (0-CAN 2.0, 1- CAN FD)
162: rec_frame_type : in std_logic;
163:
164: -- RX Remote transmission request Flag
165: rec_is_rtr : in std_logic;
166:
167: -- Identifier valid
168: rec_ivld : in std_logic;
169:
170: -- Store Metadata in RX Buffer
171: store_metadata : in std_logic;
172:
173: -- Command to store word of CAN Data
174: store_data : in std_logic;
175:
176: -- Received frame valid
177: rec_valid : in std_logic;
178:
179: -- Command to abort storing of RX frame (due to Error frame)
180: rec_abort : in std_logic;
181:
182: -------------------------------------------------------------------------------------------
183: -- Frame filters output
184: -------------------------------------------------------------------------------------------
185: -- Store Metadata in RX Buffer - Filtered
186: store_metadata_f : out std_logic;
187:
188: -- Command to store word of CAN Data - Filtered
189: store_data_f : out std_logic;
190:
191: -- Received frame valid - Filtered
192: rec_valid_f : out std_logic;
193:
194: -- Command to abort storing of RX frame (due to Error frame) - Filtered
195: rec_abort_f : out std_logic
196: );
197: end entity;
198:
199: architecture rtl of frame_filters is
200:
201: -- Outputs of individual filters are valid
202: signal int_filter_A_valid : std_logic;
203: signal int_filter_B_valid : std_logic;
204: signal int_filter_C_valid : std_logic;
205: signal int_filter_ran_valid : std_logic;
206:
207: -- Masks for each filter with allowed frame types
208: signal mask_filter_a : std_logic_vector(3 downto 0);
209: signal mask_filter_b : std_logic_vector(3 downto 0);
210: signal mask_filter_c : std_logic_vector(3 downto 0);
211: signal mask_filter_range : std_logic_vector(3 downto 0);
212:
213: -- Frame type on input to be compared with driving signal
214: signal int_data_type : std_logic_vector(3 downto 0);
215:
216: -- Concat of types of data on input
217: signal int_data_ctrl : std_logic_vector(1 downto 0);
218:
219: -- Enable signal for filters
220: signal filter_a_enable : std_logic;
221: signal filter_b_enable : std_logic;
222: signal filter_c_enable : std_logic;
223: signal filter_range_enable : std_logic;
224:
225: signal filter_result : std_logic;
226:
227: -- Valid output value
228: signal ident_valid_d : std_logic;
229: signal ident_valid_q : std_logic;
230:
231: -- Indication that frame should be dropped
232: signal drop_rtr_frame : std_logic;
233:
234: begin
235:
236: -----------------------------------------------------------------------------------------------
237: -- Decoding Filter enables based on accepted frame types by each filter
238: -----------------------------------------------------------------------------------------------
239:
240: -- Input frame type internal signal
241: int_data_ctrl <= rec_frame_type & rec_ident_type;
242:
243: -- Decoder frame_type&ident_type to one-hot
244: with int_data_ctrl select int_data_type <=
245: "0001" when "00", --CAN Basic
246: "0010" when "01", --CAN Extended
247: "0100" when "10", --CAN FD Basic
248: "1000" when others; --CAN Fd Extended
249:
250: -- Filter is enabled when at least one Frame type/Identifier type is matching
251: -- the configured value
252: mask_filter_a <= mr_filter_control_fafe & mr_filter_control_fafb &
253: mr_filter_control_fane & mr_filter_control_fanb;
254:
255: mask_filter_b <= mr_filter_control_fbfe & mr_filter_control_fbfb &
256: mr_filter_control_fbne & mr_filter_control_fbnb;
257:
258: mask_filter_c <= mr_filter_control_fcfe & mr_filter_control_fcfb &
259: mr_filter_control_fcne & mr_filter_control_fcnb;
260:
261: mask_filter_range <= mr_filter_control_frfe & mr_filter_control_frfb &
262: mr_filter_control_frne & mr_filter_control_frnb;
263:
264:
265: filter_a_enable <= '1' when ((mask_filter_a and int_data_type) /= x"0")
266: else
267: '0';
268:
269: filter_b_enable <= '1' when ((mask_filter_b and int_data_type) /= x"0")
270: else
271: '0';
272:
273: filter_c_enable <= '1' when ((mask_filter_c and int_data_type) /= x"0")
274: else
275: '0';
276:
277: filter_range_enable <= '1' when ((mask_filter_range and int_data_type) /= x"0")
278: else
279: '0';
280:
281: -----------------------------------------------------------------------------------------------
282: -- Filter instances
283: -----------------------------------------------------------------------------------------------
284: bit_filter_a_inst : entity ctu_can_fd_rtl.bit_filter
285: generic map (
286: G_WIDTH => 29,
287: G_IS_PRESENT => G_SUP_FILTA
288: )
289: port map (
290: filter_mask => mr_filter_a_mask_bit_mask_a_val, -- IN
291: filter_value => mr_filter_a_val_bit_val_a_val, -- IN
292: filter_input => rec_ident, -- IN
293: enable => filter_a_enable, -- IN
294:
295: valid => int_filter_a_valid -- OUT
296: );
297:
298: bit_filter_b_inst : entity ctu_can_fd_rtl.bit_filter
299: generic map (
300: G_WIDTH => 29,
301: G_IS_PRESENT => G_SUP_FILTB
302: )
303: port map (
304: filter_mask => mr_filter_b_mask_bit_mask_b_val, -- IN
305: filter_value => mr_filter_b_val_bit_val_b_val, -- IN
306: filter_input => rec_ident, -- IN
307: enable => filter_b_enable, -- IN
308:
309: valid => int_filter_b_valid -- OUT
310: );
311:
312: bit_filter_c_inst : entity ctu_can_fd_rtl.bit_filter
313: generic map (
314: G_WIDTH => 29,
315: G_IS_PRESENT => G_SUP_FILTC
316: )
317: port map (
318: filter_mask => mr_filter_c_mask_bit_mask_c_val, -- IN
319: filter_value => mr_filter_c_val_bit_val_c_val, -- IN
320: filter_input => rec_ident, -- IN
321: enable => filter_c_enable, -- IN
322:
323: valid => int_filter_c_valid -- OUT
324: );
325:
326: range_filter_inst : entity ctu_can_fd_rtl.range_filter
327: generic map (
328: G_WIDTH => 29,
329: G_IS_PRESENT => G_SUP_RANGE
330: )
331: port map (
332: filter_upp_th => mr_filter_ran_high_bit_ran_high_val, -- IN
333: filter_low_th => mr_filter_ran_low_bit_ran_low_val, -- IN
334: filter_input => rec_ident, -- IN
335: enable => filter_range_enable, -- IN
336:
337: valid => int_filter_ran_valid -- OUT
338: );
339:
340:
341: -----------------------------------------------------------------------------------------------
342: -- If no filter is supported then Identifier is always valid, regardless of SETTINGS[ENA] ! If
343: -- Core is not synthesized, turning filters on should not affect the acceptance! Everyhting
344: -- should be affected!
345: -----------------------------------------------------------------------------------------------
346: filt_sup_gen_false : if (G_SUP_FILTA = false and G_SUP_FILTB = false and
347: G_SUP_FILTC = false and G_SUP_RANGE = false) generate
348: ident_valid_d <= '1';
349: filter_result <= '0';
350: drop_rtr_frame <= '0';
351: end generate;
352:
353:
354: filt_sup_gen_true : if (G_SUP_FILTA = true or G_SUP_FILTB = true or
355: G_SUP_FILTC = true or G_SUP_RANGE = true) generate
356:
357: drop_rtr_frame <= '1' when (mr_settings_fdrf = DROP_RF_ENABLED
358: and rec_is_rtr = RTR_FRAME)
359: else
360: '0';
361:
362: filter_result <= '1' when (rec_ivld = '0') else
363: '0' when (drop_rtr_frame = '1') else
364: '1' when (int_filter_a_valid = '1' or
365: int_filter_b_valid = '1' or
366: int_filter_c_valid = '1' or
367: int_filter_ran_valid = '1')
368: else
369: '0';
370:
371: ident_valid_d <= filter_result when (mr_mode_afm = '1')
372: else
373: '1';
374: end generate;
375:
376:
377: -----------------------------------------------------------------------------------------------
378: -- To avoid long combinational paths, valid filter output is pipelined. This is OK since
379: -- received frame is valid on input for many clock cycles!
380: -----------------------------------------------------------------------------------------------
381: valid_reg_proc : process(res_n, clk_sys)
382: begin
383: if (res_n = '0') then
384: ident_valid_q <= '0';
385: elsif rising_edge(clk_sys) then
386: ident_valid_q <= ident_valid_d;
387: end if;
388: end process valid_reg_proc;
389:
390: -----------------------------------------------------------------------------------------------
391: -- Filtering RX Buffer commands
392: -----------------------------------------------------------------------------------------------
393: store_metadata_f <= '1' when (store_metadata = '1' and ident_valid_q = '1')
394: else
395: '0';
396:
397: store_data_f <= '1' when (store_data = '1' and ident_valid_q = '1')
398: else
399: '0';
400:
401: rec_valid_f <= '1' when (rec_valid = '1' and ident_valid_q = '1')
402: else
403: '0';
404:
405: rec_abort_f <= '1' when (rec_abort = '1' and ident_valid_q = '1')
406: else
407: '0';
408:
409: end architecture;