File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/protocol_control_fsm.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- Protocol control FSM.
71: --
72: -- Purpose:
73: -- State machine handling CAN FD protocol according to CAN FD 1.0 and ISO CAN
74: -- FD (ISO 11898-1 2015) standard.
75: -- Processes RX Data in "Process" pipeline stage with "rx_trigger". This
76: -- corresponds to moment one clock cycle behind sample point. In the same clock
77: -- cycle loads TX Shift register. FSM communicates with following modules:
78: -- 1. TXT Buffers (HW Commands)
79: -- 2. TX Arbitrator (HW Commands)
80: -- 3. RX Buffer (Storing protocol)
81: -- 4. TX Shift Register (Load)
82: -- 5. RX Shift Register (Store commands)
83: -- 6. Error detector (Error enabling, CRC check command)
84: -- 7. Prescaler (Sample control, Synchronisation control)
85: -- 8. Bus sampling (Transceiver Delay measurement)
86: -- 9. Bit Stuffing (Stuffing method, Length of Stuff rule, Data halt)
87: -- 10. Bit De-Stuffing (Stuffing method, Length of Stuff rule, Destuffed bit)
88: -- 11. CAN CRC (Enable, speculative enable, Calculated CRC sequence)
89: -- 12. Control, Retransmitt, Re-integration counters.
90: -- 13. Fault confinement (Fault confinement protocol as in ISO 11898-1 2015.
91: -- 14. Operation control (Setting transmitter/receiver idle).
92: --------------------------------------------------------------------------------
93:
94: Library ieee;
95: use ieee.std_logic_1164.all;
96: use ieee.numeric_std.ALL;
97:
98: Library ctu_can_fd_rtl;
99: use ctu_can_fd_rtl.can_constants_pkg.all;
100: use ctu_can_fd_rtl.can_types_pkg.all;
101:
102: use ctu_can_fd_rtl.CAN_FD_register_map.all;
103: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
104:
105: entity protocol_control_fsm is
106: port (
107: -------------------------------------------------------------------------------------------
108: -- Clock and Asynchronous Reset
109: -------------------------------------------------------------------------------------------
110: clk_sys : in std_logic;
111: res_n : in std_logic;
112:
113: -------------------------------------------------------------------------------------------
114: -- Signals which cause state change
115: -------------------------------------------------------------------------------------------
116: -- RX Trigger
117: rx_trigger : in std_logic;
118:
119: -- Error frame request
120: err_frm_req : in std_logic;
121:
122: -------------------------------------------------------------------------------------------
123: -- Memory registers interface
124: -------------------------------------------------------------------------------------------
125: -- Configuration values
126: mr_mode_acf : in std_logic;
127: mr_mode_stm : in std_logic;
128: mr_mode_bmm : in std_logic;
129: mr_mode_fde : in std_logic;
130: mr_mode_rom : in std_logic;
131: mr_mode_sam : in std_logic;
132:
133: mr_settings_ena : in std_logic;
134: mr_settings_nisofd : in std_logic;
135: mr_settings_rtrle : in std_logic;
136: mr_settings_ilbp : in std_logic;
137: mr_settings_pex : in std_logic;
138:
139: mr_command_cpexs : in std_logic;
140: mr_command_ercrst : in std_logic;
141:
142: mr_ssp_cfg_ssp_src : in std_logic_vector(1 downto 0);
143:
144: -- Status values
145: mr_status_pexs : out std_logic;
146: pc_dbg : out t_protocol_control_dbg;
147:
148: -------------------------------------------------------------------------------------------
149: -- Data-path interface
150: -------------------------------------------------------------------------------------------
151: -- Actual TX Data (post bit stuffing)
152: tx_data_wbs : in std_logic;
153:
154: -- Actual RX Data
155: rx_data_nbs : in std_logic;
156:
157: -------------------------------------------------------------------------------------------
158: -- RX Buffer interface
159: -------------------------------------------------------------------------------------------
160: -- Command to store CAN frame metadata to RX Buffer
161: store_metadata : out std_logic;
162:
163: -- Command to store word of CAN Data
164: store_data : out std_logic;
165:
166: -- Received frame valid
167: rec_valid : out std_logic;
168:
169: -- Command to abort storing of RX frame (due to Error frame)
170: rec_abort : out std_logic;
171:
172: -- Start of Frame pulse
173: sof_pulse : out std_logic;
174:
175: -------------------------------------------------------------------------------------------
176: -- TXT Buffer, TX Arbitrator interface
177: -------------------------------------------------------------------------------------------
178: -- There is a valid frame for transmission
179: tran_frame_valid : in std_logic;
180:
181: -- HW Commands to TXT Buffers
182: txtb_hw_cmd : out t_txtb_hw_cmd;
183:
184: -- Pointer to TXT Buffer memory
185: txtb_ptr : out natural range 0 to 20;
186:
187: -- Clock enable for TXT Buffer memory
188: txtb_clk_en : out std_logic;
189:
190: -- TX Data length code
191: tran_dlc : in std_logic_vector(3 downto 0);
192:
193: -- TX Remote transmission request flag
194: tran_is_rtr : in std_logic;
195:
196: -- TX Frame type (0-CAN 2.0, 1-CAN FD)
197: tran_frame_type : in std_logic;
198:
199: -- Identifier type (BASIC, EXTENDED)
200: tran_ident_type : in std_logic;
201:
202: -- TX Bit rate shift
203: tran_brs : in std_logic;
204:
205: -------------------------------------------------------------------------------------------
206: -- TX Shift register interface
207: -------------------------------------------------------------------------------------------
208: -- Load Base Identifier to TX Shift register
209: tx_load_base_id : out std_logic;
210:
211: -- Load extended Identifier to TX Shift register
212: tx_load_ext_id : out std_logic;
213:
214: -- Load DLC
215: tx_load_dlc : out std_logic;
216:
217: -- Load Data word to TX Shift register
218: tx_load_data_word : out std_logic;
219:
220: -- Load Stuff count
221: tx_load_stuff_count : out std_logic;
222:
223: -- Load CRC to TX Shift register
224: tx_load_crc : out std_logic;
225:
226: -- Shift register enable (shifts with TX Trigger)
227: tx_shift_ena : out std_logic;
228:
229: -- Force Dominant value instead of value from shift register
230: tx_dominant : out std_logic;
231:
232: -------------------------------------------------------------------------------------------
233: -- RX Shift register interface
234: -------------------------------------------------------------------------------------------
235: -- Clear all registers in RX Shift register
236: rx_clear : out std_logic;
237:
238: -- Store Base Identifier
239: rx_store_base_id : out std_logic;
240:
241: -- Store Extended Identifier
242: rx_store_ext_id : out std_logic;
243:
244: -- Store Identifier extension
245: rx_store_ide : out std_logic;
246:
247: -- Store Remote transmission request
248: rx_store_rtr : out std_logic;
249:
250: -- Store EDL (FDF) bit
251: rx_store_edl : out std_logic;
252:
253: -- Store DLC
254: rx_store_dlc : out std_logic;
255:
256: -- Store ESI
257: rx_store_esi : out std_logic;
258:
259: -- Store BRS
260: rx_store_brs : out std_logic;
261:
262: -- Store stuff count and Stuff Count parity
263: rx_store_stuff_count : out std_logic;
264:
265: -- Clock Enable RX Shift register for each byte.
266: rx_shift_ena : out std_logic_vector(3 downto 0);
267:
268: -- Selector for inputs of each byte of shift register
269: -- (0-Previous byte output, 1- RX Data input)
270: rx_shift_in_sel : out std_logic;
271:
272: -- RX value of Remote transmission request
273: rec_is_rtr : in std_logic;
274:
275: -- RX value of DLC (combinational), valid only in last bit of DLC
276: rec_dlc_d : in std_logic_vector(3 downto 0);
277:
278: -- RX value of DLC (captured)
279: rec_dlc_q : in std_logic_vector(3 downto 0);
280:
281: -- RX frame type (0-CAN 2.0, 1- CAN FD)
282: rec_frame_type : in std_logic;
283:
284: -- RX Frame Loopback
285: rec_lbpf : out std_logic;
286:
287: -- RX Identifier is valid
288: rec_ivld : out std_logic;
289:
290: -------------------------------------------------------------------------------------------
291: -- Control counter interface
292: -------------------------------------------------------------------------------------------
293: -- Preload control counter
294: ctrl_ctr_pload : out std_logic;
295:
296: -- Control counter preload value
297: ctrl_ctr_pload_val : out std_logic_vector(8 downto 0);
298:
299: -- Control counter is enabled
300: ctrl_ctr_ena : out std_logic;
301:
302: -- Control counter is zero
303: ctrl_ctr_zero : in std_logic;
304:
305: -- Control counter is equal to 1
306: ctrl_ctr_one : in std_logic;
307:
308: -- Control counter counted multiple of 8 bits
309: ctrl_counted_byte : in std_logic;
310:
311: -- Control counter byte index within a memory word
312: ctrl_counted_byte_index : in std_logic_vector(1 downto 0);
313:
314: -- Control counter - TXT Buffer memory index
315: ctrl_ctr_mem_index : in std_logic_vector(4 downto 0);
316:
317: -- Complementary counter enable
318: compl_ctr_ena : out std_logic;
319:
320: -- Arbitration lost capture ID field
321: arbitration_part : out std_logic_vector(2 downto 0);
322:
323: -------------------------------------------------------------------------------------------
324: -- Reintegration counter interface
325: -------------------------------------------------------------------------------------------
326: -- Reintegration counter Clear (synchronous)
327: reinteg_ctr_clr : out std_logic;
328:
329: -- Enable counting (with RX Trigger)
330: reinteg_ctr_enable : out std_logic;
331:
332: -- Reintegration counter expired (reached 128)
333: reinteg_ctr_expired : in std_logic;
334:
335: -------------------------------------------------------------------------------------------
336: -- Retransmitt counter interface
337: -------------------------------------------------------------------------------------------
338: -- Clear Retransmitt counter
339: retr_ctr_clear : out std_logic;
340:
341: -- Increment Retransmitt counter by 1
342: retr_ctr_add : out std_logic;
343:
344: -- Retransmitt limit was reached
345: retr_limit_reached : in std_logic;
346:
347: -------------------------------------------------------------------------------------------
348: -- Error detector interface
349: -------------------------------------------------------------------------------------------
350: -- Form Error has occurred
351: form_err : out std_logic;
352:
353: -- ACK Error has occurred
354: ack_err : out std_logic;
355:
356: -- Perform CRC check
357: crc_check : out std_logic;
358:
359: -- Bit Error in arbitration field
360: bit_err_arb : out std_logic;
361:
362: -- Calculated CRC and Stuff count are matching received ones
363: crc_match : in std_logic;
364:
365: -- CRC error signalling
366: crc_err : out std_logic;
367:
368: -- Clear CRC Match flag
369: crc_clear_match_flag : out std_logic;
370:
371: -- CRC Source (CRC15, CRC17, CRC21)
372: crc_src : out std_logic_vector(1 downto 0);
373:
374: -- Error position field (for Error capture)
375: err_pos : out std_logic_vector(3 downto 0);
376:
377: -------------------------------------------------------------------------------------------
378: -- Bit Stuffing/Destuffing control signals
379: -------------------------------------------------------------------------------------------
380: -- Bit Stuffing is enabled
381: stuff_enable : out std_logic;
382:
383: -- Bit De-stuffing is enabled
384: destuff_enable : out std_logic;
385:
386: -- Fixed Bit stuffing method
387: fixed_stuff : out std_logic;
388:
389: -- Frame transmission without SOF started
390: tx_frame_no_sof : out std_logic;
391:
392: -------------------------------------------------------------------------------------------
393: -- Operation control interface
394: -------------------------------------------------------------------------------------------
395: -- Unit is transmitter
396: is_transmitter : in std_logic;
397:
398: -- Unit is receiver
399: is_receiver : in std_logic;
400:
401: -- Loss of arbitration -> Turn receiver!
402: arbitration_lost : out std_logic;
403:
404: -- Set unit to be transmitter (in SOF)
405: set_transmitter : out std_logic;
406:
407: -- Set unit to be receiver
408: set_receiver : out std_logic;
409:
410: -- Set unit to be idle
411: set_idle : out std_logic;
412:
413: -------------------------------------------------------------------------------------------
414: -- Fault confinement interface
415: -------------------------------------------------------------------------------------------
416: -- Primary Error
417: primary_err : out std_logic;
418:
419: -- Active Error or Overload flag is being tranmsmitted
420: act_err_ovr_flag : out std_logic;
421:
422: -- Set unit to be error active
423: set_err_active : out std_logic;
424:
425: -- Error delimiter too late
426: err_delim_late : out std_logic;
427:
428: -- Unit is error active
429: is_err_active : in std_logic;
430:
431: -- Unit is error passive
432: is_err_passive : in std_logic;
433:
434: -- Unit is Bus off
435: is_bus_off : in std_logic;
436:
437: -- Decrement REC (by 1)
438: decrement_rec : out std_logic;
439:
440: -- Bit Error in passive error flag after ACK Error
441: bit_err_after_ack_err : out std_logic;
442:
443: -------------------------------------------------------------------------------------------
444: -- Other control signals
445: -------------------------------------------------------------------------------------------
446: -- Sample control (Nominal, Data, Secondary)
447: sp_control : out std_logic_vector(1 downto 0);
448:
449: -- Sample control (Registered)
450: sp_control_q : out std_logic_vector(1 downto 0);
451:
452: -- Enable Nominal Bit time counters.
453: nbt_ctrs_en : out std_logic;
454:
455: -- Enable Data Bit time counters.
456: dbt_ctrs_en : out std_logic;
457:
458: -- Synchronisation control (No synchronisation, Hard Synchronisation, Resynchronisation)
459: sync_control : out std_logic_vector(1 downto 0);
460:
461: -- Clear the Shift register for secondary sampling point.
462: ssp_reset : out std_logic;
463:
464: -- Enable measurement of Transmitter delay
465: tran_delay_meas : out std_logic;
466:
467: -- Transmitted frame is valid
468: tran_valid : out std_logic;
469:
470: -- CRC calculation enabled
471: crc_enable : out std_logic;
472:
473: -- CRC calculation - speculative enable
474: crc_spec_enable : out std_logic;
475:
476: -- Use RX Data for CRC calculation
477: crc_calc_from_rx : out std_logic;
478:
479: -- Load CRC Initialization vector
480: load_init_vect : out std_logic;
481:
482: -- Bit error enable
483: bit_err_enable : out std_logic;
484:
485: -- Bit rate shifted
486: br_shifted : out std_logic;
487:
488: -- Reset Bit time measurement counter
489: btmc_reset : out std_logic;
490:
491: -- Start Measurement of data bit time (in TX Trigger)
492: dbt_measure_start : out std_logic;
493:
494: -- First SSP generated (in ESI bit)
495: gen_first_ssp : out std_logic;
496:
497: -- Synchronization edge
498: sync_edge : in std_logic
499: );
500: end entity;
501:
502: architecture rtl of protocol_control_fsm is
503:
504: -----------------------------------------------------------------------------------------------
505: -- FSM related signals
506: -----------------------------------------------------------------------------------------------
507: -- Protocol control FSM
508: signal curr_state : t_protocol_control_state;
509: signal next_state : t_protocol_control_state;
510:
511: -- Clock enable for state register
512: signal state_reg_ce : std_logic;
513:
514: -----------------------------------------------------------------------------------------------
515: -- Other Internal signals
516: -----------------------------------------------------------------------------------------------
517: -- No data field should be transmitted
518: signal no_data_transmitter : std_logic;
519: signal no_data_receiver : std_logic;
520: signal no_data_field : std_logic;
521:
522: -- Preload control counter internal signal
523: signal ctrl_ctr_pload_i : std_logic;
524:
525: -- Used when control counter should be preloaded elsewhere than in sample point. This is used
526: -- during integration to reset control counter upon synchronisation edge!
527: signal ctrl_ctr_pload_unaliged : std_logic;
528:
529: -- CRC Selection
530: signal crc_use_21 : std_logic;
531: signal crc_use_17 : std_logic;
532: signal crc_src_i : std_logic_vector(1 downto 0);
533: signal crc_length_i : std_logic_vector(8 downto 0);
534:
535: -- Length of data field (decoded from DLC, does not take RTR into account)
536: signal tran_data_length : std_logic_vector(6 downto 0);
537: signal tran_data_length_i : natural range 0 to 64;
538: signal rec_data_length : std_logic_vector(6 downto 0);
539: signal rec_data_length_c : std_logic_vector(6 downto 0);
540:
541: signal data_length_c : std_logic_vector(6 downto 0);
542: signal data_length_shifted_c : std_logic_vector(9 downto 0);
543: signal data_length_sub_c : unsigned(9 downto 0);
544: signal data_length_bits_c : std_logic_vector(8 downto 0);
545:
546: -- FD Frame is being transmitted/received
547: signal is_fd_frame : std_logic;
548:
549: -- Frame transmission/reception can be started from idle or intermission!
550: signal frame_start : std_logic;
551:
552: -- IDE bit is part of arbitration
553: signal ide_is_arbitration : std_logic;
554:
555: -- Arbitration lost condition
556: signal arbitration_lost_condition : std_logic;
557:
558: -- Loss of arbitration -> Turn receiver!
559: signal arbitration_lost_i : std_logic;
560:
561: -- Transmission failed (due to reached number of retransmissions), or
562: -- first error, arb lost when there are 0 retransmissions allowed!
563: signal tx_failed : std_logic;
564:
565: -- Internal commands for RX Buffer
566: signal store_metadata_d : std_logic;
567: signal store_data_d : std_logic;
568: signal rec_valid_d : std_logic;
569:
570: -- Internal commands for TXT Buffers
571: signal txtb_hw_cmd_d : t_txtb_hw_cmd;
572: signal txtb_hw_cmd_q : t_txtb_hw_cmd;
573:
574: -- Unit should go to suspend transmission field!
575: signal go_to_suspend : std_logic;
576:
577: -- Unit should go to stuff count field
578: signal go_to_stuff_count : std_logic;
579:
580: -- Internal store commands for RX Shift register
581: signal rx_store_base_id_i : std_logic;
582: signal rx_store_ext_id_i : std_logic;
583: signal rx_store_ide_i : std_logic;
584: signal rx_store_rtr_i : std_logic;
585: signal rx_store_edl_i : std_logic;
586: signal rx_store_dlc_i : std_logic;
587: signal rx_store_esi_i : std_logic;
588: signal rx_store_brs_i : std_logic;
589: signal rx_store_stuff_count_i : std_logic;
590:
591: signal rx_clear_i : std_logic;
592:
593: -- Internal commands for TX Shift register
594: signal tx_load_base_id_i : std_logic;
595: signal tx_load_ext_id_i : std_logic;
596: signal tx_load_dlc_i : std_logic;
597: signal tx_load_data_word_i : std_logic;
598: signal tx_load_stuff_count_i : std_logic;
599: signal tx_load_crc_i : std_logic;
600:
601: signal tx_shift_ena_i : std_logic;
602:
603: -- Internal signals for detected errors
604: signal form_err_i : std_logic;
605: signal ack_err_i : std_logic;
606: signal ack_err_flag : std_logic;
607: signal ack_err_flag_clr : std_logic;
608: signal crc_err_i : std_logic;
609: signal bit_err_arb_i : std_logic;
610:
611: -- Sample control (Bit Rate) signals
612: signal sp_control_switch_data : std_logic;
613: signal sp_control_switch_nominal : std_logic;
614:
615: -- Secondary sampling point is used
616: signal switch_to_ssp : std_logic;
617:
618: signal sp_control_ce : std_logic;
619: signal sp_control_d : std_logic_vector(1 downto 0);
620: signal sp_control_q_i : std_logic_vector(1 downto 0);
621:
622: -- Synchronisation control
623: signal sync_control_d : std_logic_vector(1 downto 0);
624: signal sync_control_q : std_logic_vector(1 downto 0);
625:
626: -- Hard synchronisation should be performed
627: signal perform_hsync : std_logic;
628:
629: -- Fault confinemnt interface
630: signal primary_err_i : std_logic;
631: signal err_delim_late_i : std_logic;
632: signal set_err_active_i : std_logic;
633:
634: -- Operation state handling internal
635: signal set_transmitter_i : std_logic;
636: signal set_receiver_i : std_logic;
637: signal set_idle_i : std_logic;
638:
639: -- Flag which holds whether FSM is in first bit of error delimiter
640: signal first_err_delim_d : std_logic;
641: signal first_err_delim_q : std_logic;
642:
643: -- Bit stuffing
644: signal stuff_enable_set : std_logic;
645: signal stuff_enable_clear : std_logic;
646:
647: -- Bit stuffing disable
648: signal destuff_enable_set : std_logic;
649: signal destuff_enable_clear : std_logic;
650:
651: -- Bit error disable (internal)
652: -- Note: Bit Error is rather disabled than enabled, since it is disabled on less
653: -- places than enabled!
654: signal bit_err_disable : std_logic;
655:
656: -- Bit Error is disabled for receiver in most of the frame!
657: signal bit_err_disable_receiver : std_logic;
658:
659: -- TXT Buffer pointer
660: signal txtb_ptr_d : natural range 0 to 20;
661: signal txtb_ptr_q : natural range 0 to 20;
662:
663: -- Start of frame pulse
664: signal sof_pulse_i : std_logic;
665:
666: -- Complementary counter enable
667: signal compl_ctr_ena_i : std_logic;
668:
669: -- Logic for clocking FSM state register
670: signal tick_state_reg : std_logic;
671:
672: -- Bit-rate shifted (internal value)
673: signal br_shifted_i : std_logic;
674:
675: -- Arbitration field is being transmitted / received
676: signal is_arbitration_i : std_logic;
677:
678: -- CRC calculation - speculative enable
679: signal crc_spec_enable_i : std_logic;
680:
681: -- CRC Load initialization vector - internal value
682: signal load_init_vect_i : std_logic;
683:
684: -- Capture register to synchronize Bus off reset request till next Sample point
685: signal mr_command_ercrst_q : std_logic;
686:
687: -- Retransmitt counter clear (internal value)
688: signal retr_ctr_clear_i : std_logic;
689:
690: -- Increment Retransmitt counter by 1
691: signal retr_ctr_add_i : std_logic;
692:
693: -- Decrement Receive error counter (internal value)
694: signal decrement_rec_i : std_logic;
695:
696: -- Blocking register for retransmitt counter add signal.
697: signal retr_ctr_add_block : std_logic;
698: signal retr_ctr_add_block_clr : std_logic;
699:
700: -- Blocking HW command for Unlock.
701: signal block_txtb_unlock : std_logic;
702:
703: -- No SOF transmitted
704: signal tx_frame_no_sof_d : std_logic;
705: signal tx_frame_no_sof_q : std_logic;
706:
707: -- Control signal should be updated!
708: signal ctrl_signal_upd : std_logic;
709:
710: -- Clear bus-off reset flag
711: signal clr_bus_off_rst_flg : std_logic;
712:
713: -- Protocol exception signals
714: signal pex_on_fdf_enable : std_logic;
715: signal pex_on_res_enable : std_logic;
716:
717: -- Synchronization Edge on CAN RX that can be used during
718: -- Integration or reintegration to reset integration counter.
719: signal integ_restart_edge : std_logic;
720:
721: -- Counting of consecutive bits during passive error flag
722: signal rx_data_nbs_prev : std_logic;
723:
724: -- Protocol exception status
725: signal pexs_set : std_logic;
726:
727: -- Internal TX frame type
728: signal tran_frame_type_i : std_logic;
729:
730: -- Clock enable for TXT Buffer RAM
731: signal txtb_clk_en_d : std_logic;
732: signal txtb_clk_en_q : std_logic;
733:
734: -- When reading from TXT Buffer RAM, we can't read beyond the last word in
735: -- the TXT Buffer memory since this might cause spurious false-positive parity errors
736: signal txtb_num_words_gate : natural range 0 to 19;
737: signal txtb_gate_mem_read : std_logic;
738:
739: -- RX Frame loopback
740: signal rec_lbpf_d : std_logic;
741: signal rec_lbpf_q : std_logic;
742:
743: -- RX Frame identifier valid
744: signal rec_ivld_i : std_logic;
745: signal rec_ivld_d : std_logic;
746: signal rec_ivld_q : std_logic;
747:
748: -- Transmit dominant ACK bit
749: signal tx_dominant_ack : std_logic;
750:
751: -- Allow ACK bit to have other value being received as being transmitted
752: signal allow_flipped_ack : std_logic;
753:
754: begin
755:
756: tran_frame_type_i <= FD_CAN when (tran_frame_type = FD_CAN and mr_mode_fde = '1')
757: else
758: NORMAL_CAN;
759:
760: no_data_transmitter <= '1' when (tran_dlc = "0000" or
761: (tran_is_rtr = RTR_FRAME and tran_frame_type_i = NORMAL_CAN))
762: else
763: '0';
764:
765: no_data_receiver <= '1' when (rec_is_rtr = RTR_FRAME or rec_dlc_d = "0000")
766: else
767: '0';
768:
769: no_data_field <= '1' when (is_transmitter = '1' and no_data_transmitter = '1')
770: else
771: '1' when (is_receiver = '1' and no_data_receiver = '1')
772: else
773: '0';
774:
775: go_to_suspend <= '1' when (is_err_passive = '1' and is_transmitter = '1')
776: else
777: '0';
778:
779: ide_is_arbitration <= '1' when (tran_ident_type = EXTENDED or is_receiver = '1')
780: else
781: '0';
782:
783: arbitration_lost_condition <= '1' when (is_transmitter = '1' and tx_data_wbs = RECESSIVE and
784: rx_data_nbs = DOMINANT and rx_trigger = '1')
785: else
786: '0';
787:
788: tx_failed <= '1' when (mr_settings_rtrle = '1' and retr_limit_reached = '1')
789: else
790: '0';
791:
792: is_fd_frame <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN)
793: else
794: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN)
795: else
796: '0';
797:
798: go_to_stuff_count <= '1' when (mr_settings_nisofd = ISO_FD and is_fd_frame = '1')
799: else
800: '0';
801:
802: frame_start <= '1' when (tran_frame_valid = '1' and go_to_suspend = '0') else
803: '1' when (rx_data_nbs = DOMINANT) else
804: '0';
805:
806: tx_dominant_ack <= '1' when (crc_match = '1') and
807: ((is_receiver = '1' and mr_mode_acf = '0') or
808: (is_transmitter = '1' and mr_mode_sam = '1'))
809: else
810: '0';
811:
812: -- ACK may receive different value that transmitted when:
813: -- 1. Unit sends recessive (may receive dominant ACK from other nodes)
814: -- 2. In bus monitoring. The value does not propagate to the bus, but ACK
815: -- from another node may arrive.
816: allow_flipped_ack <= '1' when (tx_dominant_ack = '0' or mr_mode_bmm = '1')
817: else
818: '0';
819:
820: -----------------------------------------------------------------------------------------------
821: -- Signal is not decoded inside curr_state process, because it is sensitive to this signal!
822: -- Done here to avoid loops!
823: -----------------------------------------------------------------------------------------------
824: block_txtb_unlock <= '1' when (curr_state = s_pc_act_err_flag or
825: curr_state = s_pc_pas_err_flag or
826: curr_state = s_pc_err_delim_wait or
827: curr_state = s_pc_err_delim or
828: curr_state = s_pc_ovr_flag or
829: curr_state = s_pc_ovr_delim_wait or
830: curr_state = s_pc_ovr_delim)
831: else
832: '0';
833:
834: pex_on_fdf_enable <= '1' when (mr_mode_fde = FDE_DISABLE and
835: mr_settings_pex = PROTOCOL_EXCEPTION_ENABLED)
836: else
837: '0';
838:
839: pex_on_res_enable <= '1' when (mr_mode_fde = FDE_ENABLE and
840: mr_settings_pex = PROTOCOL_EXCEPTION_ENABLED)
841: else
842: '0';
843:
844: -- Do not accept unaligned edges to cause reset of integration counter
845: -- when configured as CAN 2.0 node (Classical CAN).
846: -- This reflects chapter 10.9.4 of ISO11898-1 2015
847: integ_restart_edge <= '0' when (mr_mode_fde = FDE_DISABLE and
848: mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED)
849: else
850: '1' when (sync_edge = '1')
851: else
852: '0';
853:
854: -----------------------------------------------------------------------------------------------
855: -- Decode maximal address in TXT Buffer on which valid data word is located.
856: -----------------------------------------------------------------------------------------------
857: tran_data_length_i <= to_integer(unsigned(tran_data_length));
858:
859: with tran_data_length_i select txtb_num_words_gate <=
860: 4 when 1 | 2 | 3 | 4,
861: 5 when 5 | 6 | 7 | 8,
862: 6 when 12,
863: 7 when 16,
864: 8 when 20,
865: 9 when 24,
866: 11 when 32,
867: 15 when 48,
868: 19 when 64,
869: 0 when others;
870:
871: txtb_gate_mem_read <= '1' when (txtb_ptr_d > txtb_num_words_gate)
872: else
873: '0';
874:
875: -----------------------------------------------------------------------------------------------
876: -- CRC sequence selection
877: -----------------------------------------------------------------------------------------------
878: crc_use_21 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
879: to_integer(unsigned(tran_data_length)) > 16)
880: else
881: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN and
882: to_integer(unsigned(rec_data_length)) > 16)
883: else
884: '0';
885:
886: crc_use_17 <= '1' when (is_transmitter = '1' and tran_frame_type_i = FD_CAN and
887: crc_use_21 = '0')
888: else
889: '1' when (is_receiver = '1' and rec_frame_type = FD_CAN and
890: crc_use_21 = '0')
891: else
892: '0';
893:
894: crc_src_i <= C_CRC21_SRC when (crc_use_21 = '1') else
895: C_CRC17_SRC when (crc_use_17 = '1') else
896: C_CRC15_SRC;
897:
898: crc_length_i <= C_CRC15_DURATION when (crc_src_i = C_CRC15_SRC) else
899: C_CRC17_DURATION when (crc_src_i = C_CRC17_SRC) else
900: C_CRC21_DURATION;
901:
902: -----------------------------------------------------------------------------------------------
903: -- DLC to Data length decoders
904: -----------------------------------------------------------------------------------------------
905: dlc_decoder_tx_inst : entity ctu_can_fd_rtl.dlc_decoder
906: port map (
907: dlc => tran_dlc, -- IN
908: frame_type => tran_frame_type_i, -- IN
909:
910: data_length => tran_data_length -- OUT
911: );
912:
913: dlc_decoder_rx_inst : entity ctu_can_fd_rtl.dlc_decoder
914: port map (
915: dlc => rec_dlc_q, -- IN
916: frame_type => rec_frame_type, -- IN
917:
918: data_length => rec_data_length -- OUT
919: );
920:
921: dlc_decoder_rx_inst_comb : entity ctu_can_fd_rtl.dlc_decoder
922: port map (
923: dlc => rec_dlc_d, -- IN
924: frame_type => rec_frame_type, -- IN
925:
926: data_length => rec_data_length_c -- OUT
927: );
928:
929: -- Data field length (valid only in Sample point of last bit of DLC)
930: data_length_c <= tran_data_length when (is_transmitter = '1') else
931: rec_data_length_c;
932:
933: -- Shift by 3 (Multiply by 8)
934: data_length_shifted_c <= data_length_c & "000";
935:
936: -- Subtract 1 (control counter counts till field length minus 1)
937: data_length_sub_c <= unsigned(data_length_shifted_c) - 1;
938:
939: -- Convert to length of control counter
940: data_length_bits_c <= std_logic_vector(
941: data_length_sub_c(ctrl_ctr_pload_val'length - 1 downto 0));
942:
943: -----------------------------------------------------------------------------------------------
944: -- Bus off reset request capture register. Capture when there is write to memory registers,
945: -- clear when request is processed (in next Sample Point).
946: -----------------------------------------------------------------------------------------------
947: bus_off_req_capt_proc : process(res_n, clk_sys)
948: begin
949: if (res_n = '0') then
950: mr_command_ercrst_q <= '0';
951: elsif (rising_edge(clk_sys)) then
952: if (mr_command_ercrst = '1') then
953: mr_command_ercrst_q <= '1';
954: elsif (rx_trigger = '1' and clr_bus_off_rst_flg = '1') then
955: mr_command_ercrst_q <= '0';
956: end if;
957: end if;
958: end process;
959:
960: -----------------------------------------------------------------------------------------------
961: -- Next state process
962: -----------------------------------------------------------------------------------------------
963: next_state_proc : process(
964: curr_state, err_frm_req, ctrl_ctr_zero, no_data_field, is_receiver, is_fd_frame,
965: is_bus_off, go_to_suspend, tran_frame_valid, mr_command_ercrst_q, reinteg_ctr_expired,
966: rx_data_nbs, is_err_active, go_to_stuff_count, pex_on_fdf_enable, pex_on_res_enable,
967: mr_mode_rom)
968: begin
969: next_state <= curr_state;
970:
971: if (err_frm_req = '1') then
972: if (mr_mode_rom = ROM_DISABLED) then
973: if (is_err_active = '1') then
974: next_state <= s_pc_act_err_flag;
975: else
976: next_state <= s_pc_pas_err_flag;
977: end if;
978: else
979: next_state <= s_pc_integrating;
980: end if;
981:
982: else
983: case curr_state is
984:
985: ---------------------------------------------------------------------------------------
986: -- Unit is Off
987: ---------------------------------------------------------------------------------------
988: when s_pc_off =>
989: next_state <= s_pc_integrating;
990:
991: ---------------------------------------------------------------------------------------
992: -- Unit is integrating (first integration after enabling)
993: ---------------------------------------------------------------------------------------
994: when s_pc_integrating =>
995: if (ctrl_ctr_zero = '1') then
996: next_state <= s_pc_idle;
997: end if;
998:
999: ---------------------------------------------------------------------------------------
1000: -- Start of frame
1001: ---------------------------------------------------------------------------------------
1002: when s_pc_sof =>
1003: next_state <= s_pc_base_id;
1004:
1005: ---------------------------------------------------------------------------------------
1006: -- Base identifier
1007: ---------------------------------------------------------------------------------------
1008: when s_pc_base_id =>
1009: if (ctrl_ctr_zero = '1') then
1010: next_state <= s_pc_rtr_srr_r1;
1011: end if;
1012:
1013: ---------------------------------------------------------------------------------------
1014: -- RTR/SRR/R1 bit. First bit after Base identifier.
1015: ---------------------------------------------------------------------------------------
1016: when s_pc_rtr_srr_r1 =>
1017: next_state <= s_pc_ide;
1018:
1019: ---------------------------------------------------------------------------------------
1020: -- IDE bit
1021: ---------------------------------------------------------------------------------------
1022: when s_pc_ide =>
1023: if (rx_data_nbs = DOMINANT) then
1024: next_state <= s_pc_edl_r0;
1025: else
1026: next_state <= s_pc_ext_id;
1027: end if;
1028:
1029: ---------------------------------------------------------------------------------------
1030: -- Extended identifier
1031: ---------------------------------------------------------------------------------------
1032: when s_pc_ext_id =>
1033: if (ctrl_ctr_zero = '1') then
1034: next_state <= s_pc_rtr_r1;
1035: end if;
1036:
1037: ---------------------------------------------------------------------------------------
1038: -- RTR/R1 bit after the Extended identifier
1039: ---------------------------------------------------------------------------------------
1040: when s_pc_rtr_r1 =>
1041: next_state <= s_pc_edl_r1;
1042:
1043: ---------------------------------------------------------------------------------------
1044: -- EDL/r1 bit after RTR/r1 bit in Extended Identifier
1045: ---------------------------------------------------------------------------------------
1046: when s_pc_edl_r1 =>
1047: if (rx_data_nbs = DOMINANT) then
1048: next_state <= s_pc_r0_ext;
1049: else
1050: if (pex_on_fdf_enable = '1') then
1051: next_state <= s_pc_integrating;
1052: else
1053: next_state <= s_pc_r0_fd;
1054: end if;
1055: end if;
1056:
1057: ---------------------------------------------------------------------------------------
1058: -- r0 bit after EDL/r1 bit in Extended CAN Frames.
1059: ---------------------------------------------------------------------------------------
1060: when s_pc_r0_ext =>
1061: next_state <= s_pc_dlc;
1062:
1063: ---------------------------------------------------------------------------------------
1064: -- r0(res) bit in CAN FD Frames (both Base and Extended identifier)
1065: ---------------------------------------------------------------------------------------
1066: when s_pc_r0_fd =>
1067: if (rx_data_nbs = RECESSIVE and pex_on_res_enable = '1') then
1068: next_state <= s_pc_integrating;
1069: else
1070: next_state <= s_pc_brs;
1071: end if;
1072:
1073: ---------------------------------------------------------------------------------------
1074: -- EDL/r0 bit in CAN 2.0 and CAN FD Frames with BASE identifier only!
1075: ---------------------------------------------------------------------------------------
1076: when s_pc_edl_r0 =>
1077: if (rx_data_nbs = DOMINANT) then
1078: next_state <= s_pc_dlc;
1079: else
1080: -- Protocol exception on recessive FDF/EDL in "Classical CAN" configuration
1081: if (pex_on_fdf_enable = '1') then
1082: next_state <= s_pc_integrating;
1083: else
1084: next_state <= s_pc_r0_fd;
1085: end if;
1086: end if;
1087:
1088: ---------------------------------------------------------------------------------------
1089: -- BRS (Bit rate shift) Bit
1090: ---------------------------------------------------------------------------------------
1091: when s_pc_brs =>
1092: next_state <= s_pc_esi;
1093:
1094: ---------------------------------------------------------------------------------------
1095: -- ESI (Error State Indicator) Bit
1096: ---------------------------------------------------------------------------------------
1097: when s_pc_esi =>
1098: next_state <= s_pc_dlc;
1099:
1100: ---------------------------------------------------------------------------------------
1101: -- DLC (Data length code)
1102: ---------------------------------------------------------------------------------------
1103: when s_pc_dlc =>
1104: if (ctrl_ctr_zero = '1') then
1105: if (no_data_field = '1') then
1106: if (go_to_stuff_count = '1') then
1107: next_state <= s_pc_stuff_count;
1108: else
1109: next_state <= s_pc_crc;
1110: end if;
1111: else
1112: next_state <= s_pc_data;
1113: end if;
1114: end if;
1115:
1116: ---------------------------------------------------------------------------------------
1117: -- Data field
1118: ---------------------------------------------------------------------------------------
1119: when s_pc_data =>
1120: if (ctrl_ctr_zero = '1') then
1121: if (go_to_stuff_count = '1') then
1122: next_state <= s_pc_stuff_count;
1123: else
1124: next_state <= s_pc_crc;
1125: end if;
1126: end if;
1127:
1128: ---------------------------------------------------------------------------------------
1129: -- Stuff count + Stuff parity field
1130: ---------------------------------------------------------------------------------------
1131: when s_pc_stuff_count =>
1132: if (ctrl_ctr_zero = '1') then
1133: next_state <= s_pc_crc;
1134: end if;
1135:
1136: ---------------------------------------------------------------------------------------
1137: -- CRC field
1138: ---------------------------------------------------------------------------------------
1139: when s_pc_crc =>
1140: if (ctrl_ctr_zero = '1') then
1141: next_state <= s_pc_crc_delim;
1142: end if;
1143:
1144: ---------------------------------------------------------------------------------------
1145: -- CRC Delimiter
1146: ---------------------------------------------------------------------------------------
1147: when s_pc_crc_delim =>
1148: if (is_fd_frame = '1') then
1149: next_state <= s_pc_ack_fd_1;
1150: else
1151: next_state <= s_pc_ack;
1152: end if;
1153:
1154: ---------------------------------------------------------------------------------------
1155: -- ACK Slot of CAN 2.0 frame
1156: ---------------------------------------------------------------------------------------
1157: when s_pc_ack =>
1158: next_state <= s_pc_ack_delim;
1159:
1160: ---------------------------------------------------------------------------------------
1161: -- First bit of CAN FD Frame ACK
1162: ---------------------------------------------------------------------------------------
1163: when s_pc_ack_fd_1 =>
1164: next_state <= s_pc_ack_fd_2;
1165:
1166: ---------------------------------------------------------------------------------------
1167: -- Second bit of CAN FD Frame ACK
1168: ---------------------------------------------------------------------------------------
1169: when s_pc_ack_fd_2 =>
1170: next_state <= s_pc_ack_delim;
1171:
1172: ---------------------------------------------------------------------------------------
1173: -- ACK Delimiter
1174: ---------------------------------------------------------------------------------------
1175: when s_pc_ack_delim =>
1176: next_state <= s_pc_eof;
1177:
1178: ---------------------------------------------------------------------------------------
1179: -- End of Frame. Receiver sampling DOMINANT in last bit interprets this as
1180: -- Overload flag.
1181: ---------------------------------------------------------------------------------------
1182: when s_pc_eof =>
1183: if (ctrl_ctr_zero = '1') then
1184: if (rx_data_nbs = RECESSIVE) then
1185: next_state <= s_pc_intermission;
1186: elsif (is_receiver = '1') then
1187: if (mr_mode_rom = ROM_DISABLED) then
1188: next_state <= s_pc_ovr_flag;
1189: else
1190: next_state <= s_pc_integrating;
1191: end if;
1192: end if;
1193: end if;
1194:
1195: ---------------------------------------------------------------------------------------
1196: -- Intermission field
1197: ---------------------------------------------------------------------------------------
1198: when s_pc_intermission =>
1199: if (is_bus_off = '1') then
1200: next_state <= s_pc_reintegrating_wait;
1201:
1202: -- Last bit of intermission!
1203: elsif (ctrl_ctr_zero = '1') then
1204: if (rx_data_nbs = DOMINANT) then
1205: next_state <= s_pc_base_id;
1206: elsif (go_to_suspend = '1') then
1207: next_state <= s_pc_suspend;
1208: elsif (tran_frame_valid = '1') then
1209: next_state <= s_pc_sof;
1210: else
1211: next_state <= s_pc_idle;
1212: end if;
1213:
1214: -- First or second bit of intermission!
1215: elsif (rx_data_nbs = DOMINANT) then
1216: if (mr_mode_rom = ROM_DISABLED) then
1217: next_state <= s_pc_ovr_flag;
1218: else
1219: next_state <= s_pc_integrating;
1220: end if;
1221: end if;
1222:
1223: ---------------------------------------------------------------------------------------
1224: -- Suspend transmission
1225: ---------------------------------------------------------------------------------------
1226: when s_pc_suspend =>
1227: if (rx_data_nbs = DOMINANT) then
1228: next_state <= s_pc_base_id;
1229: elsif (ctrl_ctr_zero = '1') then
1230: -- Start transmission after suspend if we have what to
1231: -- transmitt!
1232: if (tran_frame_valid = '1') then
1233: next_state <= s_pc_sof;
1234: else
1235: next_state <= s_pc_idle;
1236: end if;
1237: end if;
1238:
1239: ---------------------------------------------------------------------------------------
1240: -- Unit is in Bus idle period.
1241: ---------------------------------------------------------------------------------------
1242: when s_pc_idle =>
1243: if (is_bus_off = '1') then
1244: next_state <= s_pc_reintegrating_wait;
1245: elsif (rx_data_nbs = DOMINANT) then
1246: next_state <= s_pc_base_id;
1247: elsif (tran_frame_valid = '1') then
1248: next_state <= s_pc_sof;
1249: end if;
1250:
1251: ---------------------------------------------------------------------------------------
1252: -- Wait till command from User to start re-integration!
1253: ---------------------------------------------------------------------------------------
1254: when s_pc_reintegrating_wait =>
1255: if (mr_command_ercrst_q = '1') then
1256: next_state <= s_pc_reintegrating;
1257: end if;
1258:
1259: ---------------------------------------------------------------------------------------
1260: -- Unit is re-integrating, waiting till re-integration counter expires!
1261: ---------------------------------------------------------------------------------------
1262: when s_pc_reintegrating =>
1263: if (reinteg_ctr_expired = '1' and ctrl_ctr_zero = '1') then
1264: next_state <= s_pc_idle;
1265: end if;
1266:
1267: ---------------------------------------------------------------------------------------
1268: -- Active error flag.
1269: ---------------------------------------------------------------------------------------
1270: when s_pc_act_err_flag =>
1271: if (ctrl_ctr_zero = '1') then
1272: next_state <= s_pc_err_delim_wait;
1273: end if;
1274:
1275: ---------------------------------------------------------------------------------------
1276: -- Passive error flag.
1277: ---------------------------------------------------------------------------------------
1278: when s_pc_pas_err_flag =>
1279: if (ctrl_ctr_zero = '1') then
1280: next_state <= s_pc_err_delim_wait;
1281: end if;
1282:
1283: ---------------------------------------------------------------------------------------
1284: -- Wait till Error delimiter (detection of recessive bit)
1285: ---------------------------------------------------------------------------------------
1286: when s_pc_err_delim_wait =>
1287: if (rx_data_nbs = RECESSIVE) then
1288: next_state <= s_pc_err_delim;
1289: elsif (ctrl_ctr_zero = '1') then
1290: next_state <= s_pc_err_flag_too_long;
1291: end if;
1292:
1293: ---------------------------------------------------------------------------------------
1294: -- 13 dominant bits (6 Error flag + 7 Error delimiter) has been detected.
1295: ---------------------------------------------------------------------------------------
1296: when s_pc_err_flag_too_long =>
1297: if (rx_data_nbs = RECESSIVE) then
1298: next_state <= s_pc_err_delim;
1299: end if;
1300:
1301: ---------------------------------------------------------------------------------------
1302: -- 13 dominant bits (6 Overload flag + 7 Overload delimiter) has been detected.
1303: ---------------------------------------------------------------------------------------
1304: when s_pc_ovr_flag_too_long =>
1305: if (rx_data_nbs = RECESSIVE) then
1306: next_state <= s_pc_ovr_delim;
1307: end if;
1308:
1309: ---------------------------------------------------------------------------------------
1310: -- Error delimiter
1311: ---------------------------------------------------------------------------------------
1312: when s_pc_err_delim =>
1313: if (ctrl_ctr_zero = '1') then
1314: if (rx_data_nbs = DOMINANT) then
1315: next_state <= s_pc_ovr_flag;
1316: else
1317: next_state <= s_pc_intermission;
1318: end if;
1319: end if;
1320:
1321: ---------------------------------------------------------------------------------------
1322: -- Overload flag
1323: ---------------------------------------------------------------------------------------
1324: when s_pc_ovr_flag =>
1325: if (ctrl_ctr_zero = '1') then
1326: next_state <= s_pc_ovr_delim_wait;
1327: end if;
1328:
1329: ---------------------------------------------------------------------------------------
1330: -- Wait till overload delimiter.
1331: ---------------------------------------------------------------------------------------
1332: when s_pc_ovr_delim_wait =>
1333: if (rx_data_nbs = RECESSIVE) then
1334: next_state <= s_pc_ovr_delim;
1335: elsif (ctrl_ctr_zero = '1') then
1336: next_state <= s_pc_ovr_flag_too_long;
1337: end if;
1338:
1339: ---------------------------------------------------------------------------------------
1340: -- Overload delimiter
1341: ---------------------------------------------------------------------------------------
1342: when s_pc_ovr_delim =>
1343: if (ctrl_ctr_zero = '1') then
1344: if (rx_data_nbs = DOMINANT) then
1345: next_state <= s_pc_ovr_flag;
1346: else
1347: next_state <= s_pc_intermission;
1348: end if;
1349: end if;
1350: end case;
1351: end if;
1352: end process;
1353:
1354: -----------------------------------------------------------------------------------------------
1355: -- Current state process
1356: -----------------------------------------------------------------------------------------------
1357: curr_state_proc : process(
1358: curr_state, err_frm_req, sp_control_q_i, tx_failed, mr_settings_ena, rx_data_nbs,
1359: ctrl_ctr_zero, arbitration_lost_condition, tx_data_wbs, is_transmitter, tran_ident_type,
1360: tran_frame_type_i, tran_is_rtr, ide_is_arbitration, mr_mode_fde, tran_brs, rx_trigger,
1361: is_err_active, no_data_field, ctrl_counted_byte, ctrl_counted_byte_index, is_fd_frame,
1362: is_receiver, crc_match, mr_mode_stm, tran_frame_valid, go_to_suspend, frame_start,
1363: ctrl_ctr_one, mr_command_ercrst_q, reinteg_ctr_expired, first_err_delim_q, go_to_stuff_count,
1364: ack_err_flag, crc_length_i, data_length_bits_c, ctrl_ctr_mem_index, is_bus_off,
1365: block_txtb_unlock, mr_settings_pex, integ_restart_edge, rx_data_nbs_prev, sync_edge,
1366: mr_mode_rom, mr_settings_ilbp, tx_dominant_ack, rec_lbpf_q, rec_ivld_q, allow_flipped_ack)
1367: begin
1368:
1369: -------------------------------------------------------------------------------------------
1370: -- Default values
1371: -------------------------------------------------------------------------------------------
1372:
1373: -- Control counter
1374: ctrl_ctr_pload_i <= '0';
1375: ctrl_ctr_pload_val <= (others => '0');
1376: ctrl_ctr_pload_unaliged <= '0';
1377: ctrl_ctr_ena <= '0';
1378: compl_ctr_ena_i <= '0';
1379: arbitration_part <= ALC_RSVD;
1380:
1381: -- RX Buffer storing protocol
1382: store_metadata_d <= '0';
1383: store_data_d <= '0';
1384: rec_valid_d <= '0';
1385:
1386: sof_pulse_i <= '0';
1387:
1388: -- TXT Buffer HW Commands
1389: txtb_hw_cmd_d.lock <= '0';
1390: txtb_hw_cmd_d.valid <= '0';
1391: txtb_hw_cmd_d.err <= '0';
1392: txtb_hw_cmd_d.arbl <= '0';
1393: txtb_hw_cmd_d.failed <= '0';
1394:
1395: -- RX Shift register interface
1396: rx_store_base_id_i <= '0';
1397: rx_store_ext_id_i <= '0';
1398: rx_store_ide_i <= '0';
1399: rx_store_rtr_i <= '0';
1400: rx_store_edl_i <= '0';
1401: rx_store_dlc_i <= '0';
1402: rx_store_esi_i <= '0';
1403: rx_store_brs_i <= '0';
1404: rx_store_stuff_count_i <= '0';
1405:
1406: rx_shift_ena <= "0000";
1407: rx_shift_in_sel <= '0';
1408: rx_clear_i <= '0';
1409:
1410: -- TX Shift register interface
1411: tx_load_base_id_i <= '0';
1412: tx_load_ext_id_i <= '0';
1413: tx_load_dlc_i <= '0';
1414: tx_load_data_word_i <= '0';
1415: tx_load_stuff_count_i <= '0';
1416: tx_load_crc_i <= '0';
1417:
1418: tx_shift_ena_i <= '0';
1419: tx_dominant <= '0';
1420:
1421: reinteg_ctr_clr <= '0';
1422: reinteg_ctr_enable <= '0';
1423: is_arbitration_i <= '0';
1424: tx_dominant <= '0';
1425: crc_check <= '0';
1426:
1427: -- Error signalling
1428: form_err_i <= '0';
1429: ack_err_i <= '0';
1430: crc_err_i <= '0';
1431: bit_err_arb_i <= '0';
1432: bit_err_disable <= '0';
1433: bit_err_disable_receiver<= '0';
1434: crc_clear_match_flag <= '0';
1435: err_pos <= ERC_POS_OTHER;
1436:
1437: arbitration_lost_i <= '0';
1438: set_transmitter_i <= '0';
1439: set_receiver_i <= '0';
1440: set_idle_i <= '0';
1441:
1442: sp_control_switch_data <= '0';
1443: sp_control_switch_nominal <= '0';
1444:
1445: -- Transceiver delay measurement
1446: ssp_reset <= '0';
1447: tran_delay_meas <= '0';
1448:
1449: -- Secondary sampling point control
1450: btmc_reset <= '0';
1451: dbt_measure_start <= '0';
1452: gen_first_ssp <= '0';
1453:
1454: -- Fault confinement
1455: primary_err_i <= '0';
1456: err_delim_late_i <= '0';
1457: first_err_delim_d <= '0';
1458: set_err_active_i <= '0';
1459:
1460: br_shifted_i <= '0';
1461:
1462: -- Bit Stuffing/Destuffing control
1463: fixed_stuff <= '0';
1464: stuff_enable_set <= '0';
1465: stuff_enable_clear <= '0';
1466: destuff_enable_set <= '0';
1467: destuff_enable_clear <= '0';
1468: tx_frame_no_sof_d <= '0';
1469:
1470: -- Synchronisation control
1471: perform_hsync <= '0';
1472:
1473: -- TXT Buffer pointer
1474: txtb_ptr_d <= 0;
1475:
1476: -- CRC control
1477: crc_enable <= '0';
1478: crc_spec_enable_i <= '0';
1479: load_init_vect_i <= '0';
1480:
1481: -- Bit time counters enabling
1482: nbt_ctrs_en <= '1';
1483: dbt_ctrs_en <= '0';
1484:
1485: -- Clear block register for retransmitt counter add signal.
1486: retr_ctr_add_block_clr <= '0';
1487: tick_state_reg <= '0';
1488:
1489: -- Status signals for debug
1490: pc_dbg.is_control <= '0';
1491: pc_dbg.is_data <= '0';
1492: pc_dbg.is_stuff_count <= '0';
1493: pc_dbg.is_crc <= '0';
1494: pc_dbg.is_crc_delim <= '0';
1495: pc_dbg.is_ack <= '0';
1496: pc_dbg.is_ack_delim <= '0';
1497: pc_dbg.is_eof <= '0';
1498: pc_dbg.is_suspend <= '0';
1499: pc_dbg.is_err <= '0';
1500: pc_dbg.is_overload <= '0';
1501: pc_dbg.is_intermission <= '0';
1502: pc_dbg.is_sof <= '0';
1503:
1504: clr_bus_off_rst_flg <= '0';
1505: decrement_rec_i <= '0';
1506: ack_err_flag_clr <= '0';
1507: bit_err_after_ack_err <= '0';
1508:
1509: pexs_set <= '0';
1510:
1511: rec_lbpf_d <= rec_lbpf_q;
1512: rec_ivld_i <= rec_ivld_q;
1513:
1514: if (err_frm_req = '1') then
1515: tick_state_reg <= '1';
1516: ctrl_ctr_pload_i <= '1';
1517: if (mr_mode_rom = ROM_DISABLED) then
1518: ctrl_ctr_pload_val <= C_ERR_FLG_DURATION;
1519: else
1520: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1521: set_idle_i <= '1';
1522: end if;
1523:
1524: crc_clear_match_flag <= '1';
1525: destuff_enable_clear <= '1';
1526: stuff_enable_clear <= '1';
1527:
1528: if (sp_control_q_i = DATA_SAMPLE or
1529: sp_control_q_i = SECONDARY_SAMPLE)
1530: then
1531: sp_control_switch_nominal <= '1';
1532: br_shifted_i <= '1';
1533: end if;
1534:
1535: if (is_transmitter = '1' and block_txtb_unlock = '0') then
1536: if (tx_failed = '1') then
1537: txtb_hw_cmd_d.failed <= '1';
1538: else
1539: txtb_hw_cmd_d.err <= '1';
1540: end if;
1541: end if;
1542:
1543: -- Keep both counters enabled to make sure that Error frame starts at proper time when
1544: -- error occurred in Data Bit-rate.
1545: dbt_ctrs_en <= '1';
1546:
1547: else
1548: case curr_state is
1549:
1550: ---------------------------------------------------------------------------------------
1551: -- Unit is Off
1552: ---------------------------------------------------------------------------------------
1553: when s_pc_off =>
1554: if (mr_settings_ena = CTU_CAN_ENABLED) then
1555: nbt_ctrs_en <= '1';
1556: tick_state_reg <= '1';
1557: ctrl_ctr_pload_i <= '1';
1558: bit_err_disable <= '1';
1559:
1560: -- If we receive recessive, then set reintegration counter only to 10 (already
1561: -- one bit was measured)! During this state, whole TSEG1 already elapsed!
1562: if (rx_data_nbs = DOMINANT) then
1563: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1564: else
1565: ctrl_ctr_pload_val <= C_FIRST_INTEGRATION_DURATION;
1566: end if;
1567: else
1568: nbt_ctrs_en <= '0';
1569: end if;
1570:
1571: ---------------------------------------------------------------------------------------
1572: -- Unit is integrating (first integration after enabling)
1573: ---------------------------------------------------------------------------------------
1574: when s_pc_integrating =>
1575: bit_err_disable <= '1';
1576: ctrl_ctr_ena <= '1';
1577: perform_hsync <= '1';
1578:
1579: -- Restart integration upon reception of DOMINANT bit or upon synchronization edge
1580: -- detected!
1581: if (rx_data_nbs = DOMINANT or sync_edge = '1') then
1582: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1583: end if;
1584:
1585: -- When preloaded due to synchronisation edge, this is outside of sample point!
1586: if (rx_data_nbs = DOMINANT) then
1587: ctrl_ctr_pload_i <= '1';
1588: end if;
1589:
1590: if (integ_restart_edge = '1') then
1591: ctrl_ctr_pload_unaliged <= '1';
1592: end if;
1593:
1594: if (ctrl_ctr_zero = '1') then
1595: tick_state_reg <= '1';
1596: set_idle_i <= '1';
1597:
1598: -- Device can be integrating right after start or after protocol exception.
1599: -- Only after start, it is bus off, then it shall be set to error active and
1600: -- error counters shall be cleared. Otherwise, error counters shall retain
1601: -- their value!
1602: if (is_bus_off = '1') then
1603: set_err_active_i <= '1';
1604: end if;
1605: load_init_vect_i <= '1';
1606: end if;
1607:
1608: ---------------------------------------------------------------------------------------
1609: -- Start of frame
1610: ---------------------------------------------------------------------------------------
1611: when s_pc_sof =>
1612: tick_state_reg <= '1';
1613: bit_err_disable <= '1';
1614: ctrl_ctr_pload_i <= '1';
1615: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
1616: tx_load_base_id_i <= '1';
1617: sof_pulse_i <= '1';
1618: rec_ivld_i <= '0';
1619: tx_dominant <= '1';
1620: err_pos <= ERC_POS_SOF;
1621: crc_enable <= '1';
1622: pc_dbg.is_sof <= '1';
1623:
1624: -- If we have transmission pending, FSM goes to SOF in sample point of third bit of
1625: -- intermission or in idle. But till the end of bit, it is still Intermission/Idle
1626: -- from bus perspective, so we must allow hard-synchronization! Then, even during
1627: -- TSEG1 of SOF bit, we can keep hard-sync enabled, because it should be disabled
1628: -- due to no_pos_resync. since DUT sends dominant bit, and sync edge during TSEG1
1629: -- means positive phase error! Therefore any sync_edge will be ignored by prescaler!
1630: perform_hsync <= '1';
1631:
1632: if (rx_data_nbs = RECESSIVE) then
1633: form_err_i <= '1';
1634: end if;
1635:
1636: ---------------------------------------------------------------------------------------
1637: -- Base identifier
1638: ---------------------------------------------------------------------------------------
1639: when s_pc_base_id =>
1640: bit_err_disable <= '1';
1641: ctrl_ctr_ena <= '1';
1642: rx_shift_ena <= "1111";
1643: is_arbitration_i <= '1';
1644: tx_shift_ena_i <= '1';
1645: err_pos <= ERC_POS_ARB;
1646: crc_enable <= '1';
1647: arbitration_part <= ALC_BASE_ID;
1648:
1649: if (arbitration_lost_condition = '1') then
1650: arbitration_lost_i <= '1';
1651: stuff_enable_clear <= '1';
1652: if (tx_failed = '1') then
1653: txtb_hw_cmd_d.failed <= '1';
1654: else
1655: txtb_hw_cmd_d.arbl <= '1';
1656: end if;
1657: end if;
1658:
1659: if (ctrl_ctr_zero = '1') then
1660: tick_state_reg <= '1';
1661: rx_store_base_id_i <= '1';
1662: end if;
1663:
1664: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1665: bit_err_arb_i <= '1';
1666: end if;
1667:
1668: ---------------------------------------------------------------------------------------
1669: -- RTR/SRR/R1 bit. First bit after Base identifier.
1670: ---------------------------------------------------------------------------------------
1671: when s_pc_rtr_srr_r1 =>
1672: tick_state_reg <= '1';
1673: is_arbitration_i <= '1';
1674: bit_err_disable <= '1';
1675: crc_enable <= '1';
1676: rx_store_rtr_i <= '1';
1677: err_pos <= ERC_POS_ARB;
1678: arbitration_part <= ALC_SRR_RTR;
1679:
1680: if (arbitration_lost_condition = '1') then
1681: arbitration_lost_i <= '1';
1682: stuff_enable_clear <= '1';
1683: if (tx_failed = '1') then
1684: txtb_hw_cmd_d.failed <= '1';
1685: else
1686: txtb_hw_cmd_d.arbl <= '1';
1687: end if;
1688: end if;
1689:
1690: if (is_transmitter = '1' and tran_ident_type = BASE) then
1691: if (tran_frame_type_i = FD_CAN or tran_is_rtr = NO_RTR_FRAME) then
1692: tx_dominant <= '1';
1693: end if;
1694: end if;
1695:
1696: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1697: bit_err_arb_i <= '1';
1698: end if;
1699:
1700: ---------------------------------------------------------------------------------------
1701: -- IDE bit
1702: ---------------------------------------------------------------------------------------
1703: when s_pc_ide =>
1704: tick_state_reg <= '1';
1705: rx_store_ide_i <= '1';
1706: crc_enable <= '1';
1707: arbitration_part <= ALC_IDE;
1708:
1709: if (rx_data_nbs = RECESSIVE) then
1710: ctrl_ctr_pload_i <= '1';
1711: ctrl_ctr_pload_val <= C_EXT_ID_DURATION;
1712: tx_load_ext_id_i <= '1';
1713: else
1714: rec_ivld_i <= '1';
1715: end if;
1716:
1717: if (ide_is_arbitration = '1' and arbitration_lost_condition = '1') then
1718: arbitration_lost_i <= '1';
1719: stuff_enable_clear <= '1';
1720: if (tx_failed = '1') then
1721: txtb_hw_cmd_d.failed <= '1';
1722: else
1723: txtb_hw_cmd_d.arbl <= '1';
1724: end if;
1725: end if;
1726:
1727: if (ide_is_arbitration = '1') then
1728: is_arbitration_i <= '1';
1729: bit_err_disable <= '1';
1730: else
1731: pc_dbg.is_control <= '1';
1732: end if;
1733:
1734: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1735: bit_err_arb_i <= '1';
1736: end if;
1737:
1738: if (is_transmitter = '1' and tran_ident_type = BASE) then
1739: tx_dominant <= '1';
1740: end if;
1741:
1742: if (ide_is_arbitration = '1') then
1743: err_pos <= ERC_POS_ARB;
1744: else
1745: err_pos <= ERC_POS_CTRL;
1746: end if;
1747:
1748: ---------------------------------------------------------------------------------------
1749: -- Extended identifier
1750: ---------------------------------------------------------------------------------------
1751: when s_pc_ext_id =>
1752: ctrl_ctr_ena <= '1';
1753: rx_shift_ena <= "1111";
1754: is_arbitration_i <= '1';
1755: tx_shift_ena_i <= '1';
1756: err_pos <= ERC_POS_ARB;
1757: bit_err_disable <= '1';
1758: crc_enable <= '1';
1759: arbitration_part <= ALC_EXTENSION;
1760:
1761: if (arbitration_lost_condition = '1') then
1762: arbitration_lost_i <= '1';
1763: stuff_enable_clear <= '1';
1764: if (tx_failed = '1') then
1765: txtb_hw_cmd_d.failed <= '1';
1766: else
1767: txtb_hw_cmd_d.arbl <= '1';
1768: end if;
1769: end if;
1770:
1771: if (ctrl_ctr_zero = '1') then
1772: tick_state_reg <= '1';
1773: rx_store_ext_id_i <= '1';
1774: end if;
1775:
1776: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1777: bit_err_arb_i <= '1';
1778: end if;
1779:
1780: ---------------------------------------------------------------------------------------
1781: -- RTR/R1 bit after the Extended identifier
1782: ---------------------------------------------------------------------------------------
1783: when s_pc_rtr_r1 =>
1784: tick_state_reg <= '1';
1785: is_arbitration_i <= '1';
1786: bit_err_disable <= '1';
1787: crc_enable <= '1';
1788: rx_store_rtr_i <= '1';
1789: err_pos <= ERC_POS_ARB;
1790: arbitration_part <= ALC_RTR;
1791: rec_ivld_i <= '1';
1792:
1793: if (arbitration_lost_condition = '1') then
1794: arbitration_lost_i <= '1';
1795: stuff_enable_clear <= '1';
1796: if (tx_failed = '1') then
1797: txtb_hw_cmd_d.failed <= '1';
1798: else
1799: txtb_hw_cmd_d.arbl <= '1';
1800: end if;
1801: end if;
1802:
1803: if (is_transmitter = '1') then
1804: if (tran_frame_type_i = FD_CAN) then
1805: tx_dominant <= '1';
1806: elsif (tran_is_rtr = NO_RTR_FRAME) then
1807: tx_dominant <= '1';
1808: end if;
1809: end if;
1810:
1811: if (tx_data_wbs = DOMINANT and rx_data_nbs = RECESSIVE) then
1812: bit_err_arb_i <= '1';
1813: end if;
1814:
1815: ---------------------------------------------------------------------------------------
1816: -- EDL/r1 bit after RTR/r1 bit in Extended Identifier
1817: ---------------------------------------------------------------------------------------
1818: when s_pc_edl_r1 =>
1819: tick_state_reg <= '1';
1820: rx_store_edl_i <= '1';
1821: err_pos <= ERC_POS_CTRL;
1822: crc_enable <= '1';
1823: pc_dbg.is_control <= '1';
1824: bit_err_disable_receiver <= '1';
1825:
1826: if (is_transmitter = '1') then
1827: if (tran_frame_type_i = NORMAL_CAN) then
1828: tx_dominant <= '1';
1829: else
1830: ssp_reset <= '1';
1831: end if;
1832: end if;
1833:
1834: -- Sample recessive but CAN FD is disabled -> Form error or protocol exception!
1835: if (rx_data_nbs = RECESSIVE and mr_mode_fde = FDE_DISABLE)
1836: then
1837: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1838: form_err_i <= '1';
1839:
1840: -- Detect protocol exception. Disable bit stuffing.
1841: else
1842: destuff_enable_clear <= '1';
1843: ctrl_ctr_pload_i <= '1';
1844: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1845: pexs_set <= '1';
1846: end if;
1847: end if;
1848:
1849: ---------------------------------------------------------------------------------------
1850: -- r0 bit after EDL/r1 bit in Extended CAN Frames.
1851: ---------------------------------------------------------------------------------------
1852: when s_pc_r0_ext =>
1853: tick_state_reg <= '1';
1854: ctrl_ctr_pload_i <= '1';
1855: ctrl_ctr_pload_val <= C_DLC_DURATION;
1856: tx_load_dlc_i <= '1';
1857: err_pos <= ERC_POS_CTRL;
1858: tran_delay_meas <= '1';
1859: crc_enable <= '1';
1860: pc_dbg.is_control <= '1';
1861: bit_err_disable_receiver <= '1';
1862:
1863: if (is_transmitter = '1') then
1864: tx_dominant <= '1';
1865: end if;
1866:
1867: ---------------------------------------------------------------------------------------
1868: -- r0 bit in CAN FD Frames (both Base and Extended identifier)
1869: ---------------------------------------------------------------------------------------
1870: when s_pc_r0_fd =>
1871: tick_state_reg <= '1';
1872: tran_delay_meas <= '1';
1873: err_pos <= ERC_POS_CTRL;
1874: perform_hsync <= '1';
1875: crc_enable <= '1';
1876: pc_dbg.is_control <= '1';
1877: bit_err_disable_receiver <= '1';
1878:
1879: if (is_transmitter = '1') then
1880: tx_dominant <= '1';
1881: end if;
1882:
1883: -- Here recessive would mean further extending beyond CAN FD protocol (CAN XL in
1884: -- future). Now we don't have protocol exception, so we throw error here!
1885: if (rx_data_nbs = RECESSIVE) then
1886: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1887: form_err_i <= '1';
1888:
1889: -- Detect protocol exception. Disable bit stuffing.
1890: else
1891: destuff_enable_clear <= '1';
1892: ctrl_ctr_pload_i <= '1';
1893: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1894: pexs_set <= '1';
1895: end if;
1896: end if;
1897:
1898: ---------------------------------------------------------------------------------------
1899: -- EDL/r0 bit in CAN 2.0 and CAN FD Frames with BASE identifier only!
1900: ---------------------------------------------------------------------------------------
1901: when s_pc_edl_r0 =>
1902: tick_state_reg <= '1';
1903: rx_store_edl_i <= '1';
1904: err_pos <= ERC_POS_CTRL;
1905: crc_enable <= '1';
1906: pc_dbg.is_control <= '1';
1907: bit_err_disable_receiver <= '1';
1908:
1909: if (rx_data_nbs = DOMINANT) then
1910: ctrl_ctr_pload_i <= '1';
1911: ctrl_ctr_pload_val <= C_DLC_DURATION;
1912: tx_load_dlc_i <= '1';
1913: end if;
1914:
1915: if (is_transmitter = '1' and tran_frame_type_i = NORMAL_CAN) then
1916: tx_dominant <= '1';
1917: else
1918: ssp_reset <= '1';
1919: end if;
1920:
1921: -- Sample recessive but CAN FD is disabled -> Form error or
1922: -- protocol exception!
1923: if (rx_data_nbs = RECESSIVE and mr_mode_fde = FDE_DISABLE) then
1924: if (mr_settings_pex = PROTOCOL_EXCEPTION_DISABLED) then
1925: form_err_i <= '1';
1926:
1927: -- Detect protocol exception. Disable bit stuffing.
1928: else
1929: destuff_enable_clear <= '1';
1930: ctrl_ctr_pload_i <= '1';
1931: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
1932: pexs_set <= '1';
1933: end if;
1934: end if;
1935:
1936: ---------------------------------------------------------------------------------------
1937: -- BRS (Bit rate shift) Bit
1938: ---------------------------------------------------------------------------------------
1939: when s_pc_brs =>
1940: tick_state_reg <= '1';
1941: rx_store_brs_i <= '1';
1942: err_pos <= ERC_POS_CTRL;
1943: crc_enable <= '1';
1944: pc_dbg.is_control <= '1';
1945: bit_err_disable_receiver <= '1';
1946: dbt_ctrs_en <= '1';
1947: btmc_reset <= '1';
1948:
1949: if (is_transmitter = '1' and tran_brs = BR_NO_SHIFT) then
1950: tx_dominant <= '1';
1951: end if;
1952:
1953: if (rx_data_nbs = RECESSIVE and rx_trigger = '1') then
1954: sp_control_switch_data <= '1';
1955: br_shifted_i <= '1';
1956: end if;
1957:
1958: ---------------------------------------------------------------------------------------
1959: -- ESI (Error State Indicator) Bit
1960: ---------------------------------------------------------------------------------------
1961: when s_pc_esi =>
1962: tick_state_reg <= '1';
1963: ctrl_ctr_pload_i <= '1';
1964: ctrl_ctr_pload_val <= C_DLC_DURATION;
1965: tx_load_dlc_i <= '1';
1966: rx_store_esi_i <= '1';
1967: err_pos <= ERC_POS_CTRL;
1968: crc_enable <= '1';
1969: pc_dbg.is_control <= '1';
1970: bit_err_disable_receiver <= '1';
1971: dbt_ctrs_en <= '1';
1972:
1973: if (is_transmitter = '1' and is_err_active = '1') then
1974: tx_dominant <= '1';
1975: end if;
1976:
1977: -- Transmitter transmitts via SSP
1978: if (sp_control_q_i = SECONDARY_SAMPLE) then
1979: dbt_measure_start <= '1';
1980: gen_first_ssp <= '1';
1981: end if;
1982:
1983: ---------------------------------------------------------------------------------------
1984: -- DLC (Data length code)
1985: ---------------------------------------------------------------------------------------
1986: when s_pc_dlc =>
1987: ctrl_ctr_ena <= '1';
1988: rx_shift_ena <= "1111";
1989: tx_shift_ena_i <= '1';
1990: err_pos <= ERC_POS_CTRL;
1991: crc_enable <= '1';
1992: pc_dbg.is_control <= '1';
1993: bit_err_disable_receiver <= '1';
1994:
1995: if (sp_control_q_i /= NOMINAL_SAMPLE) then
1996: dbt_ctrs_en <= '1';
1997: end if;
1998:
1999: -- Address first Data Word in TXT Buffer RAM in advance to account for DFF delay
2000: -- and RAM delay! Do it only when transmitting to avoid toggling of RAM signals
2001: -- during reception (possible power consideration)
2002: if (is_transmitter = '1') then
2003: txtb_ptr_d <= 4;
2004: end if;
2005:
2006: if (ctrl_ctr_zero = '1') then
2007: tick_state_reg <= '1';
2008: ctrl_ctr_pload_i <= '1';
2009:
2010: if (no_data_field = '1') then
2011: if (go_to_stuff_count = '1') then
2012: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
2013: tx_load_stuff_count_i <= '1';
2014: else
2015: ctrl_ctr_pload_val <= crc_length_i;
2016: tx_load_crc_i <= '1';
2017: end if;
2018: else
2019: ctrl_ctr_pload_val <= data_length_bits_c;
2020: tx_load_data_word_i <= '1';
2021: end if;
2022:
2023: if (is_transmitter = '1' and mr_settings_ilbp = '1') then
2024: rec_lbpf_d <= LBPF_LOOPBACK;
2025: else
2026: rec_lbpf_d <= LBPF_FOREIGN;
2027: end if;
2028:
2029: store_metadata_d <= '1';
2030: rx_store_dlc_i <= '1';
2031: end if;
2032:
2033: ---------------------------------------------------------------------------------------
2034: -- Data field
2035: ---------------------------------------------------------------------------------------
2036: when s_pc_data =>
2037: ctrl_ctr_ena <= '1';
2038: rx_shift_ena(to_integer(unsigned(ctrl_counted_byte_index))) <= '1';
2039: rx_shift_in_sel <= '1';
2040: tx_shift_ena_i <= '1';
2041: err_pos <= ERC_POS_DATA;
2042: crc_enable <= '1';
2043: pc_dbg.is_data <= '1';
2044: compl_ctr_ena_i <= '1';
2045: bit_err_disable_receiver <= '1';
2046:
2047: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2048: dbt_ctrs_en <= '1';
2049: end if;
2050:
2051: -- Address next word (the one after actually transmitted one), so that when current
2052: -- word ends, TXT Buffer RAM already provides data on its output! Counter is divided
2053: -- by 32 since each memory word contains 32 bits!
2054: if (is_transmitter = '1') then
2055: txtb_ptr_d <= to_integer(unsigned(ctrl_ctr_mem_index));
2056: end if;
2057:
2058: if (ctrl_ctr_zero = '1') then
2059: tick_state_reg <= '1';
2060: ctrl_ctr_pload_i <= '1';
2061:
2062: if (go_to_stuff_count = '1') then
2063: ctrl_ctr_pload_val <= C_STUFF_COUNT_DURATION;
2064: tx_load_stuff_count_i <= '1';
2065: else
2066: ctrl_ctr_pload_val <= crc_length_i;
2067: tx_load_crc_i <= '1';
2068: end if;
2069:
2070: -- Store data word at the end of data field.
2071: store_data_d <= '1';
2072: end if;
2073:
2074: -- Store data word when multiple of 4 data bytes were counted! Avoid storing at the
2075: -- end of Data field, because CRC must be preloaded then!
2076: if (ctrl_counted_byte = '1' and
2077: ctrl_counted_byte_index = "11" and
2078: ctrl_ctr_zero = '0')
2079: then
2080: store_data_d <= '1';
2081: tx_load_data_word_i <= '1';
2082: end if;
2083:
2084: ---------------------------------------------------------------------------------------
2085: -- Stuff count + Stuff parity field
2086: ---------------------------------------------------------------------------------------
2087: when s_pc_stuff_count =>
2088: ctrl_ctr_ena <= '1';
2089: rx_shift_ena <= "1111";
2090: tx_shift_ena_i <= '1';
2091: err_pos <= ERC_POS_CRC;
2092: crc_enable <= '1';
2093: pc_dbg.is_stuff_count <= '1';
2094: bit_err_disable_receiver <= '1';
2095: fixed_stuff <= '1';
2096:
2097: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2098: dbt_ctrs_en <= '1';
2099: end if;
2100:
2101: if (ctrl_ctr_zero = '1') then
2102: tick_state_reg <= '1';
2103: ctrl_ctr_pload_val <= crc_length_i;
2104: ctrl_ctr_pload_i <= '1';
2105: tx_load_crc_i <= '1';
2106: rx_store_stuff_count_i <= '1';
2107: end if;
2108:
2109: ---------------------------------------------------------------------------------------
2110: -- CRC field
2111: ---------------------------------------------------------------------------------------
2112: when s_pc_crc =>
2113: ctrl_ctr_ena <= '1';
2114: rx_shift_ena <= "1111";
2115: tx_shift_ena_i <= '1';
2116: err_pos <= ERC_POS_CRC;
2117: pc_dbg.is_crc <= '1';
2118: bit_err_disable_receiver <= '1';
2119:
2120: if (sp_control_q_i /= NOMINAL_SAMPLE) then
2121: dbt_ctrs_en <= '1';
2122: end if;
2123:
2124: if (is_fd_frame = '1') then
2125: fixed_stuff <= '1';
2126: end if;
2127:
2128: if (ctrl_ctr_zero = '1') then
2129: tick_state_reg <= '1';
2130: end if;
2131:
2132: ---------------------------------------------------------------------------------------
2133: -- CRC Delimiter
2134: ---------------------------------------------------------------------------------------
2135: when s_pc_crc_delim =>
2136: tick_state_reg <= '1';
2137: err_pos <= ERC_POS_ACK;
2138: pc_dbg.is_crc_delim <= '1';
2139:
2140: -- Bit Error detection must be enabled for SSP
2141: -- Special enable used only in CRC delimiter when SSP is enabled and
2142: -- a SSP that reaches into TSEG1 of CRC delimiter shall detect error
2143: -- from a previous bit !
2144: -- In the moment of sample point, this must be already disabled though!
2145: -- So use rx_trigger to gate this. Do not gate by sp_control_d to avoid
2146: -- potential combo loop.
2147: --if (sp_control_q_i /= SECONDARY_SAMPLE and rx_trigger = '0') then
2148: -- bit_err_disable <= '1';
2149: --end if;
2150:
2151: -- Theoretically, we should enable bit error detection here when in SECONDARY_SAMPLE.
2152: -- (see commented code above). This would allow us to detect e.g. bit error of last bit
2153: -- of last CRC bit whose sample point is TSEG1 of CRC delimiter. This-way a bit error
2154: -- detected by SSP right in the SP of CRC delimiter would be ignored, but any earlier
2155: -- SSP (e.g. just one cycle before regular SP of CRC delimiter) would be recognized as
2156: -- bit error. ISO compliance test 8.8.2.4 tests that a "correct value" pulse around
2157: -- CRC Delimiter regular sample point will not cause error frame. There is no ISO test
2158: -- that tests if a SSP of a e.g. last CRC bit is placed in middle of CRC delimiters
2159: -- TSEG1 and detects bit error. We choose less "strict" various and opt not to detect
2160: -- bit error in this case as that may affect compliance test result! This corresponds
2161: -- to 2v5 behavior if SSP occurs anywhere within CRC delimiter. Possibly can be adjusted
2162: -- based on certification results.
2163: bit_err_disable <= '1';
2164:
2165: dbt_ctrs_en <= '1';
2166: destuff_enable_clear <= '1';
2167: stuff_enable_clear <= '1';
2168:
2169: if (rx_trigger = '1') then
2170: crc_check <= '1';
2171:
2172: if (rx_data_nbs = DOMINANT) then
2173: form_err_i <= '1';
2174: end if;
2175:
2176: if (sp_control_q_i = DATA_SAMPLE or sp_control_q_i = SECONDARY_SAMPLE) then
2177: sp_control_switch_nominal <= '1';
2178: br_shifted_i <= '1';
2179: end if;
2180: end if;
2181:
2182: ---------------------------------------------------------------------------------------
2183: -- ACK Slot of CAN 2.0 frame
2184: ---------------------------------------------------------------------------------------
2185: when s_pc_ack =>
2186: tick_state_reg <= '1';
2187: err_pos <= ERC_POS_ACK;
2188: pc_dbg.is_ack <= '1';
2189: dbt_ctrs_en <= '1';
2190:
2191: if (tx_dominant_ack = '1') then
2192: tx_dominant <= '1';
2193: end if;
2194:
2195: if (allow_flipped_ack = '1') then
2196: bit_err_disable <= '1';
2197: end if;
2198:
2199: if (is_receiver = '1' and crc_match = '1' and rx_data_nbs = DOMINANT) then
2200: decrement_rec_i <= '1';
2201: end if;
2202:
2203: if (is_transmitter = '1' and mr_mode_stm = '0' and rx_data_nbs = RECESSIVE) then
2204: ack_err_i <= '1';
2205: end if;
2206:
2207: ---------------------------------------------------------------------------------------
2208: -- First bit of CAN FD Frame ACK - Receiver sends ACK
2209: ---------------------------------------------------------------------------------------
2210: when s_pc_ack_fd_1 =>
2211: tick_state_reg <= '1';
2212: err_pos <= ERC_POS_ACK;
2213: pc_dbg.is_ack <= '1';
2214: dbt_ctrs_en <= '1';
2215:
2216: if (tx_dominant_ack = '1') then
2217: tx_dominant <= '1';
2218: end if;
2219:
2220: if (allow_flipped_ack = '1') then
2221: bit_err_disable <= '1';
2222: end if;
2223:
2224: if (is_receiver = '1' and crc_match = '1' and rx_data_nbs = DOMINANT) then
2225: decrement_rec_i <= '1';
2226: end if;
2227:
2228: ---------------------------------------------------------------------------------------
2229: -- Second bit of CAN FD Frame ACK
2230: ---------------------------------------------------------------------------------------
2231: when s_pc_ack_fd_2 =>
2232: tick_state_reg <= '1';
2233: err_pos <= ERC_POS_ACK;
2234: pc_dbg.is_ack <= '1';
2235: dbt_ctrs_en <= '1';
2236:
2237: -- No ACK sent now, but dominant or recessive should be tolerated.
2238: bit_err_disable <= '1';
2239:
2240: -- Transmitter not detecting dominant bit now, nor at previous bit -> Ack Error
2241: if (is_transmitter = '1' and mr_mode_stm = '0' and
2242: rx_data_nbs = RECESSIVE and rx_data_nbs_prev = RECESSIVE)
2243: then
2244: ack_err_i <= '1';
2245: end if;
2246:
2247: ---------------------------------------------------------------------------------------
2248: -- ACK Delimiter
2249: ---------------------------------------------------------------------------------------
2250: when s_pc_ack_delim =>
2251: tick_state_reg <= '1';
2252: ctrl_ctr_pload_i <= '1';
2253: ctrl_ctr_pload_val <= C_EOF_DURATION;
2254: err_pos <= ERC_POS_ACK;
2255: pc_dbg.is_ack_delim <= '1';
2256: bit_err_disable <= '1';
2257:
2258: if (rx_data_nbs = DOMINANT) then
2259: form_err_i <= '1';
2260: end if;
2261:
2262: if (is_receiver = '1' and crc_match = '0') then
2263: crc_err_i <= '1';
2264: end if;
2265:
2266: ---------------------------------------------------------------------------------------
2267: -- End of Frame. Receiver sampling DOMINANT in last bit interprets this as Overload
2268: -- flag!
2269: ---------------------------------------------------------------------------------------
2270: when s_pc_eof =>
2271: ctrl_ctr_ena <= '1';
2272: pc_dbg.is_eof <= '1';
2273: err_pos <= ERC_POS_EOF;
2274: bit_err_disable <= '1';
2275:
2276: if (ctrl_ctr_zero = '1') then
2277: tick_state_reg <= '1';
2278: ctrl_ctr_pload_i <= '1';
2279:
2280: if (rx_data_nbs = RECESSIVE) then
2281: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
2282:
2283: -- No Error until the end of EOF means frame is valid for transmitter!
2284: if (is_transmitter = '1') then
2285: txtb_hw_cmd_d.valid <= '1';
2286: end if;
2287:
2288: elsif (is_receiver = '1') then
2289: if (mr_mode_rom = ROM_DISABLED) then
2290: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2291: else
2292: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2293: set_idle_i <= '1';
2294: end if;
2295: end if;
2296:
2297: crc_clear_match_flag <= '1';
2298: end if;
2299:
2300: -- If there is no error (RX Recessive) in one bit before end of EOF, signal valid
2301: -- Frame reception!
2302: if (ctrl_ctr_one = '1' and rx_data_nbs = RECESSIVE) then
2303: rec_valid_d <= '1';
2304: end if;
2305:
2306: -- DOMINANT during EOF. All bits before last -> Form error! Last bit -> Receiver
2307: -- treats it as overload condition, so no error frame will be transmitted.
2308: -- Transmitter treats it as Form error!
2309: if (rx_data_nbs = DOMINANT) then
2310: if (ctrl_ctr_zero = '0') then
2311: form_err_i <= '1';
2312: elsif (is_transmitter = '1') then
2313: form_err_i <= '1';
2314: end if;
2315: end if;
2316:
2317: ---------------------------------------------------------------------------------------
2318: -- Intermission field
2319: ---------------------------------------------------------------------------------------
2320: when s_pc_intermission =>
2321: ctrl_ctr_ena <= '1';
2322: pc_dbg.is_intermission <= '1';
2323: retr_ctr_add_block_clr <= '1';
2324: bit_err_disable <= '1';
2325:
2326: -- If we are bus-off, go to reintegration wait!
2327: if (is_bus_off = '1') then
2328: tick_state_reg <= '1';
2329:
2330: else
2331: -- Last (third) bit of intermission
2332: if (ctrl_ctr_zero = '1') then
2333: tick_state_reg <= '1';
2334: ctrl_ctr_pload_i <= '1';
2335: crc_spec_enable_i <= '1';
2336:
2337: -- Go to Base ID (sampling of DOMINANT in the third bit of intermission)!
2338: if (rx_data_nbs = DOMINANT) then
2339: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
2340: tx_load_base_id_i <= '1';
2341: sof_pulse_i <= '1';
2342: rec_ivld_i <= '0';
2343:
2344: -- Goes to either IDLE, Suspend, or to SOF, when there is sth. to transmitt.
2345: -- Preload SUSPEND length in any case, since other states don't care about
2346: -- control counter.
2347: else
2348: ctrl_ctr_pload_val <= C_SUSPEND_DURATION;
2349: end if;
2350:
2351: -- Lock TXT Buffer when there is what to transmitt, and no suspend! Unit becomes
2352: -- transmitter! If not, and DOMINANT is received, become receiver!
2353: if (tran_frame_valid = '1' and go_to_suspend = '0') then
2354: txtb_hw_cmd_d.lock <= '1';
2355: set_transmitter_i <= '1';
2356: stuff_enable_set <= '1';
2357:
2358: if (rx_data_nbs = DOMINANT) then
2359: tx_frame_no_sof_d <= '1';
2360: end if;
2361:
2362: elsif (rx_data_nbs = DOMINANT) then
2363: set_receiver_i <= '1';
2364: end if;
2365:
2366: -- Transmission/reception started -> Enable Bit stuffing! Clear RX Shift
2367: -- Register!
2368: if (frame_start = '1') then
2369: destuff_enable_set <= '1';
2370: rx_clear_i <= '1';
2371: end if;
2372:
2373: -- If we dont sample dominant, nor we have sth ready for transmission, we go to
2374: -- Idle! Don't become idle when we go to suspend!
2375: if (rx_data_nbs = RECESSIVE and tran_frame_valid = '0' and
2376: go_to_suspend = '0')
2377: then
2378: set_idle_i <= '1';
2379: end if;
2380:
2381: -- First or second bit of intermission!
2382: elsif (rx_data_nbs = DOMINANT) then
2383: tick_state_reg <= '1';
2384: ctrl_ctr_pload_i <= '1';
2385: if (mr_mode_rom = ROM_DISABLED) then
2386: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2387: else
2388: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2389: set_idle_i <= '1';
2390: end if;
2391: end if;
2392:
2393: end if;
2394:
2395: -- Second or third bit of intermission, Hard Synchronisation
2396: if (ctrl_ctr_zero = '1' or ctrl_ctr_one = '1') then
2397: perform_hsync <= '1';
2398: end if;
2399:
2400: -- First or second bit of Intermission, pre-load CRC Init vector for next frame.
2401: if (ctrl_ctr_zero = '0') then
2402: load_init_vect_i <= '1';
2403: end if;
2404:
2405: ---------------------------------------------------------------------------------------
2406: -- Suspend transmission
2407: ---------------------------------------------------------------------------------------
2408: when s_pc_suspend =>
2409: ctrl_ctr_ena <= '1';
2410: perform_hsync <= '1';
2411: crc_spec_enable_i <= '1';
2412: bit_err_disable <= '1';
2413: pc_dbg.is_suspend <= '1';
2414:
2415: if (rx_data_nbs = DOMINANT) then
2416: tick_state_reg <= '1';
2417: ctrl_ctr_pload_i <= '1';
2418: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
2419: tx_load_base_id_i <= '1';
2420: sof_pulse_i <= '1';
2421: rec_ivld_i <= '0';
2422: set_receiver_i <= '1';
2423: destuff_enable_set <= '1';
2424: rx_clear_i <= '1';
2425:
2426: -- End of Suspend -> Unit goes to IDLE if there is nothing to transmitt, otherwise
2427: -- it goes to SOF and transmitts
2428: elsif (ctrl_ctr_zero = '1') then
2429: tick_state_reg <= '1';
2430: if (tran_frame_valid = '1') then
2431: set_transmitter_i <= '1';
2432: txtb_hw_cmd_d.lock <= '1';
2433: rx_clear_i <= '1';
2434: destuff_enable_set <= '1';
2435: stuff_enable_set <= '1';
2436: else
2437: set_idle_i <= '1';
2438: end if;
2439: end if;
2440:
2441: ---------------------------------------------------------------------------------------
2442: -- Unit is in Bus idle period.
2443: ---------------------------------------------------------------------------------------
2444: when s_pc_idle =>
2445: perform_hsync <= '1';
2446: crc_spec_enable_i <= '1';
2447: bit_err_disable <= '1';
2448:
2449: if (is_bus_off = '0') then
2450: if (rx_data_nbs = DOMINANT) then
2451: tick_state_reg <= '1';
2452: ctrl_ctr_pload_i <= '1';
2453: ctrl_ctr_pload_val <= C_BASE_ID_DURATION;
2454: sof_pulse_i <= '1';
2455: rec_ivld_i <= '0';
2456: crc_enable <= '1';
2457: end if;
2458:
2459: if (tran_frame_valid = '1') then
2460: tick_state_reg <= '1';
2461: txtb_hw_cmd_d.lock <= '1';
2462: set_transmitter_i <= '1';
2463: tx_load_base_id_i <= '1';
2464: stuff_enable_set <= '1';
2465:
2466: if (rx_data_nbs = DOMINANT) then
2467: tx_frame_no_sof_d <= '1';
2468: end if;
2469:
2470: elsif (rx_data_nbs = DOMINANT) then
2471: set_receiver_i <= '1';
2472: end if;
2473:
2474: -- Transmission/reception started -> Enable Bit de-stuffing! Clear RX Shift
2475: -- register!
2476: if (frame_start = '1') then
2477: destuff_enable_set <= '1';
2478: rx_clear_i <= '1';
2479: end if;
2480:
2481: -- If we are bus-off we need to move to wait for reintegration command!
2482: else
2483: tick_state_reg <= '1';
2484: end if;
2485:
2486: ---------------------------------------------------------------------------------------
2487: -- Wait till command from User to start re-integration!
2488: ---------------------------------------------------------------------------------------
2489: when s_pc_reintegrating_wait =>
2490: bit_err_disable <= '1';
2491:
2492: if (mr_command_ercrst_q = '1') then
2493: tick_state_reg <= '1';
2494: ctrl_ctr_pload_i <= '1';
2495: reinteg_ctr_clr <= '1';
2496: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2497: clr_bus_off_rst_flg <= '1';
2498: end if;
2499:
2500: ---------------------------------------------------------------------------------------
2501: -- Unit is re-integrating, waiting till re-integration counter expires!
2502: ---------------------------------------------------------------------------------------
2503: when s_pc_reintegrating =>
2504: ctrl_ctr_ena <= '1';
2505: perform_hsync <= '1';
2506: bit_err_disable <= '1';
2507:
2508: -- Restart integration upon reception of DOMINANT bit or upon synchronization edge.
2509: if (rx_data_nbs = DOMINANT or sync_edge = '1') then
2510: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2511: end if;
2512:
2513: -- When preloaded due to synchronisation edge, this is outside of sample point!
2514: if (rx_data_nbs = DOMINANT) then
2515: ctrl_ctr_pload_i <= '1';
2516: end if;
2517:
2518: if (integ_restart_edge = '1') then
2519: ctrl_ctr_pload_unaliged <= '1';
2520: end if;
2521:
2522: if (ctrl_ctr_zero = '1') then
2523: reinteg_ctr_enable <= '1';
2524: end if;
2525:
2526: if (ctrl_ctr_zero = '1' and reinteg_ctr_expired = '0') then
2527: ctrl_ctr_pload_i <= '1';
2528: ctrl_ctr_pload_val <= C_INTEGRATION_DURATION;
2529: end if;
2530:
2531: if (reinteg_ctr_expired = '1' and ctrl_ctr_zero = '1' and rx_trigger = '1') then
2532: tick_state_reg <= '1';
2533: set_idle_i <= '1';
2534: set_err_active_i <= '1';
2535: load_init_vect_i <= '1';
2536: end if;
2537:
2538: ---------------------------------------------------------------------------------------
2539: -- Active error flag.
2540: ---------------------------------------------------------------------------------------
2541: when s_pc_act_err_flag =>
2542: ctrl_ctr_ena <= '1';
2543: pc_dbg.is_err <= '1';
2544: tx_dominant <= '1';
2545: err_pos <= ERC_POS_ERR;
2546:
2547: if (ctrl_ctr_zero = '1') then
2548: tick_state_reg <= '1';
2549: ctrl_ctr_pload_i <= '1';
2550: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
2551: first_err_delim_d <= '1';
2552: end if;
2553:
2554: ---------------------------------------------------------------------------------------
2555: -- Passive error flag.
2556: ---------------------------------------------------------------------------------------
2557: when s_pc_pas_err_flag =>
2558: ctrl_ctr_ena <= '1';
2559: pc_dbg.is_err <= '1';
2560: err_pos <= ERC_POS_ERR;
2561:
2562: -- Node sending Passive error flag may receive RECESSIVE or DOMINANT, and DOMINANT
2563: -- shall not be treated as bit error!
2564: bit_err_disable <= '1';
2565:
2566: -- Reseting control counter if different bit that previous is detected. Passive
2567: -- error flag must be completed after 6 bits of equal polarity!
2568: if (rx_data_nbs_prev /= rx_data_nbs) then
2569: ctrl_ctr_pload_i <= '1';
2570: ctrl_ctr_pload_val <= C_SHORTENED_ERR_FLG_DURATION;
2571: elsif (ctrl_ctr_zero = '1') then
2572: tick_state_reg <= '1';
2573: ctrl_ctr_pload_i <= '1';
2574: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
2575: first_err_delim_d <= '1';
2576: end if;
2577:
2578: -- If dominant bit is detected, and previous error was ACK, then TEC shall be
2579: -- still incremented!
2580: if (ack_err_flag = '1' and rx_data_nbs = DOMINANT and rx_trigger = '1') then
2581: bit_err_after_ack_err <= '1';
2582: ack_err_flag_clr <= '1';
2583: end if;
2584:
2585: ---------------------------------------------------------------------------------------
2586: -- Wait till Error delimiter (detection of recessive bit)
2587: ---------------------------------------------------------------------------------------
2588: when s_pc_err_delim_wait =>
2589: pc_dbg.is_err <= '1';
2590: err_pos <= ERC_POS_ERR;
2591: ack_err_flag_clr <= '1';
2592:
2593: -- When waiting for RECESSIVE bit after Error flag, unit may receive DOMINANT and
2594: -- not interpret this as Bit error!
2595: bit_err_disable <= '1';
2596:
2597: if (ctrl_ctr_zero = '0') then
2598: ctrl_ctr_ena <= '1';
2599: else
2600: tick_state_reg <= '1';
2601: end if;
2602:
2603: if (rx_data_nbs = RECESSIVE) then
2604: tick_state_reg <= '1';
2605: ctrl_ctr_pload_i <= '1';
2606: ctrl_ctr_pload_val <= C_ERR_DELIM_DURATION;
2607: end if;
2608:
2609: -- Node received dominant bit as first bit after Error flag! This shall be treated
2610: -- as primary error
2611: if (rx_data_nbs = DOMINANT and first_err_delim_q = '1') then
2612: primary_err_i <= '1';
2613: first_err_delim_d <= '0';
2614: end if;
2615:
2616: ---------------------------------------------------------------------------------------
2617: -- 13 dominant bits (6 error flag + 7 error delimiter) has been detected (active error
2618: -- flag), or 7 has been detected (passive error flag).
2619: ---------------------------------------------------------------------------------------
2620: when s_pc_err_flag_too_long =>
2621: pc_dbg.is_err <= '1';
2622: err_pos <= ERC_POS_ERR;
2623: bit_err_disable <= '1';
2624: ctrl_ctr_ena <= '1';
2625:
2626: if (rx_data_nbs = RECESSIVE) then
2627: tick_state_reg <= '1';
2628: ctrl_ctr_pload_i <= '1';
2629: ctrl_ctr_pload_val <= C_ERR_DELIM_DURATION;
2630:
2631: -- This indicates that either 14th dominant bit was detected, or each next
2632: -- consecutive 8 DOMINANT bits were detected!
2633: elsif (ctrl_ctr_zero = '1') then
2634: tick_state_reg <= '1';
2635: ctrl_ctr_pload_i <= '1';
2636: ctrl_ctr_pload_val <= C_DOMINANT_REPEAT_DURATION;
2637: err_delim_late_i <= '1';
2638: end if;
2639:
2640: ---------------------------------------------------------------------------------------
2641: -- 13 dominant bits (6 overload flag + 7 overload delimiter) has been detected.
2642: ---------------------------------------------------------------------------------------
2643: when s_pc_ovr_flag_too_long =>
2644: pc_dbg.is_overload <= '1';
2645: err_pos <= ERC_POS_OVRL;
2646: bit_err_disable <= '1';
2647: ctrl_ctr_ena <= '1';
2648:
2649: if (rx_data_nbs = RECESSIVE) then
2650: tick_state_reg <= '1';
2651: ctrl_ctr_pload_i <= '1';
2652: ctrl_ctr_pload_val <= C_OVR_DELIM_DURATION;
2653:
2654: -- This indicates that either 14th dominant bit was detected, or each next
2655: -- consecutive 8 DOMINANT bits were detected!
2656: elsif (ctrl_ctr_zero = '1') then
2657: tick_state_reg <= '1';
2658: ctrl_ctr_pload_i <= '1';
2659: ctrl_ctr_pload_val <= C_DOMINANT_REPEAT_DURATION;
2660: err_delim_late_i <= '1';
2661: end if;
2662:
2663: ---------------------------------------------------------------------------------------
2664: -- Error delimiter
2665: ---------------------------------------------------------------------------------------
2666: when s_pc_err_delim =>
2667: pc_dbg.is_err <= '1';
2668: ctrl_ctr_ena <= '1';
2669: err_pos <= ERC_POS_ERR;
2670: bit_err_disable <= '1';
2671:
2672: if (ctrl_ctr_zero = '1') then
2673: tick_state_reg <= '1';
2674: ctrl_ctr_pload_i <= '1';
2675:
2676: if (rx_data_nbs = DOMINANT) then
2677: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2678: else
2679: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
2680: end if;
2681: elsif (rx_data_nbs = DOMINANT) then
2682: form_err_i <= '1';
2683: end if;
2684:
2685: ---------------------------------------------------------------------------------------
2686: -- Overload flag
2687: ---------------------------------------------------------------------------------------
2688: when s_pc_ovr_flag =>
2689: pc_dbg.is_overload <= '1';
2690: ctrl_ctr_ena <= '1';
2691: tx_dominant <= '1';
2692: err_pos <= ERC_POS_OVRL;
2693:
2694: if (ctrl_ctr_zero = '1') then
2695: tick_state_reg <= '1';
2696: ctrl_ctr_pload_i <= '1';
2697: ctrl_ctr_pload_val <= C_DELIM_WAIT_DURATION;
2698: end if;
2699:
2700: ---------------------------------------------------------------------------------------
2701: -- Wait till overload delimiter.
2702: ---------------------------------------------------------------------------------------
2703: when s_pc_ovr_delim_wait =>
2704: pc_dbg.is_overload <= '1';
2705: err_pos <= ERC_POS_OVRL;
2706:
2707: if (ctrl_ctr_zero = '0') then
2708: ctrl_ctr_ena <= '1';
2709: else
2710: tick_state_reg <= '1';
2711: end if;
2712:
2713: -- When waiting for RECESSIVE bit after Overload flag, unit may receive DOMINANT
2714: -- and not interpret this as Bit error!
2715: bit_err_disable <= '1';
2716:
2717: if (rx_data_nbs = RECESSIVE) then
2718: tick_state_reg <= '1';
2719: ctrl_ctr_pload_i <= '1';
2720: ctrl_ctr_pload_val <= C_OVR_DELIM_DURATION;
2721: end if;
2722:
2723: ---------------------------------------------------------------------------------------
2724: -- Overload delimiter
2725: ---------------------------------------------------------------------------------------
2726: when s_pc_ovr_delim =>
2727: ctrl_ctr_ena <= '1';
2728: pc_dbg.is_overload <= '1';
2729: err_pos <= ERC_POS_OVRL;
2730: bit_err_disable <= '1';
2731:
2732: if (ctrl_ctr_zero = '1') then
2733: tick_state_reg <= '1';
2734: ctrl_ctr_pload_i <= '1';
2735:
2736: if (rx_data_nbs = DOMINANT) then
2737: ctrl_ctr_pload_val <= C_OVR_FLG_DURATION;
2738: else
2739: ctrl_ctr_pload_val <= C_INTERMISSION_DURATION;
2740: end if;
2741: elsif (rx_data_nbs = DOMINANT) then
2742: form_err_i <= '1';
2743: end if;
2744:
2745: end case;
2746: end if;
2747:
2748: end process;
2749:
2750: -----------------------------------------------------------------------------------------------
2751: -- FSM State register
2752: -----------------------------------------------------------------------------------------------
2753: state_reg_ce <= '1' when (tick_state_reg = '1' and ctrl_signal_upd = '1')
2754: else
2755: '0';
2756:
2757: fsm_state_reg_proc : process(clk_sys, res_n)
2758: begin
2759: if (res_n = '0') then
2760: curr_state <= s_pc_off;
2761: elsif (rising_edge(clk_sys)) then
2762: if (state_reg_ce = '1') then
2763: curr_state <= next_state;
2764: end if;
2765: end if;
2766: end process;
2767:
2768: -----------------------------------------------------------------------------------------------
2769: -- Control counter is preloaded:
2770: -- 1. When core is off and becomes non-off
2771: -- 2. When preloaded by any state and RX trigger is active. This saves gating with RX Trigger
2772: -- in each FSM state!
2773: -- 3. When counter is reset during integration due to synchronisation edge. This can be
2774: -- anytime, not just in sample point!
2775: -----------------------------------------------------------------------------------------------
2776: ctrl_ctr_pload <= ctrl_ctr_pload_i when (curr_state = s_pc_off) else
2777: ctrl_ctr_pload_i when (ctrl_signal_upd = '1') else
2778: '1' when (ctrl_ctr_pload_unaliged = '1') else
2779: '0';
2780:
2781: -----------------------------------------------------------------------------------------------
2782: -- Registering control commands to RX Buffer due to following reasons
2783: -- 1. In last bit of DLC, DLC is not yet sampled in RX Shift register, thus we need to delay
2784: -- storing of metadata word by one clock cycle!
2785: -- 2. Break possible long combinational paths between RX Buffer and Protocol control FSM!
2786: -----------------------------------------------------------------------------------------------
2787: rx_buf_cmds_proc : process(clk_sys, res_n)
2788: begin
2789: if (res_n = '0') then
2790: store_metadata <= '0';
2791: store_data <= '0';
2792: rec_valid <= '0';
2793: rec_abort <= '0';
2794: elsif (rising_edge(clk_sys)) then
2795:
2796: -- Frame is stored to RX Buffer when unit is either receiver or loopback mode is
2797: -- enabled. Each command is active only for one clock cycle!
2798: if ((is_receiver = '1' or mr_settings_ilbp = '1') and (rx_trigger = '1'))
2799: then
2800: store_metadata <= store_metadata_d;
2801: store_data <= store_data_d;
2802: rec_valid <= rec_valid_d;
2803: else
2804: store_metadata <= '0';
2805: store_data <= '0';
2806: rec_valid <= '0';
2807: end if;
2808:
2809: rec_abort <= err_frm_req;
2810:
2811: end if;
2812: end process;
2813:
2814: ctrl_signal_upd <= '1' when (rx_trigger = '1' or err_frm_req = '1')
2815: else
2816: '0';
2817:
2818: rec_ivld_d <= rec_ivld_i when (rx_trigger = '1')
2819: else
2820: rec_ivld_q;
2821:
2822: -----------------------------------------------------------------------------------------------
2823: -- Register Loopback frame flag and Identifier valid flag
2824: -----------------------------------------------------------------------------------------------
2825: rex_lbpc_reg_proc : process (clk_sys, res_n)
2826: begin
2827: if (res_n = '0') then
2828: rec_lbpf_q <= '0';
2829: rec_ivld_q <= '0';
2830: elsif (rising_edge(clk_sys)) then
2831: rec_lbpf_q <= rec_lbpf_d;
2832: rec_ivld_q <= rec_ivld_d;
2833: end if;
2834: end process;
2835:
2836: -----------------------------------------------------------------------------------------------
2837: -- TXT Buffer HW commands pipeline
2838: -----------------------------------------------------------------------------------------------
2839: txtb_hw_cmd_proc : process(clk_sys, res_n)
2840: begin
2841: if (res_n = '0') then
2842: txtb_hw_cmd_q.lock <= '0';
2843: txtb_hw_cmd_q.valid <= '0';
2844: txtb_hw_cmd_q.err <= '0';
2845: txtb_hw_cmd_q.arbl <= '0';
2846: txtb_hw_cmd_q.failed <= '0';
2847: elsif (rising_edge(clk_sys)) then
2848: if (ctrl_signal_upd = '1') then
2849: txtb_hw_cmd_q <= txtb_hw_cmd_d;
2850: else
2851: txtb_hw_cmd_q <= ('0', '0', '0', '0', '0');
2852: end if;
2853: end if;
2854: end process;
2855:
2856: -----------------------------------------------------------------------------------------------
2857: -- RX Shift register commands gating. Each command can be active only in sample point
2858: -- (rx_trigger = '1')!
2859: -----------------------------------------------------------------------------------------------
2860: rx_store_base_id <= rx_store_base_id_i and rx_trigger;
2861: rx_store_ext_id <= rx_store_ext_id_i and rx_trigger;
2862: rx_store_ide <= rx_store_ide_i and rx_trigger;
2863: rx_store_rtr <= rx_store_rtr_i and rx_trigger;
2864: rx_store_edl <= rx_store_edl_i and rx_trigger;
2865: rx_store_dlc <= rx_store_dlc_i and rx_trigger;
2866: rx_store_esi <= rx_store_esi_i and rx_trigger;
2867: rx_store_brs <= rx_store_brs_i and rx_trigger;
2868: rx_store_stuff_count <= rx_store_stuff_count_i and rx_trigger;
2869:
2870: -----------------------------------------------------------------------------------------------
2871: -- TX Shift register commands gating. Each command can be active only in sample point
2872: -- (rx_trigger = '1')!
2873: -----------------------------------------------------------------------------------------------
2874: tx_load_base_id <= tx_load_base_id_i and rx_trigger;
2875: tx_load_ext_id <= tx_load_ext_id_i and rx_trigger;
2876: tx_load_dlc <= tx_load_dlc_i and rx_trigger;
2877: tx_load_data_word <= tx_load_data_word_i and rx_trigger;
2878: tx_load_stuff_count <= tx_load_stuff_count_i and rx_trigger;
2879: tx_load_crc <= tx_load_crc_i and rx_trigger;
2880:
2881: -----------------------------------------------------------------------------------------------
2882: -- TX Shift register is enabled only when the unit is transmitter!
2883: -----------------------------------------------------------------------------------------------
2884: tx_shift_ena <= '1' when (tx_shift_ena_i = '1' and is_transmitter = '1')
2885: else
2886: '0';
2887:
2888: -----------------------------------------------------------------------------------------------
2889: -- Error signalling gating. Each command can be active only in sample point (rx_trigger = '1')!
2890: -----------------------------------------------------------------------------------------------
2891: form_err <= form_err_i and rx_trigger;
2892: ack_err <= ack_err_i and rx_trigger;
2893: crc_err <= crc_err_i and rx_trigger;
2894: bit_err_arb <= bit_err_arb_i and rx_trigger;
2895:
2896: -- decrement_rec is special. It is only set upon sampling dominant bit in ACK field.
2897: -- Thus previous bit must have been recessive (CRC Delimiter) - otherwise there would be
2898: -- error frame.
2899: -- Since Protocol Control FSM processes rx_trigger wbs, the rx_data_nbs must have changed
2900: -- to dominant in the very same cycle as the rx_trigger used for gating.
2901: -- See no_decrement_rec_without_rx_trigger_asrt below which checks for this case
2902: decrement_rec <= decrement_rec_i;
2903:
2904: -----------------------------------------------------------------------------------------------
2905: -- Switching of Bit-rate
2906: -----------------------------------------------------------------------------------------------
2907: switch_to_ssp <= '1' when (sp_control_switch_data = '1' and is_transmitter = '1' and
2908: mr_ssp_cfg_ssp_src /= SSP_SRC_NO_SSP)
2909: else
2910: '0';
2911:
2912: sp_control_d <= NOMINAL_SAMPLE when (sp_control_switch_nominal = '1')
2913: else
2914: SECONDARY_SAMPLE when (switch_to_ssp = '1')
2915: else
2916: DATA_SAMPLE when (sp_control_switch_data = '1')
2917: else
2918: sp_control_q_i;
2919:
2920: sp_control_ce <= '1' when (sp_control_switch_nominal = '1') else
2921: '1' when (sp_control_switch_data = '1') else
2922: '0';
2923:
2924: sp_control_reg_proc : process(clk_sys, res_n)
2925: begin
2926: if (res_n = '0') then
2927: sp_control_q_i <= NOMINAL_SAMPLE;
2928: elsif (rising_edge(clk_sys)) then
2929: if (sp_control_ce = '1') then
2930: sp_control_q_i <= sp_control_d;
2931: end if;
2932: end if;
2933: end process;
2934:
2935: sp_control <= sp_control_d when (br_shifted_i = '1') else
2936: sp_control_q_i;
2937:
2938: -----------------------------------------------------------------------------------------------
2939: -- Indicates that Active Error or Overload flag is being transmitted! Can't be part of current
2940: -- state, since it must be valid also during error condition to distiguish error during error
2941: -- flag!
2942: -----------------------------------------------------------------------------------------------
2943: act_err_ovr_flag <= '1' when (curr_state = s_pc_act_err_flag) else
2944: '1' when (curr_state = s_pc_ovr_flag) else
2945: '0';
2946:
2947: first_err_delim_flag_reg : process(clk_sys, res_n)
2948: begin
2949: if (res_n = '0') then
2950: first_err_delim_q <= '0';
2951: elsif (rising_edge(clk_sys)) then
2952: if (rx_trigger = '1') then
2953: first_err_delim_q <= first_err_delim_d;
2954: end if;
2955: end if;
2956: end process;
2957:
2958: -----------------------------------------------------------------------------------------------
2959: -- Detection of primary error and late error delimiter must be active only for one clock cycle
2960: -- in Sample point (rx_trigger)!
2961: -----------------------------------------------------------------------------------------------
2962: primary_err <= '1' when (primary_err_i = '1' and rx_trigger = '1')
2963: else
2964: '0';
2965:
2966: err_delim_late <= '1' when (err_delim_late_i = '1' and rx_trigger = '1')
2967: else
2968: '0';
2969:
2970: set_err_active <= '1' when (set_err_active_i = '1' and rx_trigger = '1')
2971: else
2972: '0';
2973:
2974: rx_clear <= '1' when (rx_clear_i = '1' and rx_trigger = '1')
2975: else
2976: '0';
2977:
2978: -----------------------------------------------------------------------------------------------
2979: -- Bit error is disabled:
2980: -- 1. In arbitration field, there it is detected extra since only transmitting dominant and
2981: -- receiving recessive is trated as bit error.
2982: -- 2. For receiver during control, data, CRC fields!
2983: -----------------------------------------------------------------------------------------------
2984: bit_err_enable <= '0' when (bit_err_disable = '1') else
2985: '0' when (bit_err_disable_receiver = '1' and is_receiver = '1') else
2986: '1';
2987:
2988: -----------------------------------------------------------------------------------------------
2989: -- Retransmitt counter is incremented when error frame is detected, or when arbitration loss
2990: -- occurs! Active only when:
2991: -- 1. Counter is not cleared (clear has priority)
2992: -- 2. Retransmitt limitation is enabled. Not counting when disabled.
2993: -- 3. Unit is reciever. Only transmitter counts re-transmissions!
2994: -----------------------------------------------------------------------------------------------
2995: retr_ctr_add_i <= '0' when (retr_ctr_clear_i = '1' or mr_settings_rtrle = '0'
2996: or is_receiver = '1' or retr_ctr_add_block = '1') else
2997: '1' when (arbitration_lost_i = '1' and rx_trigger = '1') else
2998: '1' when (err_frm_req = '1') else
2999: '0';
3000:
3001: -----------------------------------------------------------------------------------------------
3002: -- Retransmitt counter is cleared when:
3003: -- 1. Transmission is valid.
3004: -- 2. Transmission failed (TXT Buffer is moving to TX Error)!
3005: -----------------------------------------------------------------------------------------------
3006: retr_ctr_clear_i <= '1' when (txtb_hw_cmd_d.valid = '1' and rx_trigger = '1') else
3007: '1' when (txtb_hw_cmd_d.failed = '1') else
3008: '0';
3009:
3010: -----------------------------------------------------------------------------------------------
3011: -- Retransmitt counter must be modified only once if multiple Error frames are requested during
3012: -- single frame. This flag is set upon first Error frame, and it blocks increments upon next
3013: -- error frames!
3014: -----------------------------------------------------------------------------------------------
3015: retr_ctr_add_block_proc : process(clk_sys, res_n)
3016: begin
3017: if (res_n = '0') then
3018: retr_ctr_add_block <= '0';
3019: elsif (rising_edge(clk_sys)) then
3020: if (retr_ctr_add_i = '1') then
3021: retr_ctr_add_block <= '1';
3022: elsif (retr_ctr_add_block_clr = '1') then
3023: retr_ctr_add_block <= '0';
3024: end if;
3025: end if;
3026: end process;
3027:
3028:
3029: -- Start of frame pulse is active in Sample point of SOF only!
3030: sof_pulse <= '1' when (sof_pulse_i = '1' and rx_trigger = '1')
3031: else
3032: '0';
3033:
3034: -----------------------------------------------------------------------------------------------
3035: -- Complementary counter counts only in Sample point once per bit time.
3036: -----------------------------------------------------------------------------------------------
3037: compl_ctr_ena <= '1' when (compl_ctr_ena_i = '1' and rx_trigger = '1')
3038: else
3039: '0';
3040:
3041: -----------------------------------------------------------------------------------------------
3042: -- Operation control commands active in Sample point only!
3043: -----------------------------------------------------------------------------------------------
3044: set_transmitter <= '1' when (set_transmitter_i = '1' and rx_trigger = '1')
3045: else
3046: '0';
3047:
3048: -- No need to gate "set_receiver_i" by rx_trigger since this is always set in frame fields
3049: -- where previous bits are recessive and dominant is sampled. Since Protocol control operates
3050: -- with RX trigger one cycle after RX data are destuffed, it must be first cycle where such
3051: -- condition is true. Thus gating by rx_data_nbs=DOMINANT is sufficient, and in the cycle
3052: -- where this signal is set, the Protocol control FSM changes state. Thus it may never happed
3053: -- that the "set_receiver" would hold for multiple cycles.
3054: set_receiver <= '1' when (set_receiver_i = '1')
3055: else
3056: '0';
3057:
3058: -----------------------------------------------------------------------------------------------
3059: -- Idle must be un-gated also by Error frame request, since in ROM mode it is possible that
3060: -- upon any kind of error, unit should go to integrating and therefore stop being transmitter
3061: -- or receiver!
3062: -----------------------------------------------------------------------------------------------
3063: set_idle <= '1' when (set_idle_i = '1' and (rx_trigger = '1' or err_frm_req = '1'))
3064: else
3065: '0';
3066:
3067: -----------------------------------------------------------------------------------------------
3068: -- CRC select source for calculation:
3069: -- 1. When speculative enable is selected, always use RX Data. This is in idle/intermission/
3070: -- suspend when dominant is sampled and cosidered as SOF.
3071: -- 2. When we are in arbitration, always use idle. This is to make sure that transmitting
3072: -- recessive and receiving dominant (loosing arbitration) will calculate data from
3073: -- DOMINANT value
3074: -- 3. In other cases Transmitter uses TX Data, Receiver uses RX Data.
3075: -----------------------------------------------------------------------------------------------
3076: crc_calc_from_rx <= '1' when (crc_spec_enable_i = '1') else
3077: '1' when (is_arbitration_i = '1') else
3078: '1' when (is_receiver = '1') else
3079: '0';
3080:
3081: load_init_vect <= '1' when (load_init_vect_i = '1' and rx_trigger = '1')
3082: else
3083: '0';
3084:
3085: -----------------------------------------------------------------------------------------------
3086: -- Bit Stuffing enable
3087: -----------------------------------------------------------------------------------------------
3088: stuff_ena_reg_proc : process(clk_sys, res_n)
3089: begin
3090: if (res_n = '0') then
3091: stuff_enable <= '0';
3092: elsif (rising_edge(clk_sys)) then
3093: if (ctrl_signal_upd = '1') then
3094: if (stuff_enable_set = '1') then
3095: stuff_enable <= '1';
3096: elsif (stuff_enable_clear = '1') then
3097: stuff_enable <= '0';
3098: end if;
3099: end if;
3100: end if;
3101: end process;
3102:
3103: -----------------------------------------------------------------------------------------------
3104: -- Bit DeStuffing enable, Stuff Error
3105: -----------------------------------------------------------------------------------------------
3106: destuff_ena_reg_proc : process(clk_sys, res_n)
3107: begin
3108: if (res_n = '0') then
3109: destuff_enable <= '0';
3110: elsif (rising_edge(clk_sys)) then
3111: if (ctrl_signal_upd = '1') then
3112: if (destuff_enable_set = '1') then
3113: destuff_enable <= '1';
3114: elsif (destuff_enable_clear = '1') then
3115: destuff_enable <= '0';
3116: end if;
3117: end if;
3118: end if;
3119: end process;
3120:
3121:
3122: -----------------------------------------------------------------------------------------------
3123: -- Synchronisation type
3124: -----------------------------------------------------------------------------------------------
3125: sync_control_d <= NO_SYNC when ((sp_control_switch_data = '1' and is_transmitter = '1') or
3126: sp_control_q_i = SECONDARY_SAMPLE or
3127: (sp_control_q_i = DATA_SAMPLE and is_transmitter = '1'))
3128: else
3129: HARD_SYNC when (perform_hsync = '1')
3130: else
3131: RE_SYNC;
3132:
3133: sync_control_reg_proc : process(clk_sys, res_n)
3134: begin
3135: if (res_n = '0') then
3136: sync_control_q <= HARD_SYNC;
3137: elsif (rising_edge(clk_sys)) then
3138: sync_control_q <= sync_control_d;
3139: end if;
3140: end process;
3141:
3142: -----------------------------------------------------------------------------------------------
3143: -- TXT Buffer pointer registering
3144: -----------------------------------------------------------------------------------------------
3145: txtb_ptr_reg_proc : process(clk_sys, res_n)
3146: begin
3147: if (res_n = '0') then
3148: txtb_ptr_q <= 0;
3149: elsif (rising_edge(clk_sys)) then
3150: if (txtb_clk_en_d = '1') then
3151: txtb_ptr_q <= txtb_ptr_d;
3152: end if;
3153: end if;
3154: end process;
3155:
3156: -- Enable memory only when pointer changes. This allows clocking the memory only when new read
3157: -- data are to be read!
3158: txtb_clk_en_d <= '1' when (txtb_ptr_q /= txtb_ptr_d and txtb_gate_mem_read = '0')
3159: else
3160: '0';
3161:
3162: -----------------------------------------------------------------------------------------------
3163: -- Register clock enable! Data need to be loaded from TXT Buffer RAM after address has changed!
3164: -----------------------------------------------------------------------------------------------
3165: txtb_ce_reg_proc : process(clk_sys, res_n)
3166: begin
3167: if (res_n = '0') then
3168: txtb_clk_en_q <= '0';
3169: elsif (rising_edge(clk_sys)) then
3170: txtb_clk_en_q <= txtb_clk_en_d;
3171: end if;
3172: end process;
3173:
3174: -----------------------------------------------------------------------------------------------
3175: -- Frame transmission (transmitter) started without SOF!
3176: -----------------------------------------------------------------------------------------------
3177: tx_frame_no_sof_proc : process(clk_sys, res_n)
3178: begin
3179: if (res_n = '0') then
3180: tx_frame_no_sof_q <= '0';
3181: elsif (rising_edge(clk_sys)) then
3182: if (rx_trigger = '1') then
3183: tx_frame_no_sof_q <= tx_frame_no_sof_d;
3184: end if;
3185: end if;
3186: end process;
3187:
3188: -----------------------------------------------------------------------------------------------
3189: -- Registering value from previous bit of CAN_RX signal
3190: -----------------------------------------------------------------------------------------------
3191: prev_rx_data_reg_proc : process(res_n, clk_sys)
3192: begin
3193: if (res_n = '0') then
3194: rx_data_nbs_prev <= RECESSIVE;
3195: elsif (rising_edge(clk_sys)) then
3196: if (rx_trigger = '1') then
3197: rx_data_nbs_prev <= rx_data_nbs;
3198: end if;
3199: end if;
3200: end process;
3201:
3202: -----------------------------------------------------------------------------------------------
3203: -- Remembering ACK error. Needed by transmitter sending passive error frame due to ACK error.
3204: -----------------------------------------------------------------------------------------------
3205: ack_err_flag_proc : process(clk_sys, res_n)
3206: begin
3207: if (res_n = '0') then
3208: ack_err_flag <= '0';
3209: elsif (rising_edge(clk_sys)) then
3210: if (ack_err_i = '1' and rx_trigger = '1') then
3211: ack_err_flag <= '1';
3212: elsif (ack_err_flag_clr = '1') then
3213: ack_err_flag <= '0';
3214: end if;
3215: end if;
3216: end process;
3217:
3218: -----------------------------------------------------------------------------------------------
3219: -- Protocol exception status
3220: -----------------------------------------------------------------------------------------------
3221: pexs_proc : process(clk_sys, res_n)
3222: begin
3223: if (res_n = '0') then
3224: mr_status_pexs <= '0';
3225: elsif (rising_edge(clk_sys)) then
3226: if (pexs_set = '1') then
3227: mr_status_pexs <= '1';
3228: elsif (mr_command_cpexs = '1') then
3229: mr_status_pexs <= '0';
3230: end if;
3231: end if;
3232: end process;
3233:
3234: -----------------------------------------------------------------------------------------------
3235: -- Internal signals to output propagation
3236: -----------------------------------------------------------------------------------------------
3237: crc_src <= crc_src_i;
3238: txtb_hw_cmd <= txtb_hw_cmd_q;
3239: tran_valid <= txtb_hw_cmd_q.valid;
3240: sync_control <= sync_control_q;
3241: txtb_ptr <= txtb_ptr_q;
3242: br_shifted <= br_shifted_i;
3243: sp_control_q <= sp_control_q_i;
3244: crc_spec_enable <= crc_spec_enable_i;
3245: retr_ctr_clear <= retr_ctr_clear_i;
3246: arbitration_lost <= arbitration_lost_i;
3247: retr_ctr_add <= retr_ctr_add_i;
3248: tx_frame_no_sof <= tx_frame_no_sof_q;
3249: txtb_clk_en <= txtb_clk_en_q;
3250: pc_dbg.is_arbitration <= is_arbitration_i;
3251: rec_lbpf <= rec_lbpf_q;
3252: rec_ivld <= rec_ivld_q;
3253:
3254:
3255: -----------------------------------------------------------------------------------------------
3256: -----------------------------------------------------------------------------------------------
3257: -- Assertions
3258: -----------------------------------------------------------------------------------------------
3259: -----------------------------------------------------------------------------------------------
3260:
3261: -- psl default clock is rising_edge(clk_sys);
3262:
3263: -- psl no_simul_crc_17_crc_21_asrt : assert never
3264: -- (crc_use_17 = '1' and crc_use_21 = '1')
3265: -- report "Can't use simultaneously CRC 17 and CRC 21";
3266:
3267: -- psl no_simul_rx_trigger_err_req_asrt : assert never
3268: -- (rx_trigger = '1' and err_frm_req = '1')
3269: -- report "RX Trigger and Error frame request can't be active at once since they should occur in different pipeline stages!";
3270:
3271: -- psl no_simul_rx_rtr_and_fd_frame_asrt : assert never
3272: -- (rec_is_rtr = RTR_FRAME and rec_frame_type = FD_CAN)
3273: -- report "RTR and FDF can't be received simultaneously!";
3274:
3275:
3276: -- Error frame requests can't arrive during following frame fields:
3277: -- OFF, Integrating, reintegrating, Idle, Intermission (dominant bit
3278: -- is interpreted as Overload or SOF of new frame), Suspend
3279: -- (dominant bit is new frame), Error delimiter wait (Accepts
3280: -- both dominant and recessive and waits for recessive)
3281:
3282: -- psl no_err_frm_req_in_off : assert never
3283: -- (err_frm_req = '1') and
3284: -- (curr_state = s_pc_off or
3285: -- curr_state = s_pc_idle or curr_state = s_pc_intermission or
3286: -- curr_state = s_pc_suspend or curr_state = s_pc_reintegrating)
3287: -- report "Error frame request in invalid Protocol control field!";
3288:
3289: -- psl no_secondary_sample_receiver : assert never
3290: -- (sp_control_q_i = SECONDARY_SAMPLE) and (is_receiver = '1')
3291: -- report "Receiver shall never use secondary sample point!";
3292:
3293: -- psl no_sof_receiver : assert never
3294: -- (curr_state = s_pc_sof and is_receiver = '1')
3295: -- report "SOF state shall never be entered when receiver!";
3296:
3297: -- psl no_err_ovr_in_rom_mode : assert never
3298: -- (curr_state = s_pc_act_err_flag or curr_state = s_pc_pas_err_flag or
3299: -- curr_state = s_pc_err_delim or curr_state = s_pc_ovr_delim)
3300: -- and (mr_mode_rom = ROM_ENABLED)
3301: -- report "Error or Overload frames shall never be transmitted in ROM mode!";
3302:
3303: -- psl no_tx_in_rom_mode : assert never
3304: -- (mr_mode_rom = '1' and is_transmitter = '1')
3305: -- report "Device shall not transmit frames in ROM mode!";
3306:
3307: -- psl no_stuff_destuff_in_eof : assert never
3308: -- (stuff_enable = '1' or destuff_enable = '1') and
3309: -- (curr_state = s_pc_eof)
3310: -- report "Bit stuffing destuffin should be never enabled during EOF!";
3311:
3312: -- psl no_decrement_rec_without_rx_trigger_asrt : assert never
3313: -- (decrement_rec_i = '1' and rx_trigger = '0')
3314: -- report "decrement_rec_i shall never be 1 without rx_trigger being 1!";
3315:
3316:
3317: end architecture;