File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/can_crc.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- CAN CRC
71: --
72: -- Sub-modules:
73: -- CRC 15 - Calculated from data without bit stuffing.
74: -- CRC 17 - Calculated from data with bit stuffing.
75: -- CRC 21 - Calculated from data with bit stuffing.
76: --
77: -- Purpose:
78: -- Calculates crc sequences for CAN frame. Transmitter calculates CRC from
79: -- transmitted serial sequence. Receiver calculates data from RX sequence.
80: -- Final CRC is multiplexed on output. If node loses arbitration, source of
81: -- CRC calculation is changed.
82: -- Pipeline stages in which input is processed:
83: -- CRC 15 - Process (RX) / Stuff (TX)
84: -- CRC 17 - Process (RX) / Stuff + 1 clock cycle (TX)
85: -- CRC 21 - Process (RX) / Stuff + 1 clock cycle (TX)
86: --------------------------------------------------------------------------------
87:
88: Library ieee;
89: use ieee.std_logic_1164.all;
90: use ieee.numeric_std.ALL;
91:
92: Library ctu_can_fd_rtl;
93: use ctu_can_fd_rtl.can_constants_pkg.all;
94: use ctu_can_fd_rtl.can_types_pkg.all;
95:
96: use ctu_can_fd_rtl.CAN_FD_register_map.all;
97: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
98:
99: entity can_crc is
100: generic (
101: -- CRC 15 polynomial
102: G_CRC15_POL : std_logic_vector(15 downto 0) := x"C599";
103:
104: -- CRC 17 polynomial
105: G_CRC17_POL : std_logic_vector(19 downto 0) := x"3685B";
106:
107: -- CRC 15 polynomial
108: G_CRC21_POL : std_logic_vector(23 downto 0) := x"302899"
109: );
110: port (
111: -------------------------------------------------------------------------------------------
112: -- System clock and Asynchronous Reset
113: -------------------------------------------------------------------------------------------
114: clk_sys : in std_logic;
115: res_n : in std_logic;
116:
117: -------------------------------------------------------------------------------------------
118: -- Memory registers interface
119: -------------------------------------------------------------------------------------------
120: mr_settings_nisofd : in std_logic;
121:
122: -------------------------------------------------------------------------------------------
123: -- Data inputs for CRC calculation
124: -------------------------------------------------------------------------------------------
125: -- TX Data with Bit Stuffing
126: data_tx_wbs : in std_logic;
127:
128: -- TX Data without Bit Stuffing
129: data_tx_nbs : in std_logic;
130:
131: -- RX Data with Bit Stuffing
132: data_rx_wbs : in std_logic;
133:
134: -- RX Data without Bit Stuffing
135: data_rx_nbs : in std_logic;
136:
137: -------------------------------------------------------------------------------------------
138: -- Trigger signals to process the data on each CRC input.
139: -------------------------------------------------------------------------------------------
140: -- Trigger for TX Data with Bit Stuffing
141: trig_tx_wbs : in std_logic;
142:
143: -- Trigger for TX Data without Bit Stuffing
144: trig_tx_nbs : in std_logic;
145:
146: -- Trigger for RX Data with Bit Stuffing
147: trig_rx_wbs : in std_logic;
148:
149: -- Trigger for RX Data without Bit Stuffing
150: trig_rx_nbs : in std_logic;
151:
152: -------------------------------------------------------------------------------------------
153: -- Control signals
154: -------------------------------------------------------------------------------------------
155: -- Enable for all CRC circuits.
156: crc_enable : in std_logic;
157:
158: -- CRC calculation - speculative enable
159: crc_spec_enable : in std_logic;
160:
161: -- Use RX Data for CRC calculation
162: crc_calc_from_rx : in std_logic;
163:
164: -- Load CRC Initialization vector
165: load_init_vect : in std_logic;
166:
167: -------------------------------------------------------------------------------------------
168: -- CRC Outputs
169: -------------------------------------------------------------------------------------------
170: crc_15 : out std_logic_vector(14 downto 0);
171: crc_17 : out std_logic_vector(16 downto 0);
172: crc_21 : out std_logic_vector(20 downto 0)
173: );
174: end entity;
175:
176: architecture rtl of can_crc is
177:
178: -- Initialization vectors
179: signal init_vect_msb_17 : std_logic;
180: signal init_vect_msb_21 : std_logic;
181:
182: -------------------------------------------------------------------------------------------
183: -- Immediate outputs of CRC circuits
184: -------------------------------------------------------------------------------------------
185:
186: -- Data inputs to CRC 17 and CRC 21
187: signal crc_17_21_data_in : std_logic;
188:
189: -- Triggers for CRC 17 and 21
190: signal crc_17_21_trigger : std_logic;
191:
192: -- Data inputs to CRC 15
193: signal crc_15_data_in : std_logic;
194:
195: -- Triggers for CRC 15
196: signal crc_15_trigger : std_logic;
197:
198: -- Internal enable signals
199: signal crc_ena_15 : std_logic;
200: signal crc_ena_17_21 : std_logic;
201:
202: begin
203:
204: -----------------------------------------------------------------------------------------------
205: -- For CRC 17 and 21, init vector MSB depends on ISO/NON-ISO type:
206: -- ISO - Highest bit 1
207: -- NON-ISO - All zeroes
208: -----------------------------------------------------------------------------------------------
209: init_vect_msb_17 <= '1' when (mr_settings_nisofd = ISO_FD)
210: else
211: '0';
212:
213: init_vect_msb_21 <= '1' when (mr_settings_nisofd = ISO_FD)
214: else
215: '0';
216:
217: -----------------------------------------------------------------------------------------------
218: -- Muxes for CRC 17,21. For Receiver choose crc from RX Stream, for Transmitter use CRC from
219: -- TX Stream.
220: -----------------------------------------------------------------------------------------------
221: crc_17_21_data_in <= data_rx_wbs when (crc_calc_from_rx = '1')
222: else
223: data_tx_wbs;
224:
225: crc_17_21_trigger <= trig_rx_wbs when (crc_calc_from_rx = '1')
226: else
227: trig_tx_wbs;
228:
229: -----------------------------------------------------------------------------------------------
230: -- Muxes for CRC 15. For Receiver choose crc from RX Stream, for Transmitter use CRC from
231: -- TX Stream.
232: -----------------------------------------------------------------------------------------------
233: crc_15_data_in <= data_rx_nbs when (crc_calc_from_rx = '1')
234: else
235: data_tx_nbs;
236:
237: crc_15_trigger <= trig_rx_nbs when (crc_calc_from_rx = '1')
238: else
239: trig_tx_nbs;
240:
241: -----------------------------------------------------------------------------------------------
242: -- CRC circuits calculate data upon trigger when enabled by one of two enable signals:
243: -- 1 Regular - CRC processes data regardless of data value.
244: -- 2. Speculative - Processes data value only if it is DOMINANT! This corresponds to processing
245: -- DOMINANT bit in IDLE, Suspend or Intermission and considering this bit as SOF! This bit
246: -- must be included in CRC calculation, but only when it is DOMINANT!
247: -----------------------------------------------------------------------------------------------
248: crc_ena_15 <= '1' when (crc_enable = '1')
249: else
250: '1' when (crc_spec_enable = '1' and crc_15_data_in = DOMINANT)
251: else
252: '0';
253:
254: crc_ena_17_21 <= '1' when (crc_enable = '1')
255: else
256: '1' when (crc_spec_enable = '1' and crc_17_21_data_in = DOMINANT)
257: else
258: '0';
259:
260: -----------------------------------------------------------------------------------------------
261: -- CRC 15 (from RX Data, no Bit Stuffing)
262: -----------------------------------------------------------------------------------------------
263: crc_calc_15_inst : entity ctu_can_fd_rtl.crc_calc
264: generic map (
265: G_CRC_WIDTH => 15,
266: G_POLYNOMIAL => G_CRC15_POL
267: )
268: port map (
269: res_n => res_n, -- IN
270: clk_sys => clk_sys, -- IN
271:
272: data_in => crc_15_data_in, -- IN
273: trig => crc_15_trigger, -- IN
274: enable => crc_ena_15, -- IN
275: init_vect_msb => '0', -- IN
276: load_init_vect => load_init_vect, -- IN
277:
278: crc => crc_15 -- OUT
279: );
280:
281: -----------------------------------------------------------------------------------------------
282: -- CRC 17 (from TX or RX Data, with Bit Stuffing)
283: -----------------------------------------------------------------------------------------------
284: crc_calc_17_rx_inst : entity ctu_can_fd_rtl.crc_calc
285: generic map(
286: G_CRC_WIDTH => 17,
287: G_POLYNOMIAL => G_CRC17_POL
288: )
289: port map(
290: res_n => res_n, -- IN
291: clk_sys => clk_sys, -- IN
292:
293: data_in => crc_17_21_data_in, -- IN
294: trig => crc_17_21_trigger, -- IN
295: enable => crc_ena_17_21, -- IN
296: init_vect_msb => init_vect_msb_17, -- IN
297: load_init_vect => load_init_vect, -- IN
298:
299: crc => crc_17 -- OUT
300: );
301:
302:
303: -----------------------------------------------------------------------------------------------
304: -- CRC 21 (from TX or RX Data, with Bit Stuffing)
305: -----------------------------------------------------------------------------------------------
306: crc_calc_21_rx_inst : entity ctu_can_fd_rtl.crc_calc
307: generic map(
308: G_CRC_WIDTH => 21,
309: G_POLYNOMIAL => G_CRC21_POL
310: )
311: port map(
312: res_n => res_n, -- IN
313: clk_sys => clk_sys, -- IN
314:
315: data_in => crc_17_21_data_in, -- IN
316: trig => crc_17_21_trigger, -- IN
317: enable => crc_ena_17_21, -- IN
318: init_vect_msb => init_vect_msb_21, -- IN
319: load_init_vect => load_init_vect, -- IN
320:
321: crc => crc_21 -- OUT
322: );
323:
324: end architecture;