File: /__w/ctu-can-regression/ctu-can-regression/src/can_core/rx_shift_reg.vhd
0: --------------------------------------------------------------------------------
1: --
2: -- CTU CAN FD IP Core
3: -- Copyright (C) 2021-2023 Ondrej Ille
4: -- Copyright (C) 2023- Logic Design Services Ltd.s
5: --
6: -- Permission is hereby granted, free of charge, to any person obtaining a copy
7: -- of this VHDL component and associated documentation files (the "Component"),
8: -- to use, copy, modify, merge, publish, distribute the Component for
9: -- non-commercial purposes. Using the Component for commercial purposes is
10: -- forbidden unless previously agreed with Copyright holder.
11: --
12: -- The above copyright notice and this permission notice shall be included in
13: -- all copies or substantial portions of the Component.
14: --
15: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
18: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
21: -- IN THE COMPONENT.
22: --
23: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
24: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
25: -- protocol license from Bosch.
26: --
27: -- -------------------------------------------------------------------------------
28: --
29: -- CTU CAN FD IP Core
30: -- Copyright (C) 2015-2020 MIT License
31: --
32: -- Authors:
33: -- Ondrej Ille <ondrej.ille@gmail.com>
34: -- Martin Jerabek <martin.jerabek01@gmail.com>
35: --
36: -- Project advisors:
37: -- Jiri Novak <jnovak@fel.cvut.cz>
38: -- Pavel Pisa <pisa@cmp.felk.cvut.cz>
39: --
40: -- Department of Measurement (http://meas.fel.cvut.cz/)
41: -- Faculty of Electrical Engineering (http://www.fel.cvut.cz)
42: -- Czech Technical University (http://www.cvut.cz/)
43: --
44: -- Permission is hereby granted, free of charge, to any person obtaining a copy
45: -- of this VHDL component and associated documentation files (the "Component"),
46: -- to deal in the Component without restriction, including without limitation
47: -- the rights to use, copy, modify, merge, publish, distribute, sublicense,
48: -- and/or sell copies of the Component, and to permit persons to whom the
49: -- Component is furnished to do so, subject to the following conditions:
50: --
51: -- The above copyright notice and this permission notice shall be included in
52: -- all copies or substantial portions of the Component.
53: --
54: -- THE COMPONENT IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
55: -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
56: -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
57: -- AUTHORS OR COPYRIGHTHOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
58: -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
59: -- FROM, OUT OF OR IN CONNECTION WITH THE COMPONENT OR THE USE OR OTHER DEALINGS
60: -- IN THE COMPONENT.
61: --
62: -- The CAN protocol is developed by Robert Bosch GmbH and protected by patents.
63: -- Anybody who wants to implement this IP core on silicon has to obtain a CAN
64: -- protocol license from Bosch.
65: --
66: --------------------------------------------------------------------------------
67:
68: --------------------------------------------------------------------------------
69: -- Module:
70: -- RX Shift register.
71: --
72: -- Purpose:
73: -- Implements 32-bits shift register for reception of CAN serial data stream.
74: -- Receives CAN ID (Base, Extended), DLC, Data, Stuff count and CRC.
75: -- Controlled by Protocol control FSM, stored sequences are stored into capture
76: -- registers (CAN IDs, DLC, flags like RTR, BRS etc...), or RX Buffer FIFO
77: -- directly. Operates in Linear mode or Byte mode. Byte mode is used for
78: -- reception of Data field. Linear mode is used in all other multi-bit fields.
79: -- RX Shift register is shifted in "Process" pipeline stage.
80: --------------------------------------------------------------------------------
81:
82: Library ieee;
83: use ieee.std_logic_1164.all;
84: use ieee.numeric_std.ALL;
85:
86: Library ctu_can_fd_rtl;
87: use ctu_can_fd_rtl.can_constants_pkg.all;
88: use ctu_can_fd_rtl.can_types_pkg.all;
89:
90: use ctu_can_fd_rtl.CAN_FD_register_map.all;
91: use ctu_can_fd_rtl.CAN_FD_frame_format.all;
92:
93: entity rx_shift_reg is
94: port (
95: -------------------------------------------------------------------------------------------
96: -- Clock and Asynchronous Reset
97: -------------------------------------------------------------------------------------------
98: clk_sys : in std_logic;
99: res_n : in std_logic;
100:
101: -------------------------------------------------------------------------------------------
102: -- DFT support
103: -------------------------------------------------------------------------------------------
104: scan_enable : in std_logic;
105:
106: -------------------------------------------------------------------------------------------
107: -- Trigger signals
108: -------------------------------------------------------------------------------------------
109: -- RX Trigger
110: rx_trigger : in std_logic;
111:
112: -------------------------------------------------------------------------------------------
113: -- Data-path interface
114: -------------------------------------------------------------------------------------------
115: -- Actual RX Data
116: rx_data_nbs : in std_logic;
117:
118: -------------------------------------------------------------------------------------------
119: -- Protocol control FSM interface
120: -------------------------------------------------------------------------------------------
121: -- Clear all registers in Shift register (Glitch free)
122: rx_clear : in std_logic;
123:
124: -- Clock Enable RX Shift register for each byte.
125: rx_shift_ena : in std_logic_vector(3 downto 0);
126:
127: -- Selector for inputs of each byte of shift register
128: -- (0-Previous byte output, 1- RX Data input)
129: rx_shift_in_sel : in std_logic;
130:
131: -- Store Base Identifier
132: rx_store_base_id : in std_logic;
133:
134: -- Store Extended Identifier
135: rx_store_ext_id : in std_logic;
136:
137: -- Store Identifier extension
138: rx_store_ide : in std_logic;
139:
140: -- Store Remote transmission request
141: rx_store_rtr : in std_logic;
142:
143: -- Store EDL (FDF) bit
144: rx_store_edl : in std_logic;
145:
146: -- Store DLC
147: rx_store_dlc : in std_logic;
148:
149: -- Store ESI
150: rx_store_esi : in std_logic;
151:
152: -- Store BRS
153: rx_store_brs : in std_logic;
154:
155: -- Store stuff count
156: rx_store_stuff_count : in std_logic;
157:
158: -------------------------------------------------------------------------------------------
159: -- RX Buffer interface
160: -------------------------------------------------------------------------------------------
161: -- RX CAN Identifier
162: rec_ident : out std_logic_vector(28 downto 0);
163:
164: -- RX Data length code (D input)
165: rec_dlc_d : out std_logic_vector(3 downto 0);
166:
167: -- RX Data length code
168: rec_dlc : out std_logic_vector(3 downto 0);
169:
170: -- RX Remote transmission request flag
171: rec_is_rtr : out std_logic;
172:
173: -- RX Recieved identifier type (0-BASE Format, 1-Extended Format);
174: rec_ident_type : out std_logic;
175:
176: -- RX frame type (0-CAN 2.0, 1- CAN FD)
177: rec_frame_type : out std_logic;
178:
179: -- RX Bit rate shift Flag
180: rec_brs : out std_logic;
181:
182: -- RX Error state indicator
183: rec_esi : out std_logic;
184:
185: -- Data words to be stored to RX Buffer. Valid only when rx_trigger='1' in last bit of data
186: -- word stored
187: store_data_word : out std_logic_vector(31 downto 0);
188:
189: -------------------------------------------------------------------------------------------
190: -- CRC information for CRC comparison
191: -------------------------------------------------------------------------------------------
192: -- Received CRC
193: rx_crc : out std_logic_vector(20 downto 0);
194:
195: -- Received Stuff count + Stuff Parity
196: rx_stuff_count : out std_logic_vector(3 downto 0)
197: );
198: end entity;
199:
200: architecture rtl of rx_shift_reg is
201:
202: -- Internal reset
203: signal res_n_i_d : std_logic;
204: signal res_n_i_q_scan : std_logic;
205:
206: -- Shift register status
207: signal rx_shift_reg_q : std_logic_vector(31 downto 0);
208:
209: -- RX Shift register shift
210: signal rx_shift_cmd : std_logic_vector(3 downto 0);
211:
212: -- Shift register input selector demuxed
213: signal rx_shift_in_sel_demuxed : std_logic_vector(3 downto 1);
214:
215: signal rec_is_rtr_i : std_logic;
216: signal rec_frame_type_i : std_logic;
217:
218: begin
219:
220: -- Internal reset: Async reset + reset by design!
221: res_n_i_d <= '0' when (rx_clear = '1' or res_n = '0')
222: else
223: '1';
224:
225: -----------------------------------------------------------------------------------------------
226: -- Registering reset to avoid glitches
227: -----------------------------------------------------------------------------------------------
228: rx_shift_res_reg_inst : entity ctu_can_fd_rtl.rst_reg
229: generic map (
230: G_RESET_POLARITY => '0'
231: )
232: port map (
233: -- Clock and Reset
234: clk => clk_sys, -- IN
235: arst => res_n, -- IN
236:
237: -- Flip flop input / output
238: d => res_n_i_d, -- IN
239: q => res_n_i_q_scan, -- OUT
240:
241: -- Scan mode control
242: scan_enable => scan_enable -- IN
243: );
244:
245: -----------------------------------------------------------------------------------------------
246: -- Shift the register when it is enabled and RX Trigger is active! Protocol control keeps the
247: -- register disabled when e.g Bus is idle to save power!
248: -----------------------------------------------------------------------------------------------
249: rx_shift_cmd_gen : for i in 0 to 3 generate
250: rx_shift_cmd(i) <= '1' when (rx_trigger = '1' and rx_shift_ena(i) = '1')
251: else
252: '0';
253: end generate rx_shift_cmd_gen;
254:
255: -----------------------------------------------------------------------------------------------
256: -- D input of received DLC is needed by Protocol control FSM in the last bit of DLC. Thus it is
257: -- needed at the same clock cycle as it is stored so Q value is not yet there!
258: -----------------------------------------------------------------------------------------------
259: rec_dlc_d <= rx_shift_reg_q(2 downto 0) & rx_data_nbs;
260:
261: rx_shift_in_sel_demuxed <= rx_shift_in_sel & rx_shift_in_sel &
262: rx_shift_in_sel;
263:
264: -----------------------------------------------------------------------------------------------
265: -- RX Shift register
266: -----------------------------------------------------------------------------------------------
267: shift_reg_byte_inst : entity ctu_can_fd_rtl.shift_reg_byte
268: generic map (
269: G_RESET_POLARITY => '0',
270: G_RESET_VALUE => x"00000000",
271: G_NUM_BYTES => 4
272: )
273: port map (
274: clk => clk_sys, -- IN
275: res_n => res_n_i_q_scan, -- IN
276: input => rx_data_nbs, -- IN
277: byte_clock_ena => rx_shift_cmd, -- IN
278: byte_input_sel => rx_shift_in_sel_demuxed, -- IN
279:
280: reg_stat => rx_shift_reg_q -- OUT
281: );
282:
283: -----------------------------------------------------------------------------------------------
284: -- Store Identifier
285: -----------------------------------------------------------------------------------------------
286: id_store_proc : process(clk_sys, res_n_i_q_scan)
287: begin
288: if (res_n_i_q_scan = '0') then
289: rec_ident <= (others => '0');
290: elsif (rising_edge(clk_sys)) then
291: if (rx_store_base_id = '1') then
292: rec_ident(IDENTIFIER_BASE_H downto IDENTIFIER_BASE_L) <=
293: rx_shift_reg_q(9 downto 0) & rx_data_nbs;
294: end if;
295:
296: if (rx_store_ext_id = '1') then
297: rec_ident(IDENTIFIER_EXT_H downto IDENTIFIER_EXT_L) <=
298: rx_shift_reg_q(16 downto 0) & rx_data_nbs;
299: end if;
300: end if;
301: end process;
302:
303: -----------------------------------------------------------------------------------------------
304: -- Store IDE bit (Identifier type)
305: -----------------------------------------------------------------------------------------------
306: ide_store_proc : process(clk_sys, res_n_i_q_scan)
307: begin
308: if (res_n_i_q_scan = '0') then
309: rec_ident_type <= '0';
310: elsif (rising_edge(clk_sys)) then
311: if (rx_store_ide = '1') then
312: rec_ident_type <= rx_data_nbs;
313: end if;
314: end if;
315: end process;
316:
317: -----------------------------------------------------------------------------------------------
318: -- RX Store RTR bit (Remote transmission request bit)
319: -----------------------------------------------------------------------------------------------
320: rx_store_proc : process(clk_sys, res_n_i_q_scan)
321: begin
322: if (res_n_i_q_scan = '0') then
323: rec_is_rtr_i <= '0';
324: elsif (rising_edge(clk_sys)) then
325: if (rx_store_rtr = '1') then
326: rec_is_rtr_i <= rx_data_nbs;
327: end if;
328: end if;
329: end process;
330:
331: -- RTR flag can't be active at the same time as FDF. FDF has priority!
332: rec_is_rtr <= rec_is_rtr_i when (rec_frame_type_i = NORMAL_CAN)
333: else
334: NO_RTR_FRAME;
335:
336: -----------------------------------------------------------------------------------------------
337: -- Store EDL/FDF bit (Extended data length or Flexible data-rate format)
338: -----------------------------------------------------------------------------------------------
339: edl_store_proc : process(clk_sys, res_n_i_q_scan)
340: begin
341: if (res_n_i_q_scan = '0') then
342: rec_frame_type_i <= '0';
343: elsif (rising_edge(clk_sys)) then
344: if (rx_store_edl = '1') then
345: rec_frame_type_i <= rx_data_nbs;
346: end if;
347: end if;
348: end process;
349:
350: rec_frame_type <= rec_frame_type_i;
351:
352:
353: -----------------------------------------------------------------------------------------------
354: -- Store ESI bit (Error state indicator)
355: -----------------------------------------------------------------------------------------------
356: esi_store_proc : process(clk_sys, res_n_i_q_scan)
357: begin
358: if (res_n_i_q_scan = '0') then
359: rec_esi <= '0';
360: elsif (rising_edge(clk_sys)) then
361: if (rx_store_esi = '1') then
362: rec_esi <= rx_data_nbs;
363: end if;
364: end if;
365: end process;
366:
367: -----------------------------------------------------------------------------------------------
368: -- Store BRS bit (Bit rate shift)
369: -----------------------------------------------------------------------------------------------
370: brs_store_proc : process(clk_sys, res_n_i_q_scan)
371: begin
372: if (res_n_i_q_scan = '0') then
373: rec_brs <= '0';
374: elsif (rising_edge(clk_sys)) then
375: if (rx_store_brs = '1') then
376: rec_brs <= rx_data_nbs;
377: end if;
378: end if;
379: end process;
380:
381: -----------------------------------------------------------------------------------------------
382: -- Store DLC (Data length code)
383: -----------------------------------------------------------------------------------------------
384: dlc_store_proc : process(clk_sys, res_n_i_q_scan)
385: begin
386: if (res_n_i_q_scan = '0') then
387: rec_dlc <= (others => '0');
388: elsif (rising_edge(clk_sys)) then
389: if (rx_store_dlc = '1') then
390: rec_dlc <= rx_shift_reg_q(2 downto 0) & rx_data_nbs;
391: end if;
392: end if;
393: end process;
394:
395: -----------------------------------------------------------------------------------------------
396: -- Store RX Stuff Count
397: -----------------------------------------------------------------------------------------------
398: stuff_count_store_proc : process(clk_sys, res_n_i_q_scan)
399: begin
400: if (res_n_i_q_scan = '0') then
401: rx_stuff_count <= (others => '0');
402: elsif (rising_edge(clk_sys)) then
403: if (rx_store_stuff_count = '1') then
404: rx_stuff_count <= rx_shift_reg_q(2 downto 0) & rx_data_nbs;
405: end if;
406: end if;
407: end process;
408:
409:
410: -----------------------------------------------------------------------------------------------
411: -- CRC Value propagation to output. Valid only when rx_trigger='1' in the last clock cycle of
412: -- last CRC bit.
413: -----------------------------------------------------------------------------------------------
414: rx_crc <= rx_shift_reg_q(20 downto 0);
415:
416: -----------------------------------------------------------------------------------------------
417: -- Output data word. Valid one clock cycle after rx_trigger='1'. Whole output data word is
418: -- taken from shift reg. instead of taking the lowest byte from data input (as in case of ID,
419: -- DLC, etc.). This is because the lowest bit does not have fixed position if data word is
420: -- being stored! Due to this, when storing data word to RX Buffer, it must be stored one clock
421: -- cycle after rx_trigger='1'!
422: -----------------------------------------------------------------------------------------------
423: store_data_word <= rx_shift_reg_q;
424:
425: -----------------------------------------------------------------------------------------------
426: -- Assertions
427: -----------------------------------------------------------------------------------------------
428:
429: -- psl default clock is rising_edge(clk_sys);
430:
431: -- psl rx_shift_reg_byte_config : assert never
432: -- (rx_shift_in_sel = '1') and
433: -- (rx_store_base_id = '1' or rx_store_ext_id = '1' or
434: -- rx_store_ide = '1' or rx_store_rtr = '1' or rx_store_edl = '1' or
435: -- rx_store_dlc = '1' or rx_store_esi = '1' or rx_store_brs = '1' or
436: -- rx_store_stuff_count = '1')
437: -- report "RX Shift register should be configured as Byte shift register only during DATA phase of CAN frame";
438:
439: -- psl no_simul_capture_and_clear : assert never
440: -- (res_n_i_q_scan = '0') and
441: -- (rx_store_base_id = '1' or rx_store_ext_id = '1' or
442: -- rx_store_ide = '1' or rx_store_rtr = '1' or rx_store_edl = '1' or
443: -- rx_store_dlc = '1' or rx_store_esi = '1' or rx_store_brs = '1' or
444: -- rx_store_stuff_count = '1')
445: -- report "RX Shift register should not be cleared when RX Data should be stored!";
446:
447: end architecture;