NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RETRANSMITT_COUNTER	100.0 % (15/15)	100.0 % (14/14)	100.0 % (46/46)	100.0 % (25/25)	N.A.	N.A.	100.0 % (100/100)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RETRANSMITT_COUNTER

100.0 % (15/15)

100.0 % (14/14)

100.0 % (46/46)

100.0 % (25/25)

N.A.

100.0 % (100/100)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

143:    retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else 
144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else 
145:                   retr_ctr_q;

Count: 90557
Threshold: 1

Signal assignment statement on line 143:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else
Count: 21288
Threshold: 1

Signal assignment statement on line 144:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

Count: 30935
Threshold: 1

Signal assignment statement on line 145:

145: retr_ctr_q;
Count: 38334
Threshold: 1

If statement on lines 148 to 150:

148:    retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1') 
149:                       else 
150:                   '0';

Count: 87631
Threshold: 1

Signal assignment statement on line 148:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')
Count: 50936
Threshold: 1

Signal assignment statement on line 150:

150: '0';
Count: 36695
Threshold: 1

If statement on lines 157 to 163:

157:        if (rst_n = '0') then 
158:            retr_ctr_q <= (others => '0'); 
...
162:            end if; 
163:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 158:

158: retr_ctr_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 160 to 162:

160:            if (retr_ctr_ce = '1') then 
161:                retr_ctr_q <= retr_ctr_d; 
162:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 161:

161: retr_ctr_q <= retr_ctr_d;
Count: 31880
Threshold: 1

If statement on lines 167 to 169:

167:    retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q) 
168:                              else 
169:                          '0';

Count: 6278
Threshold: 1

Signal assignment statement on line 167:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)
Count: 1858
Threshold: 1

Signal assignment statement on line 169:

169: '0';
Count: 4420
Threshold: 1

Signal assignment statement on line 172:

172: retr_ctr <= std_logic_vector(retr_ctr_q);
Count: 4527
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

143: retr_ctr_d <= (retr_ctr_q + 1) when (retr_ctr_add = '1') else

	Evaluated to	Count	Threshold
Bin	True	21288	1
Bin	False	69269	1

"if" / "when" / "else" condition on line 144:

144:                   (others => '0') when (retr_ctr_clear = '1' or txtb_changed = '1') else

	Evaluated to	Count	Threshold
Bin	True	30935	1
Bin	False	38334	1

"if" / "when" / "else" condition on line 148:

148: retr_ctr_ce <= '1' when (txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1')

	Evaluated to	Count	Threshold
Bin	True	50936	1
Bin	False	36695	1

"if" / "when" / "else" condition on line 157:

157: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 159:

159: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 160:

160: if (retr_ctr_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	31880	1
Bin	False	547142454	1

"if" / "when" / "else" condition on line 167:

167: retr_limit_reached <= '1' when (unsigned(mr_settings_rtrth) = retr_ctr_q)

	Evaluated to	Count	Threshold
Bin	True	1858	1
Bin	False	4420	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TXTB_CHANGED

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RETR_CTR_CLEAR

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RETR_CTR_ADD

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

MR_SETTINGS_RTRTH

	Element	From	To	Threshold	Excluded due to
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Covered toggles:

Port:

RETR_LIMIT_REACHED

	From	To	Count	Threshold
Bin	0	1	1858	1
Bin	1	0	1858	1

Port:

RETR_CTR

	Element	From	To	Count	Threshold
Bin	(3)	0	1	55	1
Bin	(3)	1	0	1656	1
Bin	(2)	0	1	134	1
Bin	(2)	1	0	1735	1
Bin	(1)	0	1	265	1
Bin	(1)	1	0	1866	1
Bin	(0)	0	1	646	1
Bin	(0)	1	0	2247	1

Signal:

RETR_CTR_D

	Element	From	To	Count	Threshold
Bin	(3)	0	1	160	1
Bin	(3)	1	0	1761	1
Bin	(2)	0	1	376	1
Bin	(2)	1	0	1977	1
Bin	(1)	0	1	975	1
Bin	(1)	1	0	2576	1
Bin	(0)	0	1	11327	1
Bin	(0)	1	0	12928	1

Signal:

RETR_CTR_Q

	Element	From	To	Count	Threshold
Bin	(3)	0	1	55	1
Bin	(3)	1	0	1656	1
Bin	(2)	0	1	134	1
Bin	(2)	1	0	1735	1
Bin	(1)	0	1	265	1
Bin	(1)	1	0	1866	1
Bin	(0)	0	1	646	1
Bin	(0)	1	0	2247	1

Signal:

RETR_CTR_CE

	From	To	Count	Threshold
Bin	0	1	31892	1
Bin	1	0	33493	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 143:

retr_ctr_add = '1'

	Evaluated to	Count	Threshold
Bin	False	69269	1
Bin	True	21288	1

"or" expression on line 144:

 retr_ctr_clear = '1' or txtb_changed = '1' 
 <-------LHS-------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	38334	1
Bin	False	True	10038	1
Bin	True	False	20897	1

"=" expression on line 144:

retr_ctr_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	48372	1
Bin	True	20897	1

"=" expression on line 144:

txtb_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	59231	1
Bin	True	10038	1

"or" expression on line 148:

 txtb_changed = '1' or retr_ctr_clear = '1' or retr_ctr_add = '1' 
 <------------------LHS------------------->    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	36695	1
Bin	False	True	10515	1
Bin	True	False	30770	1

"or" expression on line 148:

 txtb_changed = '1' or retr_ctr_clear = '1' 
 <------LHS------->    <-------RHS-------->

	LHS	RHS	Count	Threshold
Bin	False	False	47210	1
Bin	False	True	30429	1
Bin	True	False	9992	1

"=" expression on line 148:

txtb_changed = '1'

	Evaluated to	Count	Threshold
Bin	False	77639	1
Bin	True	9992	1

"=" expression on line 148:

retr_ctr_clear = '1'

	Evaluated to	Count	Threshold
Bin	False	57202	1
Bin	True	30429	1

"=" expression on line 148:

retr_ctr_add = '1'

	Evaluated to	Count	Threshold
Bin	False	67465	1
Bin	True	20166	1

"=" expression on line 157:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 160:

retr_ctr_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	547142454	1
Bin	True	31880	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_MAC_TOP.I_MAC_PC_TOP.I_MAC_PC_RETRANSMITT_COUNTER

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/medium_access_control/mac_pc_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 143 to 145:

Signal assignment statement on line 143:

Signal assignment statement on line 144:

Signal assignment statement on line 145:

If statement on lines 148 to 150:

Signal assignment statement on line 148:

Signal assignment statement on line 150:

If statement on lines 157 to 163:

Signal assignment statement on line 158:

If statement on lines 160 to 162:

Signal assignment statement on line 161:

If statement on lines 167 to 169:

Signal assignment statement on line 167:

Signal assignment statement on line 169:

Signal assignment statement on line 172:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 143:

"if" / "when" / "else" condition on line 144:

"if" / "when" / "else" condition on line 148:

"if" / "when" / "else" condition on line 157:

"if" / "when" / "else" condition on line 159:

"if" / "when" / "else" condition on line 160:

"if" / "when" / "else" condition on line 167:

Uncovered toggles:

Excluded toggles:

Port:

Port:

Port:

Port:

Port:

Port:

Covered toggles:

Port:

Port:

Signal:

Signal:

Signal:

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 143:

"or" expression on line 144:

"=" expression on line 144:

"=" expression on line 144:

"or" expression on line 148:

"or" expression on line 148:

"=" expression on line 148:

"=" expression on line 148:

"=" expression on line 148:

"=" expression on line 157:

"=" expression on line 160:

Uncovered FSM states:

Excluded FSM states:

Covered FSM states:

Uncovered functional coverage:

Excluded functional coverage:

Covered functional coverage: