NVC code coverage report

Signal assignment statement on line 196:

196:    rxb_port_b_data_out <= rxb_port_b_data_out_i; 
Count: 107537
Threshold: 1

---

Signal assignment statement on lines 287 to 288:

287:        mr_tst_dest_tst_addr_pad <= 
288:            std_logic_vector(unsigned(mr_tst_dest_tst_addr) mod G_RX_BUF_SIZE); 
Count: 93288
Threshold: 1

---

If statement on lines 291 to 293:

291:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = TMTGT_RXBUF) 
292:                   else 
293:               '0'; 
Count: 6708
Threshold: 1

---

Signal assignment statement on line 291:

291:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = TMTGT_RXBUF) 
Count: 45
Threshold: 1

---

Signal assignment statement on line 293:

293:               '0'; 
Count: 6663
Threshold: 1

---

If statement on lines 296 to 298:

296:    rxb_port_a_address_i <= rxb_port_a_address when (tst_ena = '0') 
297:                                               else 
298:                            mr_tst_dest_tst_addr_pad(G_RX_BUF_PTR_WIDTH - 1 downto 0); 
Count: 340600
Threshold: 1

---

Signal assignment statement on line 296:

296:    rxb_port_a_address_i <= rxb_port_a_address when (tst_ena = '0') 
Count: 293415
Threshold: 1

---

Signal assignment statement on line 298:

298:                            mr_tst_dest_tst_addr_pad(G_RX_BUF_PTR_WIDTH - 1 downto 0); 
Count: 47185
Threshold: 1

---

If statement on lines 300 to 302:

300:    rxb_port_a_write_i <= rxb_port_a_write when (tst_ena = '0') 
301:                                           else 
302:                          mr_tst_control_twrstb; 
Count: 355005
Threshold: 1

---

Signal assignment statement on line 300:

300:    rxb_port_a_write_i <= rxb_port_a_write when (tst_ena = '0') 
Count: 284971
Threshold: 1

---

Signal assignment statement on line 302:

302:                          mr_tst_control_twrstb; 
Count: 70034
Threshold: 1

---

If statement on lines 304 to 306:

304:    rxb_port_a_data_in_i <= rxb_port_a_data_in when (tst_ena = '0') 
305:                                               else 
306:                            mr_tst_wdata_tst_wdata; 
Count: 3113378
Threshold: 1

---

Signal assignment statement on line 304:

304:    rxb_port_a_data_in_i <= rxb_port_a_data_in when (tst_ena = '0') 
Count: 3106983
Threshold: 1

---

Signal assignment statement on line 306:

306:                            mr_tst_wdata_tst_wdata; 
Count: 6395
Threshold: 1

---

If statement on lines 309 to 311:

309:    rxb_port_b_address_i <= rxb_port_b_address when (tst_ena = '0') 
310:                                               else 
311:                            mr_tst_dest_tst_addr_pad(G_RX_BUF_PTR_WIDTH - 1 downto 0); 
Count: 234701
Threshold: 1

---

Signal assignment statement on line 309:

309:    rxb_port_b_address_i <= rxb_port_b_address when (tst_ena = '0') 
Count: 187516
Threshold: 1

---

Signal assignment statement on line 311:

311:                            mr_tst_dest_tst_addr_pad(G_RX_BUF_PTR_WIDTH - 1 downto 0); 
Count: 47185
Threshold: 1

---

If statement on lines 313 to 315:

313:    mr_tst_rdata_tst_rdata <= rxb_port_b_data_out_i when (tst_ena = '1') 
314:                                                    else 
315:                              (others => '0'); 
Count: 109228
Threshold: 1

---

Signal assignment statement on line 313:

313:    mr_tst_rdata_tst_rdata <= rxb_port_b_data_out_i when (tst_ena = '1') 
Count: 50101
Threshold: 1

---

Signal assignment statement on line 315:

315:                              (others => '0'); 
Count: 59127
Threshold: 1

"if" / "when" / "else" condition on line 291:

291:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = TMTGT_RXBUF) 

	Evaluated to	Count	Threshold
Bin	True	45	1
Bin	False	6663	1

---

"if" / "when" / "else" condition on line 296:

296:    rxb_port_a_address_i <= rxb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	293415	1
Bin	False	47185	1

---

"if" / "when" / "else" condition on line 300:

300:    rxb_port_a_write_i <= rxb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	284971	1
Bin	False	70034	1

---

"if" / "when" / "else" condition on line 304:

304:    rxb_port_a_data_in_i <= rxb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	3106983	1
Bin	False	6395	1

---

"if" / "when" / "else" condition on line 309:

309:    rxb_port_b_address_i <= rxb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	187516	1
Bin	False	47185	1

---

"if" / "when" / "else" condition on line 313:

313:    mr_tst_rdata_tst_rdata <= rxb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	50101	1
Bin	False	59127	1

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 RXB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 RXB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 RXB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RXB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Signal:

 MR_TST_DEST_TST_ADDR_PAD

	Element	From	To	Count	Threshold	Excluded due to
Bin	(15)	0	1	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	21399	1
Bin	(31)	1	0	18493	1
Bin	(30)	0	1	12499	1
Bin	(30)	1	0	18612	1
Bin	(29)	0	1	16902	1
Bin	(29)	1	0	13996	1
Bin	(28)	0	1	17082	1
Bin	(28)	1	0	23195	1
Bin	(27)	0	1	17015	1
Bin	(27)	1	0	14109	1
Bin	(26)	0	1	16993	1
Bin	(26)	1	0	23106	1
Bin	(25)	0	1	21615	1
Bin	(25)	1	0	18709	1
Bin	(24)	0	1	12394	1
Bin	(24)	1	0	18507	1
Bin	(23)	0	1	21421	1
Bin	(23)	1	0	18515	1
Bin	(22)	0	1	12559	1
Bin	(22)	1	0	18672	1
Bin	(21)	0	1	16960	1
Bin	(21)	1	0	14054	1
Bin	(20)	0	1	17078	1
Bin	(20)	1	0	23191	1
Bin	(19)	0	1	17010	1
Bin	(19)	1	0	14104	1
Bin	(18)	0	1	16966	1
Bin	(18)	1	0	23079	1
Bin	(17)	0	1	21592	1
Bin	(17)	1	0	18686	1
Bin	(16)	0	1	12366	1
Bin	(16)	1	0	18479	1
Bin	(15)	0	1	21426	1
Bin	(15)	1	0	18520	1
Bin	(14)	0	1	12538	1
Bin	(14)	1	0	18651	1
Bin	(13)	0	1	16985	1
Bin	(13)	1	0	14079	1
Bin	(12)	0	1	17133	1
Bin	(12)	1	0	23246	1
Bin	(11)	0	1	17035	1
Bin	(11)	1	0	14129	1
Bin	(10)	0	1	16976	1
Bin	(10)	1	0	23089	1
Bin	(9)	0	1	21642	1
Bin	(9)	1	0	18736	1
Bin	(8)	0	1	12374	1
Bin	(8)	1	0	18487	1
Bin	(7)	0	1	21491	1
Bin	(7)	1	0	18585	1
Bin	(6)	0	1	12603	1
Bin	(6)	1	0	18716	1
Bin	(5)	0	1	16973	1
Bin	(5)	1	0	14067	1
Bin	(4)	0	1	17089	1
Bin	(4)	1	0	23202	1
Bin	(3)	0	1	17026	1
Bin	(3)	1	0	14120	1
Bin	(2)	0	1	16994	1
Bin	(2)	1	0	23107	1
Bin	(1)	0	1	21633	1
Bin	(1)	1	0	18727	1
Bin	(0)	0	1	12422	1
Bin	(0)	1	0	18535	1

---

Port:

 RXB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	25127	1
Bin	(31)	1	0	23668	1
Bin	(30)	0	1	16750	1
Bin	(30)	1	0	24002	1
Bin	(29)	0	1	20741	1
Bin	(29)	1	0	19160	1
Bin	(28)	0	1	25091	1
Bin	(28)	1	0	34100	1
Bin	(27)	0	1	25192	1
Bin	(27)	1	0	24966	1
Bin	(26)	0	1	24518	1
Bin	(26)	1	0	33476	1
Bin	(25)	0	1	28939	1
Bin	(25)	1	0	28862	1
Bin	(24)	0	1	27276	1
Bin	(24)	1	0	29934	1
Bin	(23)	0	1	28977	1
Bin	(23)	1	0	28891	1
Bin	(22)	0	1	20515	1
Bin	(22)	1	0	29260	1
Bin	(21)	0	1	25083	1
Bin	(21)	1	0	24832	1
Bin	(20)	0	1	25360	1
Bin	(20)	1	0	34091	1
Bin	(19)	0	1	26658	1
Bin	(19)	1	0	26871	1
Bin	(18)	0	1	27021	1
Bin	(18)	1	0	36204	1
Bin	(17)	0	1	30504	1
Bin	(17)	1	0	29594	1
Bin	(16)	0	1	21581	1
Bin	(16)	1	0	29591	1
Bin	(15)	0	1	30594	1
Bin	(15)	1	0	28820	1
Bin	(14)	0	1	22942	1
Bin	(14)	1	0	30151	1
Bin	(13)	0	1	30179	1
Bin	(13)	1	0	25900	1
Bin	(12)	0	1	32619	1
Bin	(12)	1	0	37795	1
Bin	(11)	0	1	33856	1
Bin	(11)	1	0	29259	1
Bin	(10)	0	1	27274	1
Bin	(10)	1	0	33859	1
Bin	(9)	0	1	33278	1
Bin	(9)	1	0	30434	1
Bin	(8)	0	1	22595	1
Bin	(8)	1	0	29433	1
Bin	(7)	0	1	34617	1
Bin	(7)	1	0	31102	1
Bin	(6)	0	1	24596	1
Bin	(6)	1	0	30113	1
Bin	(5)	0	1	29638	1
Bin	(5)	1	0	27108	1
Bin	(4)	0	1	27224	1
Bin	(4)	1	0	33970	1
Bin	(3)	0	1	28271	1
Bin	(3)	1	0	25534	1
Bin	(2)	0	1	28423	1
Bin	(2)	1	0	34635	1
Bin	(1)	0	1	33739	1
Bin	(1)	1	0	30948	1
Bin	(0)	0	1	24894	1
Bin	(0)	1	0	30626	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	18725	1
Bin	1	0	19742	1

---

Signal:

 RXB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(11)	0	1	28	1
Bin	(11)	1	0	193	1
Bin	(10)	0	1	53	1
Bin	(10)	1	0	218	1
Bin	(9)	0	1	108	1
Bin	(9)	1	0	273	1
Bin	(8)	0	1	218	1
Bin	(8)	1	0	383	1
Bin	(7)	0	1	432	1
Bin	(7)	1	0	597	1
Bin	(6)	0	1	1184	1
Bin	(6)	1	0	1844	1
Bin	(5)	0	1	2500	1
Bin	(5)	1	0	3160	1
Bin	(4)	0	1	8848	1
Bin	(4)	1	0	10449	1
Bin	(3)	0	1	20078	1
Bin	(3)	1	0	21679	1
Bin	(2)	0	1	43645	1
Bin	(2)	1	0	45244	1
Bin	(1)	0	1	72179	1
Bin	(1)	1	0	73780	1
Bin	(0)	0	1	134717	1
Bin	(0)	1	0	136318	1

---

Signal:

 RXB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	148051	1
Bin	1	0	149688	1

---

Signal:

 RXB_PORT_A_DATA_IN_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	119737	1
Bin	(31)	1	0	121338	1
Bin	(30)	0	1	121390	1
Bin	(30)	1	0	122991	1
Bin	(29)	0	1	124552	1
Bin	(29)	1	0	126153	1
Bin	(28)	0	1	142955	1
Bin	(28)	1	0	144556	1
Bin	(27)	0	1	139650	1
Bin	(27)	1	0	141251	1
Bin	(26)	0	1	148873	1
Bin	(26)	1	0	150474	1
Bin	(25)	0	1	141519	1
Bin	(25)	1	0	143120	1
Bin	(24)	0	1	164035	1
Bin	(24)	1	0	165636	1
Bin	(23)	0	1	140554	1
Bin	(23)	1	0	142155	1
Bin	(22)	0	1	152229	1
Bin	(22)	1	0	153830	1
Bin	(21)	0	1	144975	1
Bin	(21)	1	0	146576	1
Bin	(20)	0	1	155366	1
Bin	(20)	1	0	156967	1
Bin	(19)	0	1	155839	1
Bin	(19)	1	0	157440	1
Bin	(18)	0	1	168165	1
Bin	(18)	1	0	169766	1
Bin	(17)	0	1	155660	1
Bin	(17)	1	0	157261	1
Bin	(16)	0	1	158823	1
Bin	(16)	1	0	160424	1
Bin	(15)	0	1	196283	1
Bin	(15)	1	0	197884	1
Bin	(14)	0	1	190122	1
Bin	(14)	1	0	191723	1
Bin	(13)	0	1	188306	1
Bin	(13)	1	0	189907	1
Bin	(12)	0	1	201616	1
Bin	(12)	1	0	203217	1
Bin	(11)	0	1	198537	1
Bin	(11)	1	0	200138	1
Bin	(10)	0	1	182284	1
Bin	(10)	1	0	183885	1
Bin	(9)	0	1	186806	1
Bin	(9)	1	0	188407	1
Bin	(8)	0	1	175981	1
Bin	(8)	1	0	177582	1
Bin	(7)	0	1	202418	1
Bin	(7)	1	0	204019	1
Bin	(6)	0	1	195294	1
Bin	(6)	1	0	196895	1
Bin	(5)	0	1	189771	1
Bin	(5)	1	0	191372	1
Bin	(4)	0	1	186633	1
Bin	(4)	1	0	188234	1
Bin	(3)	0	1	196016	1
Bin	(3)	1	0	197617	1
Bin	(2)	0	1	199292	1
Bin	(2)	1	0	200893	1
Bin	(1)	0	1	202871	1
Bin	(1)	1	0	204472	1
Bin	(0)	0	1	206753	1
Bin	(0)	1	0	208354	1

---

Signal:

 RXB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(11)	0	1	17	1
Bin	(11)	1	0	182	1
Bin	(10)	0	1	34	1
Bin	(10)	1	0	199	1
Bin	(9)	0	1	71	1
Bin	(9)	1	0	236	1
Bin	(8)	0	1	144	1
Bin	(8)	1	0	309	1
Bin	(7)	0	1	287	1
Bin	(7)	1	0	452	1
Bin	(6)	0	1	870	1
Bin	(6)	1	0	1530	1
Bin	(5)	0	1	1856	1
Bin	(5)	1	0	2516	1
Bin	(4)	0	1	5535	1
Bin	(4)	1	0	7136	1
Bin	(3)	0	1	11393	1
Bin	(3)	1	0	12994	1
Bin	(2)	0	1	23670	1
Bin	(2)	1	0	25271	1
Bin	(1)	0	1	47182	1
Bin	(1)	1	0	48783	1
Bin	(0)	0	1	92352	1
Bin	(0)	1	0	93953	1

---

Signal:

 RXB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	24804	1
Bin	(31)	1	0	22523	1
Bin	(30)	0	1	16198	1
Bin	(30)	1	0	22837	1
Bin	(29)	0	1	20391	1
Bin	(29)	1	0	18033	1
Bin	(28)	0	1	24779	1
Bin	(28)	1	0	31436	1
Bin	(27)	0	1	24649	1
Bin	(27)	1	0	22263	1
Bin	(26)	0	1	24168	1
Bin	(26)	1	0	30838	1
Bin	(25)	0	1	28614	1
Bin	(25)	1	0	26203	1
Bin	(24)	0	1	24543	1
Bin	(24)	1	0	28090	1
Bin	(23)	0	1	28641	1
Bin	(23)	1	0	26209	1
Bin	(22)	0	1	20175	1
Bin	(22)	1	0	26696	1
Bin	(21)	0	1	24540	1
Bin	(21)	1	0	22075	1
Bin	(20)	0	1	24838	1
Bin	(20)	1	0	31443	1
Bin	(19)	0	1	26082	1
Bin	(19)	1	0	23687	1
Bin	(18)	0	1	26624	1
Bin	(18)	1	0	33093	1
Bin	(17)	0	1	29923	1
Bin	(17)	1	0	27439	1
Bin	(16)	0	1	21005	1
Bin	(16)	1	0	27348	1
Bin	(15)	0	1	30208	1
Bin	(15)	1	0	27742	1
Bin	(14)	0	1	22590	1
Bin	(14)	1	0	28992	1
Bin	(13)	0	1	29365	1
Bin	(13)	1	0	24822	1
Bin	(12)	0	1	31117	1
Bin	(12)	1	0	36395	1
Bin	(11)	0	1	32307	1
Bin	(11)	1	0	27728	1
Bin	(10)	0	1	27270	1
Bin	(10)	1	0	33357	1
Bin	(9)	0	1	33273	1
Bin	(9)	1	0	29909	1
Bin	(8)	0	1	22591	1
Bin	(8)	1	0	28918	1
Bin	(7)	0	1	34613	1
Bin	(7)	1	0	30592	1
Bin	(6)	0	1	24591	1
Bin	(6)	1	0	29606	1
Bin	(5)	0	1	29629	1
Bin	(5)	1	0	26588	1
Bin	(4)	0	1	27214	1
Bin	(4)	1	0	33451	1
Bin	(3)	0	1	28267	1
Bin	(3)	1	0	25018	1
Bin	(2)	0	1	28414	1
Bin	(2)	1	0	34130	1
Bin	(1)	0	1	33735	1
Bin	(1)	1	0	30457	1
Bin	(0)	0	1	24890	1
Bin	(0)	1	0	30128	1

---

Signal:

 MR_TST_DEST_TST_ADDR_PAD

	Element	From	To	Count	Threshold
Bin	(15)	1	0	91687	1
Bin	(14)	1	0	91687	1
Bin	(13)	1	0	91687	1
Bin	(12)	1	0	91687	1
Bin	(11)	0	1	11	1
Bin	(11)	1	0	34445	1
Bin	(10)	0	1	21	1
Bin	(10)	1	0	34455	1
Bin	(9)	0	1	41	1
Bin	(9)	1	0	34475	1
Bin	(8)	0	1	81	1
Bin	(8)	1	0	34515	1
Bin	(7)	0	1	161	1
Bin	(7)	1	0	34595	1
Bin	(6)	0	1	354	1
Bin	(6)	1	0	6298	1
Bin	(5)	0	1	704	1
Bin	(5)	1	0	6648	1
Bin	(4)	0	1	3615	1
Bin	(4)	1	0	5216	1
Bin	(3)	0	1	5035	1
Bin	(3)	1	0	6636	1
Bin	(2)	0	1	10345	1
Bin	(2)	1	0	11946	1
Bin	(1)	0	1	22457	1
Bin	(1)	1	0	24058	1
Bin	(0)	0	1	44877	1
Bin	(0)	1	0	46478	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	45	1
Bin	1	0	1646	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(4095)	0	1	6	1
Bin	(4095)	1	0	24782	1
Bin	(4094)	0	1	10	1
Bin	(4094)	1	0	24778	1
Bin	(4093)	0	1	10	1
Bin	(4093)	1	0	24778	1
Bin	(4092)	0	1	16	1
Bin	(4092)	1	0	24772	1
Bin	(4091)	0	1	23	1
Bin	(4091)	1	0	24765	1
Bin	(4090)	0	1	28	1
Bin	(4090)	1	0	24760	1
Bin	(4089)	0	1	22	1
Bin	(4089)	1	0	24766	1
Bin	(4088)	0	1	31	1
Bin	(4088)	1	0	24757	1
Bin	(4087)	0	1	42	1
Bin	(4087)	1	0	24746	1
Bin	(4086)	0	1	35	1
Bin	(4086)	1	0	24753	1
Bin	(4085)	0	1	23	1
Bin	(4085)	1	0	24765	1
Bin	(4084)	0	1	46	1
Bin	(4084)	1	0	24742	1
Bin	(4083)	0	1	59	1
Bin	(4083)	1	0	24729	1
Bin	(4082)	0	1	50	1
Bin	(4082)	1	0	24738	1
Bin	(4081)	0	1	46	1
Bin	(4081)	1	0	24742	1
Bin	(4080)	0	1	62	1
Bin	(4080)	1	0	24726	1
Bin	(4079)	0	1	78	1
Bin	(4079)	1	0	24710	1
Bin	(4078)	0	1	64	1
Bin	(4078)	1	0	24724	1
Bin	(4077)	0	1	60	1
Bin	(4077)	1	0	24728	1
Bin	(4076)	0	1	79	1
Bin	(4076)	1	0	24709	1
Bin	(4075)	0	1	98	1
Bin	(4075)	1	0	24690	1
Bin	(4074)	0	1	50	1
Bin	(4074)	1	0	24738	1
Bin	(4073)	0	1	73	1
Bin	(4073)	1	0	24715	1
Bin	(4072)	0	1	96	1
Bin	(4072)	1	0	24692	1
Bin	(4071)	0	1	117	1
Bin	(4071)	1	0	24671	1
Bin	(4070)	0	1	68	1
Bin	(4070)	1	0	24720	1
Bin	(4069)	0	1	87	1
Bin	(4069)	1	0	24701	1
Bin	(4068)	0	1	113	1
Bin	(4068)	1	0	24675	1
Bin	(4067)	0	1	134	1
Bin	(4067)	1	0	24654	1
Bin	(4066)	0	1	139	1
Bin	(4066)	1	0	24649	1
Bin	(4065)	0	1	99	1
Bin	(4065)	1	0	24689	1
Bin	(4064)	0	1	128	1
Bin	(4064)	1	0	24660	1
Bin	(4063)	0	1	153	1
Bin	(4063)	1	0	24635	1
Bin	(4062)	0	1	70	1
Bin	(4062)	1	0	24718	1
Bin	(4061)	0	1	78	1
Bin	(4061)	1	0	24710	1
Bin	(4060)	0	1	144	1
Bin	(4060)	1	0	24644	1
Bin	(4059)	0	1	172	1
Bin	(4059)	1	0	24616	1
Bin	(4058)	0	1	83	1
Bin	(4058)	1	0	24705	1
Bin	(4057)	0	1	125	1
Bin	(4057)	1	0	24663	1
Bin	(4056)	0	1	161	1
Bin	(4056)	1	0	24627	1
Bin	(4055)	0	1	191	1
Bin	(4055)	1	0	24597	1
Bin	(4054)	0	1	105	1
Bin	(4054)	1	0	24683	1
Bin	(4053)	0	1	139	1
Bin	(4053)	1	0	24649	1
Bin	(4052)	0	1	178	1
Bin	(4052)	1	0	24610	1
Bin	(4051)	0	1	208	1
Bin	(4051)	1	0	24580	1
Bin	(4050)	0	1	213	1
Bin	(4050)	1	0	24575	1
Bin	(4049)	0	1	151	1
Bin	(4049)	1	0	24637	1
Bin	(4048)	0	1	193	1
Bin	(4048)	1	0	24595	1
Bin	(4047)	0	1	228	1
Bin	(4047)	1	0	24560	1
Bin	(4046)	0	1	108	1
Bin	(4046)	1	0	24680	1
Bin	(4045)	0	1	164	1
Bin	(4045)	1	0	24624	1
Bin	(4044)	0	1	210	1
Bin	(4044)	1	0	24578	1
Bin	(4043)	0	1	246	1
Bin	(4043)	1	0	24542	1
Bin	(4042)	0	1	195	1
Bin	(4042)	1	0	24593	1
Bin	(4041)	0	1	123	1
Bin	(4041)	1	0	24665	1
Bin	(4040)	0	1	225	1
Bin	(4040)	1	0	24563	1
Bin	(4039)	0	1	262	1
Bin	(4039)	1	0	24526	1
Bin	(4038)	0	1	267	1
Bin	(4038)	1	0	24521	1
Bin	(4037)	0	1	188	1
Bin	(4037)	1	0	24600	1
Bin	(4036)	0	1	240	1
Bin	(4036)	1	0	24548	1
Bin	(4035)	0	1	282	1
Bin	(4035)	1	0	24506	1
Bin	(4034)	0	1	137	1
Bin	(4034)	1	0	24651	1
Bin	(4033)	0	1	201	1
Bin	(4033)	1	0	24587	1
Bin	(4032)	0	1	257	1
Bin	(4032)	1	0	24531	1
Bin	(4031)	0	1	302	1
Bin	(4031)	1	0	24486	1
Bin	(4030)	0	1	145	1
Bin	(4030)	1	0	24643	1
Bin	(4029)	0	1	214	1
Bin	(4029)	1	0	24574	1
Bin	(4028)	0	1	274	1
Bin	(4028)	1	0	24514	1
Bin	(4027)	0	1	321	1
Bin	(4027)	1	0	24467	1
Bin	(4026)	0	1	173	1
Bin	(4026)	1	0	24615	1
Bin	(4025)	0	1	228	1
Bin	(4025)	1	0	24560	1
Bin	(4024)	0	1	291	1
Bin	(4024)	1	0	24497	1
Bin	(4023)	0	1	341	1
Bin	(4023)	1	0	24447	1
Bin	(4022)	0	1	159	1
Bin	(4022)	1	0	24629	1
Bin	(4021)	0	1	168	1
Bin	(4021)	1	0	24620	1
Bin	(4020)	0	1	307	1
Bin	(4020)	1	0	24481	1
Bin	(4019)	0	1	359	1
Bin	(4019)	1	0	24429	1
Bin	(4018)	0	1	280	1
Bin	(4018)	1	0	24508	1
Bin	(4017)	0	1	254	1
Bin	(4017)	1	0	24534	1
Bin	(4016)	0	1	324	1
Bin	(4016)	1	0	24464	1
Bin	(4015)	0	1	378	1
Bin	(4015)	1	0	24410	1
Bin	(4014)	0	1	202	1
Bin	(4014)	1	0	24586	1
Bin	(4013)	0	1	268	1
Bin	(4013)	1	0	24520	1
Bin	(4012)	0	1	341	1
Bin	(4012)	1	0	24447	1
Bin	(4011)	0	1	396	1
Bin	(4011)	1	0	24392	1
Bin	(4010)	0	1	304	1
Bin	(4010)	1	0	24484	1
Bin	(4009)	0	1	281	1
Bin	(4009)	1	0	24507	1
Bin	(4008)	0	1	357	1
Bin	(4008)	1	0	24431	1
Bin	(4007)	0	1	417	1
Bin	(4007)	1	0	24371	1
Bin	(4006)	0	1	96	1
Bin	(4006)	1	0	24692	1
Bin	(4005)	0	1	295	1
Bin	(4005)	1	0	24493	1
Bin	(4004)	0	1	375	1
Bin	(4004)	1	0	24413	1
Bin	(4003)	0	1	434	1
Bin	(4003)	1	0	24354	1
Bin	(4002)	0	1	365	1
Bin	(4002)	1	0	24423	1
Bin	(4001)	0	1	307	1
Bin	(4001)	1	0	24481	1
Bin	(4000)	0	1	390	1
Bin	(4000)	1	0	24398	1
Bin	(3999)	0	1	454	1
Bin	(3999)	1	0	24334	1
Bin	(3998)	0	1	210	1
Bin	(3998)	1	0	24578	1
Bin	(3997)	0	1	320	1
Bin	(3997)	1	0	24468	1
Bin	(3996)	0	1	407	1
Bin	(3996)	1	0	24381	1
Bin	(3995)	0	1	473	1
Bin	(3995)	1	0	24315	1
Bin	(3994)	0	1	251	1
Bin	(3994)	1	0	24537	1
Bin	(3993)	0	1	334	1
Bin	(3993)	1	0	24454	1
Bin	(3992)	0	1	424	1
Bin	(3992)	1	0	24364	1
Bin	(3991)	0	1	492	1
Bin	(3991)	1	0	24296	1
Bin	(3990)	0	1	260	1
Bin	(3990)	1	0	24528	1
Bin	(3989)	0	1	348	1
Bin	(3989)	1	0	24440	1
Bin	(3988)	0	1	441	1
Bin	(3988)	1	0	24347	1
Bin	(3987)	0	1	511	1
Bin	(3987)	1	0	24277	1
Bin	(3986)	0	1	269	1
Bin	(3986)	1	0	24519	1
Bin	(3985)	0	1	362	1
Bin	(3985)	1	0	24426	1
Bin	(3984)	0	1	458	1
Bin	(3984)	1	0	24330	1
Bin	(3983)	0	1	530	1
Bin	(3983)	1	0	24258	1
Bin	(3982)	0	1	375	1
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Bin	(1665)	1	0	16504	1
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Bin	(1658)	1	0	19693	1
Bin	(1657)	0	1	7852	1
Bin	(1657)	1	0	16936	1
Bin	(1656)	0	1	10449	1
Bin	(1656)	1	0	14339	1
Bin	(1655)	0	1	11513	1
Bin	(1655)	1	0	13275	1
Bin	(1654)	0	1	6868	1
Bin	(1654)	1	0	17920	1
Bin	(1653)	0	1	8331	1
Bin	(1653)	1	0	16457	1
Bin	(1652)	0	1	10000	1
Bin	(1652)	1	0	14788	1
Bin	(1651)	0	1	11996	1
Bin	(1651)	1	0	12792	1
Bin	(1650)	0	1	9648	1
Bin	(1650)	1	0	15140	1
Bin	(1649)	0	1	7878	1
Bin	(1649)	1	0	16910	1
Bin	(1648)	0	1	7659	1
Bin	(1648)	1	0	17129	1
Bin	(1647)	0	1	9191	1
Bin	(1647)	1	0	15597	1
Bin	(1646)	0	1	8	1
Bin	(1646)	1	0	24780	1
Bin	(1645)	0	1	8358	1
Bin	(1645)	1	0	16430	1
Bin	(1644)	0	1	8146	1
Bin	(1644)	1	0	16642	1
Bin	(1643)	0	1	11563	1
Bin	(1643)	1	0	13225	1
Bin	(1642)	0	1	2796	1
Bin	(1642)	1	0	21992	1
Bin	(1641)	0	1	7898	1
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Bin	(1640)	0	1	10519	1
Bin	(1640)	1	0	14269	1
Bin	(1639)	0	1	12058	1
Bin	(1639)	1	0	12730	1
Bin	(1638)	0	1	5607	1
Bin	(1638)	1	0	19181	1
Bin	(1637)	0	1	7911	1
Bin	(1637)	1	0	16877	1
Bin	(1636)	0	1	10062	1
Bin	(1636)	1	0	14726	1
Bin	(1635)	0	1	11601	1
Bin	(1635)	1	0	13187	1
Bin	(1634)	0	1	9317	1
Bin	(1634)	1	0	15471	1
Bin	(1633)	0	1	8403	1
Bin	(1633)	1	0	16385	1
Bin	(1632)	0	1	10081	1
Bin	(1632)	1	0	14707	1
Bin	(1631)	0	1	12100	1
Bin	(1631)	1	0	12688	1
Bin	(1630)	0	1	8852	1
Bin	(1630)	1	0	15936	1
Bin	(1629)	0	1	7937	1
Bin	(1629)	1	0	16851	1
Bin	(1628)	0	1	10576	1
Bin	(1628)	1	0	14212	1
Bin	(1627)	0	1	12121	1
Bin	(1627)	1	0	12667	1
Bin	(1626)	0	1	8434	1
Bin	(1626)	1	0	16354	1
Bin	(1625)	0	1	7949	1
Bin	(1625)	1	0	16839	1
Bin	(1624)	0	1	10110	1
Bin	(1624)	1	0	14678	1
Bin	(1623)	0	1	11657	1
Bin	(1623)	1	0	13131	1
Bin	(1622)	0	1	6569	1
Bin	(1622)	1	0	18219	1
Bin	(1621)	0	1	8450	1
Bin	(1621)	1	0	16338	1
Bin	(1620)	0	1	10127	1
Bin	(1620)	1	0	14661	1
Bin	(1619)	0	1	12167	1
Bin	(1619)	1	0	12621	1
Bin	(1618)	0	1	2879	1
Bin	(1618)	1	0	21909	1
Bin	(1617)	0	1	8468	1
Bin	(1617)	1	0	16320	1
Bin	(1616)	0	1	10152	1
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Bin	(1615)	1	0	12598	1
Bin	(1614)	0	1	7991	1
Bin	(1614)	1	0	16797	1
Bin	(1613)	0	1	7990	1
Bin	(1613)	1	0	16798	1
Bin	(1612)	0	1	10655	1
Bin	(1612)	1	0	14133	1
Bin	(1611)	0	1	12212	1
Bin	(1611)	1	0	12576	1
Bin	(1610)	0	1	5704	1
Bin	(1610)	1	0	19084	1
Bin	(1609)	0	1	8003	1
Bin	(1609)	1	0	16785	1
Bin	(1608)	0	1	10179	1
Bin	(1608)	1	0	14609	1
Bin	(1607)	0	1	12234	1
Bin	(1607)	1	0	12554	1
Bin	(1606)	0	1	6624	1
Bin	(1606)	1	0	18164	1
Bin	(1605)	0	1	8020	1
Bin	(1605)	1	0	16768	1
Bin	(1604)	0	1	10696	1
Bin	(1604)	1	0	14092	1
Bin	(1603)	0	1	12256	1
Bin	(1603)	1	0	12532	1
Bin	(1602)	0	1	6559	1
Bin	(1602)	1	0	18229	1
Bin	(1601)	0	1	6134	1
Bin	(1601)	1	0	18654	1
Bin	(1600)	0	1	10715	1
Bin	(1600)	1	0	14073	1
Bin	(1599)	0	1	11775	1
Bin	(1599)	1	0	13013	1
Bin	(1598)	0	1	8968	1
Bin	(1598)	1	0	15820	1
Bin	(1597)	0	1	8042	1
Bin	(1597)	1	0	16746	1
Bin	(1596)	0	1	10227	1
Bin	(1596)	1	0	14561	1

---

Signal:

 PARITY_WRITE

	From	To	Count	Threshold
Bin	0	1	90531	1
Bin	1	0	90812	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	15339	1
Bin	1	0	11569	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	7513	1
Bin	1	0	9114	1