NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 4956
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 75
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1527
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10341235
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10326256
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 14979
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 95805
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 94835
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 970
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 682092
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 673009
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 9083
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85807
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84550
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1257
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 5271
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 543
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 4728
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	75	1
Bin	False	1527	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10326256	1
Bin	False	14979	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	94835	1
Bin	False	970	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	673009	1
Bin	False	9083	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84550	1
Bin	False	1257	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	543	1
Bin	False	4728	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	113	1
Bin	(31)	1	0	278	1
Bin	(30)	0	1	115	1
Bin	(30)	1	0	280	1
Bin	(29)	0	1	120	1
Bin	(29)	1	0	285	1
Bin	(28)	0	1	132	1
Bin	(28)	1	0	297	1
Bin	(27)	0	1	128	1
Bin	(27)	1	0	293	1
Bin	(26)	0	1	123	1
Bin	(26)	1	0	288	1
Bin	(25)	0	1	141	1
Bin	(25)	1	0	306	1
Bin	(24)	0	1	122	1
Bin	(24)	1	0	287	1
Bin	(23)	0	1	131	1
Bin	(23)	1	0	296	1
Bin	(22)	0	1	119	1
Bin	(22)	1	0	284	1
Bin	(21)	0	1	132	1
Bin	(21)	1	0	297	1
Bin	(20)	0	1	128	1
Bin	(20)	1	0	293	1
Bin	(19)	0	1	126	1
Bin	(19)	1	0	291	1
Bin	(18)	0	1	126	1
Bin	(18)	1	0	291	1
Bin	(17)	0	1	120	1
Bin	(17)	1	0	285	1
Bin	(16)	0	1	123	1
Bin	(16)	1	0	288	1
Bin	(15)	0	1	119	1
Bin	(15)	1	0	284	1
Bin	(14)	0	1	119	1
Bin	(14)	1	0	284	1
Bin	(13)	0	1	125	1
Bin	(13)	1	0	290	1
Bin	(12)	0	1	121	1
Bin	(12)	1	0	286	1
Bin	(11)	0	1	125	1
Bin	(11)	1	0	290	1
Bin	(10)	0	1	117	1
Bin	(10)	1	0	282	1
Bin	(9)	0	1	126	1
Bin	(9)	1	0	291	1
Bin	(8)	0	1	127	1
Bin	(8)	1	0	292	1
Bin	(7)	0	1	127	1
Bin	(7)	1	0	292	1
Bin	(6)	0	1	112	1
Bin	(6)	1	0	277	1
Bin	(5)	0	1	124	1
Bin	(5)	1	0	289	1
Bin	(4)	0	1	127	1
Bin	(4)	1	0	292	1
Bin	(3)	0	1	122	1
Bin	(3)	1	0	287	1
Bin	(2)	0	1	127	1
Bin	(2)	1	0	292	1
Bin	(1)	0	1	121	1
Bin	(1)	1	0	286	1
Bin	(0)	0	1	119	1
Bin	(0)	1	0	284	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	281	1
Bin	(31)	1	0	436	1
Bin	(30)	0	1	292	1
Bin	(30)	1	0	447	1
Bin	(29)	0	1	212	1
Bin	(29)	1	0	367	1
Bin	(28)	0	1	757	1
Bin	(28)	1	0	906	1
Bin	(27)	0	1	585	1
Bin	(27)	1	0	734	1
Bin	(26)	0	1	659	1
Bin	(26)	1	0	811	1
Bin	(25)	0	1	641	1
Bin	(25)	1	0	792	1
Bin	(24)	0	1	603	1
Bin	(24)	1	0	755	1
Bin	(23)	0	1	691	1
Bin	(23)	1	0	841	1
Bin	(22)	0	1	803	1
Bin	(22)	1	0	953	1
Bin	(21)	0	1	775	1
Bin	(21)	1	0	925	1
Bin	(20)	0	1	769	1
Bin	(20)	1	0	920	1
Bin	(19)	0	1	803	1
Bin	(19)	1	0	950	1
Bin	(18)	0	1	749	1
Bin	(18)	1	0	897	1
Bin	(17)	0	1	653	1
Bin	(17)	1	0	806	1
Bin	(16)	0	1	485	1
Bin	(16)	1	0	638	1
Bin	(15)	0	1	528	1
Bin	(15)	1	0	681	1
Bin	(14)	0	1	518	1
Bin	(14)	1	0	670	1
Bin	(13)	0	1	508	1
Bin	(13)	1	0	662	1
Bin	(12)	0	1	505	1
Bin	(12)	1	0	660	1
Bin	(11)	0	1	630	1
Bin	(11)	1	0	784	1
Bin	(10)	0	1	428	1
Bin	(10)	1	0	581	1
Bin	(9)	0	1	892	1
Bin	(9)	1	0	1039	1
Bin	(8)	0	1	698	1
Bin	(8)	1	0	850	1
Bin	(7)	0	1	1187	1
Bin	(7)	1	0	1328	1
Bin	(6)	0	1	818	1
Bin	(6)	1	0	963	1
Bin	(5)	0	1	659	1
Bin	(5)	1	0	810	1
Bin	(4)	0	1	482	1
Bin	(4)	1	0	636	1
Bin	(3)	0	1	894	1
Bin	(3)	1	0	1041	1
Bin	(2)	0	1	564	1
Bin	(2)	1	0	714	1
Bin	(1)	0	1	820	1
Bin	(1)	1	0	967	1
Bin	(0)	0	1	1108	1
Bin	(0)	1	0	1253	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	468	1
Bin	1	0	633	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101611	1
Bin	(4)	1	0	5033389	1
Bin	(3)	0	1	128538	1
Bin	(3)	1	0	5006452	1
Bin	(2)	0	1	109217	1
Bin	(2)	1	0	5025909	1
Bin	(1)	0	1	4895653	1
Bin	(1)	1	0	239759	1
Bin	(0)	0	1	3845811	1
Bin	(0)	1	0	1290205	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11314	1
Bin	1	0	11507	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	15039	1
Bin	(31)	1	0	319025	1
Bin	(30)	0	1	16359	1
Bin	(30)	1	0	317709	1
Bin	(29)	0	1	14996	1
Bin	(29)	1	0	319068	1
Bin	(28)	0	1	21939	1
Bin	(28)	1	0	312139	1
Bin	(27)	0	1	20700	1
Bin	(27)	1	0	313378	1
Bin	(26)	0	1	19580	1
Bin	(26)	1	0	314494	1
Bin	(25)	0	1	21852	1
Bin	(25)	1	0	312230	1
Bin	(24)	0	1	21142	1
Bin	(24)	1	0	312920	1
Bin	(23)	0	1	20618	1
Bin	(23)	1	0	313444	1
Bin	(22)	0	1	21415	1
Bin	(22)	1	0	312657	1
Bin	(21)	0	1	20778	1
Bin	(21)	1	0	313286	1
Bin	(20)	0	1	20850	1
Bin	(20)	1	0	313220	1
Bin	(19)	0	1	36154	1
Bin	(19)	1	0	297918	1
Bin	(18)	0	1	41938	1
Bin	(18)	1	0	292132	1
Bin	(17)	0	1	39470	1
Bin	(17)	1	0	294602	1
Bin	(16)	0	1	82454	1
Bin	(16)	1	0	251624	1
Bin	(15)	0	1	18912	1
Bin	(15)	1	0	315154	1
Bin	(14)	0	1	20328	1
Bin	(14)	1	0	313738	1
Bin	(13)	0	1	19116	1
Bin	(13)	1	0	314952	1
Bin	(12)	0	1	19179	1
Bin	(12)	1	0	314897	1
Bin	(11)	0	1	41635	1
Bin	(11)	1	0	292435	1
Bin	(10)	0	1	40314	1
Bin	(10)	1	0	293746	1
Bin	(9)	0	1	47131	1
Bin	(9)	1	0	286935	1
Bin	(8)	0	1	50280	1
Bin	(8)	1	0	283794	1
Bin	(7)	0	1	43972	1
Bin	(7)	1	0	290098	1
Bin	(6)	0	1	44633	1
Bin	(6)	1	0	289441	1
Bin	(5)	0	1	45443	1
Bin	(5)	1	0	288637	1
Bin	(4)	0	1	50548	1
Bin	(4)	1	0	283526	1
Bin	(3)	0	1	52294	1
Bin	(3)	1	0	281782	1
Bin	(2)	0	1	56486	1
Bin	(2)	1	0	277602	1
Bin	(1)	0	1	94202	1
Bin	(1)	1	0	239867	1
Bin	(0)	0	1	82909	1
Bin	(0)	1	0	251182	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3352	1
Bin	(4)	1	0	3517	1
Bin	(3)	0	1	113	1
Bin	(3)	1	0	278	1
Bin	(2)	0	1	5327	1
Bin	(2)	1	0	5492	1
Bin	(1)	0	1	3959	1
Bin	(1)	1	0	3959	1
Bin	(0)	0	1	11227	1
Bin	(0)	1	0	11392	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	281	1
Bin	(31)	1	0	436	1
Bin	(30)	0	1	292	1
Bin	(30)	1	0	447	1
Bin	(29)	0	1	212	1
Bin	(29)	1	0	367	1
Bin	(28)	0	1	757	1
Bin	(28)	1	0	906	1
Bin	(27)	0	1	585	1
Bin	(27)	1	0	734	1
Bin	(26)	0	1	659	1
Bin	(26)	1	0	811	1
Bin	(25)	0	1	641	1
Bin	(25)	1	0	792	1
Bin	(24)	0	1	603	1
Bin	(24)	1	0	755	1
Bin	(23)	0	1	691	1
Bin	(23)	1	0	841	1
Bin	(22)	0	1	803	1
Bin	(22)	1	0	953	1
Bin	(21)	0	1	775	1
Bin	(21)	1	0	925	1
Bin	(20)	0	1	769	1
Bin	(20)	1	0	920	1
Bin	(19)	0	1	803	1
Bin	(19)	1	0	950	1
Bin	(18)	0	1	749	1
Bin	(18)	1	0	897	1
Bin	(17)	0	1	653	1
Bin	(17)	1	0	806	1
Bin	(16)	0	1	485	1
Bin	(16)	1	0	638	1
Bin	(15)	0	1	528	1
Bin	(15)	1	0	681	1
Bin	(14)	0	1	518	1
Bin	(14)	1	0	670	1
Bin	(13)	0	1	508	1
Bin	(13)	1	0	662	1
Bin	(12)	0	1	505	1
Bin	(12)	1	0	660	1
Bin	(11)	0	1	630	1
Bin	(11)	1	0	784	1
Bin	(10)	0	1	428	1
Bin	(10)	1	0	581	1
Bin	(9)	0	1	892	1
Bin	(9)	1	0	1039	1
Bin	(8)	0	1	698	1
Bin	(8)	1	0	850	1
Bin	(7)	0	1	1187	1
Bin	(7)	1	0	1328	1
Bin	(6)	0	1	818	1
Bin	(6)	1	0	963	1
Bin	(5)	0	1	659	1
Bin	(5)	1	0	810	1
Bin	(4)	0	1	482	1
Bin	(4)	1	0	636	1
Bin	(3)	0	1	894	1
Bin	(3)	1	0	1041	1
Bin	(2)	0	1	564	1
Bin	(2)	1	0	714	1
Bin	(1)	0	1	820	1
Bin	(1)	1	0	967	1
Bin	(0)	0	1	1108	1
Bin	(0)	1	0	1253	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	75	1
Bin	1	0	240	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	17	1
Bin	(20)	1	0	672	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	688	1
Bin	(18)	0	1	3	1
Bin	(18)	1	0	686	1
Bin	(17)	0	1	23	1
Bin	(17)	1	0	666	1
Bin	(16)	0	1	27	1
Bin	(16)	1	0	662	1
Bin	(15)	0	1	30	1
Bin	(15)	1	0	659	1
Bin	(14)	0	1	29	1
Bin	(14)	1	0	660	1
Bin	(13)	0	1	14	1
Bin	(13)	1	0	675	1
Bin	(12)	0	1	13	1
Bin	(12)	1	0	676	1
Bin	(11)	0	1	35	1
Bin	(11)	1	0	654	1
Bin	(10)	0	1	43	1
Bin	(10)	1	0	646	1
Bin	(9)	0	1	24	1
Bin	(9)	1	0	665	1
Bin	(8)	0	1	32	1
Bin	(8)	1	0	657	1
Bin	(7)	0	1	42	1
Bin	(7)	1	0	647	1
Bin	(6)	0	1	52	1
Bin	(6)	1	0	637	1
Bin	(5)	0	1	88	1
Bin	(5)	1	0	601	1
Bin	(4)	0	1	146	1
Bin	(4)	1	0	543	1
Bin	(3)	0	1	293	1
Bin	(3)	1	0	396	1
Bin	(2)	0	1	369	1
Bin	(2)	1	0	320	1
Bin	(1)	0	1	273	1
Bin	(1)	1	0	416	1
Bin	(0)	0	1	228	1
Bin	(0)	1	0	461	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	1235	1
Bin	1	0	1090	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	1198	1
Bin	1	0	1363	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	596	1
Bin	True	True	75	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	14979	1
Bin	True	10326256	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	970	1
Bin	True	94835	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	9083	1
Bin	True	673009	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1257	1
Bin	True	84550	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	4728	1
Bin	True	543	1