NVC code coverage report

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Current Instance	Statement	Branch	Toggle	Expression	FSM state	Functional	Average
CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_SSP_GENERATOR	100.0 % (55/55)	100.0 % (56/56)	100.0 % (262/262)	100.0 % (65/65)	N.A.	N.A.	100.0 % (438/438)

Current Instance

Statement

Branch

Toggle

Expression

FSM state

Functional

Average

CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_SSP_GENERATOR

100.0 % (55/55)

100.0 % (56/56)

100.0 % (262/262)

100.0 % (65/65)

N.A.

100.0 % (438/438)

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Statement

Branch

Toggle

Expression

FSM state

Functional

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 172 to 175:

172:    btmc_meas_running_d <= '0' when (btmc_reset = '1') else 
173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else 
174:                           '0' when (tx_trigger = '1') else 
175:                           btmc_meas_running_q;

Count: 22933192
Threshold: 1

Signal assignment statement on line 172:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else
Count: 84396
Threshold: 1

Signal assignment statement on line 173:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

Count: 4302
Threshold: 1

Signal assignment statement on line 174:

174: '0' when (tx_trigger = '1') else
Count: 11403906
Threshold: 1

Signal assignment statement on line 175:

175: btmc_meas_running_q;
Count: 11440588
Threshold: 1

If statement on lines 179 to 183:

179:        if (rst_n = '0') then 
180:            btmc_meas_running_q <= '0'; 
181:        elsif (rising_edge(clk_sys)) then 
182:            btmc_meas_running_q <= btmc_meas_running_d; 
183:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 180:

180: btmc_meas_running_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 182:

182: btmc_meas_running_q <= btmc_meas_running_d;
Count: 547174334
Threshold: 1

If statement on lines 192 to 194:

192:    btmc_d <= (others => '0') when (btmc_reset = '1') else 
193:                     btmc_add when (btmc_meas_running_q = '1') else 
194:                       btmc_q;

Count: 496819
Threshold: 1

Signal assignment statement on line 192:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else
Count: 31390
Threshold: 1

Signal assignment statement on line 193:

193: btmc_add when (btmc_meas_running_q = '1') else
Count: 425547
Threshold: 1

Signal assignment statement on line 194:

194: btmc_q;
Count: 39882
Threshold: 1

Signal assignment statement on line 196:

196: btmc_add <= std_logic_vector(unsigned(btmc_q) + 1);
Count: 219202
Threshold: 1

If statement on lines 198 to 199:

198:    btmc_ce <= '1' when (btmc_d /= btmc_q) else 
199:               '0';

Count: 436803
Threshold: 1

Signal assignment statement on line 198:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else
Count: 217601
Threshold: 1

Signal assignment statement on line 199:

199: '0';
Count: 219202
Threshold: 1

If statement on lines 203 to 209:

203:        if (rst_n = '0') then 
204:            btmc_q <= (others => '0'); 
...
208:            end if; 
209:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 204:

204: btmc_q <= (others => '0');
Count: 2422674
Threshold: 1

If statement on lines 206 to 208:

206:            if (btmc_ce = '1') then 
207:                btmc_q <= btmc_d; 
208:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 207:

207: btmc_q <= btmc_d;
Count: 215478
Threshold: 1

If statement on lines 217 to 219:

217:    first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else 
218:                   '0' when (sspc_expired = '1') else 
219:                   first_ssp_q;

Count: 23270615
Threshold: 1

Signal assignment statement on line 217:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else
Count: 6453
Threshold: 1

Signal assignment statement on line 218:

218: '0' when (sspc_expired = '1') else
Count: 22489472
Threshold: 1

Signal assignment statement on line 219:

219: first_ssp_q;
Count: 774690
Threshold: 1

If statement on lines 223 to 227:

223:        if (rst_n = '0') then 
224:            first_ssp_q <= '0'; 
225:        elsif (rising_edge(clk_sys)) then 
226:            first_ssp_q <= first_ssp_d; 
227:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 224:

224: first_ssp_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 226:

226: first_ssp_q <= first_ssp_d;
Count: 547174334
Threshold: 1

If statement on lines 236 to 238:

236:    sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else 
237:                  '0' when (ssp_enable = '0') else 
238:                  sspc_ena_q;

Count: 22886583
Threshold: 1

Signal assignment statement on line 236:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else
Count: 4302
Threshold: 1

Signal assignment statement on line 237:

237: '0' when (ssp_enable = '0') else
Count: 22485820
Threshold: 1

Signal assignment statement on line 238:

238: sspc_ena_q;
Count: 396461
Threshold: 1

If statement on lines 242 to 246:

242:        if (rst_n = '0') then 
243:            sspc_ena_q <= '0'; 
244:        elsif (rising_edge(clk_sys)) then 
245:            sspc_ena_q <= sspc_ena_d; 
246:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 243:

243: sspc_ena_q <= '0';
Count: 2422674
Threshold: 1

Signal assignment statement on line 245:

245: sspc_ena_q <= sspc_ena_d;
Count: 547174334
Threshold: 1

If statement on lines 260 to 262:

260:    sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1') 
261:                                                                    else 
262:                      unsigned(btmc_q);

Count: 222947
Threshold: 1

Signal assignment statement on line 260:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')
Count: 24952
Threshold: 1

Signal assignment statement on line 262:

262: unsigned(btmc_q);
Count: 197995
Threshold: 1

If statement on lines 264 to 265:

264:    sspc_expired <= '1' when (sspc_q >= sspc_threshold) else 
265:                    '0';

Count: 9247257
Threshold: 1

Signal assignment statement on line 264:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else
Count: 197984
Threshold: 1

Signal assignment statement on line 265:

265: '0';
Count: 9049273
Threshold: 1

Signal assignment statement on line 267:

267: sspc_add <= sspc_q + 1;
Count: 9052249
Threshold: 1

If statement on lines 274 to 276:

274:    sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else 
275:                    sspc_add when (sspc_ena_q = '1') else 
276:                      sspc_q;

Count: 18170417
Threshold: 1

Signal assignment statement on line 274:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else
Count: 452071
Threshold: 1

Signal assignment statement on line 275:

275: sspc_add when (sspc_ena_q = '1') else
Count: 17705750
Threshold: 1

Signal assignment statement on line 276:

276: sspc_q;
Count: 12596
Threshold: 1

If statement on lines 278 to 279:

278:    sspc_ce <= '1' when (sspc_d /= sspc_q) else 
279:               '0';

Count: 18102897
Threshold: 1

Signal assignment statement on line 278:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else
Count: 9052249
Threshold: 1

Signal assignment statement on line 279:

279: '0';
Count: 9050648
Threshold: 1

If statement on lines 283 to 289:

283:        if (rst_n = '0') then 
284:            sspc_q <= C_SSPC_RST_VAL; 
...
288:            end if; 
289:        end if;

Count: 1096781321
Threshold: 1

Signal assignment statement on line 284:

284: sspc_q <= C_SSPC_RST_VAL;
Count: 2422674
Threshold: 1

If statement on lines 286 to 288:

286:            if (sspc_ce = '1') then 
287:                sspc_q <= sspc_d; 
288:            end if;

Count: 547174334
Threshold: 1

Signal assignment statement on line 287:

287: sspc_q <= sspc_d;
Count: 9050459
Threshold: 1

If statement on lines 295 to 296:

295:    sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else 
296:                  '0';

Count: 403472
Threshold: 1

Signal assignment statement on line 295:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else
Count: 195230
Threshold: 1

Signal assignment statement on line 296:

296: '0';
Count: 208242
Threshold: 1

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 172:

172: btmc_meas_running_d <= '0' when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	84396	1
Bin	False	22848796	1

"if" / "when" / "else" condition on line 173:

173:                           '1' when (dbt_measure_start = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	4302	1
Bin	False	22844494	1

"if" / "when" / "else" condition on line 174:

174: '0' when (tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	11403906	1
Bin	False	11440588	1

"if" / "when" / "else" condition on line 179:

179: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 181:

181: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 192:

192: btmc_d <= (others => '0') when (btmc_reset = '1') else

	Evaluated to	Count	Threshold
Bin	True	31390	1
Bin	False	465429	1

"if" / "when" / "else" condition on line 193:

193: btmc_add when (btmc_meas_running_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	425547	1
Bin	False	39882	1

"if" / "when" / "else" condition on line 198:

198: btmc_ce <= '1' when (btmc_d /= btmc_q) else

	Evaluated to	Count	Threshold
Bin	True	217601	1
Bin	False	219202	1

"if" / "when" / "else" condition on line 203:

203: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 205:

205: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 206:

206: if (btmc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	215478	1
Bin	False	546958856	1

"if" / "when" / "else" condition on line 217:

217: first_ssp_d <= '1' when (gen_first_ssp = '1'and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	6453	1
Bin	False	23264162	1

"if" / "when" / "else" condition on line 218:

218: '0' when (sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	22489472	1
Bin	False	774690	1

"if" / "when" / "else" condition on line 223:

223: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 225:

225: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 236:

236: sspc_ena_d <= '1' when (gen_first_ssp = '1' and tx_trigger = '1') else

	Evaluated to	Count	Threshold
Bin	True	4302	1
Bin	False	22882281	1

"if" / "when" / "else" condition on line 237:

237: '0' when (ssp_enable = '0') else

	Evaluated to	Count	Threshold
Bin	True	22485820	1
Bin	False	396461	1

"if" / "when" / "else" condition on line 242:

242: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 244:

244: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 260:

260: sspc_threshold <= resize(unsigned(ssp_delay), G_SSP_CTRS_WIDTH) when (first_ssp_q = '1')

	Evaluated to	Count	Threshold
Bin	True	24952	1
Bin	False	197995	1

"if" / "when" / "else" condition on line 264:

264: sspc_expired <= '1' when (sspc_q >= sspc_threshold) else

	Evaluated to	Count	Threshold
Bin	True	197984	1
Bin	False	9049273	1

"if" / "when" / "else" condition on line 274:

274: sspc_d <= C_SSPC_RST_VAL when (btmc_reset = '1' or sspc_expired = '1') else

	Evaluated to	Count	Threshold
Bin	True	452071	1
Bin	False	17718346	1

"if" / "when" / "else" condition on line 275:

275: sspc_add when (sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	17705750	1
Bin	False	12596	1

"if" / "when" / "else" condition on line 278:

278: sspc_ce <= '1' when (sspc_d /= sspc_q) else

	Evaluated to	Count	Threshold
Bin	True	9052249	1
Bin	False	9050648	1

"if" / "when" / "else" condition on line 283:

283: if (rst_n = '0') then

	Evaluated to	Count	Threshold
Bin	True	2422674	1
Bin	False	1094358647	1

"if" / "when" / "else" condition on line 285:

285: elsif (rising_edge(clk_sys)) then

	Evaluated to	Count	Threshold
Bin	True	547174334	1
Bin	False	547184313	1

"if" / "when" / "else" condition on line 286:

286: if (sspc_ce = '1') then

	Evaluated to	Count	Threshold
Bin	True	9050459	1
Bin	False	538123875	1

"if" / "when" / "else" condition on line 295:

295: sample_sec <= '1' when (sspc_expired = '1' and sspc_ena_q = '1') else

	Evaluated to	Count	Threshold
Bin	True	195230	1
Bin	False	208242	1

Uncovered toggles:

Excluded toggles:

Port:

CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

BTMC_RESET

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

DBT_MEASURE_START

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

GEN_FIRST_SSP

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

SSP_DELAY

	Element	From	To	Threshold	Excluded due to
Bin	(8)	0	1	1	Exclude file
Bin	(8)	1	0	1	Exclude file
Bin	(7)	0	1	1	Exclude file
Bin	(7)	1	0	1	Exclude file
Bin	(6)	0	1	1	Exclude file
Bin	(6)	1	0	1	Exclude file
Bin	(5)	0	1	1	Exclude file
Bin	(5)	1	0	1	Exclude file
Bin	(4)	0	1	1	Exclude file
Bin	(4)	1	0	1	Exclude file
Bin	(3)	0	1	1	Exclude file
Bin	(3)	1	0	1	Exclude file
Bin	(2)	0	1	1	Exclude file
Bin	(2)	1	0	1	Exclude file
Bin	(1)	0	1	1	Exclude file
Bin	(1)	1	0	1	Exclude file
Bin	(0)	0	1	1	Exclude file
Bin	(0)	1	0	1	Exclude file

Port:

SSP_ENABLE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Port:

TX_TRIGGER

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

Covered toggles:

Port:

SAMPLE_SEC

	From	To	Count	Threshold
Bin	0	1	195230	1
Bin	1	0	196831	1

Signal:

BTMC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	85	1
Bin	(10)	1	0	1686	1
Bin	(9)	0	1	160	1
Bin	(9)	1	0	1761	1
Bin	(8)	0	1	332	1
Bin	(8)	1	0	1933	1
Bin	(7)	0	1	679	1
Bin	(7)	1	0	2280	1
Bin	(6)	0	1	1373	1
Bin	(6)	1	0	2974	1
Bin	(5)	0	1	3500	1
Bin	(5)	1	0	5101	1
Bin	(4)	0	1	6342	1
Bin	(4)	1	0	7943	1
Bin	(3)	0	1	13323	1
Bin	(3)	1	0	14924	1
Bin	(2)	0	1	27236	1
Bin	(2)	1	0	28837	1
Bin	(1)	0	1	53165	1
Bin	(1)	1	0	54766	1
Bin	(0)	0	1	107579	1
Bin	(0)	1	0	109180	1

Signal:

BTMC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	85	1
Bin	(10)	1	0	1686	1
Bin	(9)	0	1	160	1
Bin	(9)	1	0	1761	1
Bin	(8)	0	1	332	1
Bin	(8)	1	0	1933	1
Bin	(7)	0	1	679	1
Bin	(7)	1	0	2280	1
Bin	(6)	0	1	1373	1
Bin	(6)	1	0	2974	1
Bin	(5)	0	1	3500	1
Bin	(5)	1	0	5101	1
Bin	(4)	0	1	6342	1
Bin	(4)	1	0	7943	1
Bin	(3)	0	1	13323	1
Bin	(3)	1	0	14924	1
Bin	(2)	0	1	27236	1
Bin	(2)	1	0	28837	1
Bin	(1)	0	1	53165	1
Bin	(1)	1	0	54766	1
Bin	(0)	0	1	107579	1
Bin	(0)	1	0	109180	1

Signal:

BTMC_ADD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	85	1
Bin	(10)	1	0	1686	1
Bin	(9)	0	1	160	1
Bin	(9)	1	0	1761	1
Bin	(8)	0	1	332	1
Bin	(8)	1	0	1933	1
Bin	(7)	0	1	679	1
Bin	(7)	1	0	2280	1
Bin	(6)	0	1	1373	1
Bin	(6)	1	0	2974	1
Bin	(5)	0	1	3500	1
Bin	(5)	1	0	5101	1
Bin	(4)	0	1	6350	1
Bin	(4)	1	0	7951	1
Bin	(3)	0	1	13330	1
Bin	(3)	1	0	14931	1
Bin	(2)	0	1	27243	1
Bin	(2)	1	0	28844	1
Bin	(1)	0	1	54452	1
Bin	(1)	1	0	56053	1
Bin	(0)	0	1	109180	1
Bin	(0)	1	0	107579	1

Signal:

BTMC_CE

	From	To	Count	Threshold
Bin	0	1	217601	1
Bin	1	0	219202	1

Signal:

BTMC_MEAS_RUNNING_D

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

Signal:

BTMC_MEAS_RUNNING_Q

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

Signal:

SSPC_D

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2780	1
Bin	(10)	1	0	4381	1
Bin	(9)	0	1	5245	1
Bin	(9)	1	0	6846	1
Bin	(8)	0	1	10884	1
Bin	(8)	1	0	12485	1
Bin	(7)	0	1	22204	1
Bin	(7)	1	0	23805	1
Bin	(6)	0	1	44937	1
Bin	(6)	1	0	46538	1
Bin	(5)	0	1	153612	1
Bin	(5)	1	0	155213	1
Bin	(4)	0	1	249938	1
Bin	(4)	1	0	251539	1
Bin	(3)	0	1	557410	1
Bin	(3)	1	0	559011	1
Bin	(2)	0	1	1179421	1
Bin	(2)	1	0	1181022	1
Bin	(1)	0	1	2231931	1
Bin	(1)	1	0	2233532	1
Bin	(0)	0	1	4462418	1
Bin	(0)	1	0	4460817	1

Signal:

SSPC_Q

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2780	1
Bin	(10)	1	0	4381	1
Bin	(9)	0	1	5245	1
Bin	(9)	1	0	6846	1
Bin	(8)	0	1	10884	1
Bin	(8)	1	0	12485	1
Bin	(7)	0	1	22204	1
Bin	(7)	1	0	23805	1
Bin	(6)	0	1	44937	1
Bin	(6)	1	0	46538	1
Bin	(5)	0	1	153612	1
Bin	(5)	1	0	155213	1
Bin	(4)	0	1	249938	1
Bin	(4)	1	0	251539	1
Bin	(3)	0	1	557410	1
Bin	(3)	1	0	559011	1
Bin	(2)	0	1	1179421	1
Bin	(2)	1	0	1181022	1
Bin	(1)	0	1	2231931	1
Bin	(1)	1	0	2233532	1
Bin	(0)	0	1	4462418	1
Bin	(0)	1	0	4460817	1

Signal:

SSPC_CE

	From	To	Count	Threshold
Bin	0	1	9050648	1
Bin	1	0	9050648	1

Signal:

SSPC_EXPIRED

	From	To	Count	Threshold
Bin	0	1	197984	1
Bin	1	0	197984	1

Signal:

SSPC_THRESHOLD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	5	1
Bin	(14)	1	0	1606	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	1611	1
Bin	(12)	0	1	20	1
Bin	(12)	1	0	1621	1
Bin	(11)	0	1	40	1
Bin	(11)	1	0	1641	1
Bin	(10)	0	1	85	1
Bin	(10)	1	0	1686	1
Bin	(9)	0	1	160	1
Bin	(9)	1	0	1761	1
Bin	(8)	0	1	345	1
Bin	(8)	1	0	1946	1
Bin	(7)	0	1	700	1
Bin	(7)	1	0	2301	1
Bin	(6)	0	1	1366	1
Bin	(6)	1	0	2967	1
Bin	(5)	0	1	3463	1
Bin	(5)	1	0	5064	1
Bin	(4)	0	1	6160	1
Bin	(4)	1	0	7761	1
Bin	(3)	0	1	12870	1
Bin	(3)	1	0	14471	1
Bin	(2)	0	1	25502	1
Bin	(2)	1	0	27103	1
Bin	(1)	0	1	47589	1
Bin	(1)	1	0	49190	1
Bin	(0)	0	1	96021	1
Bin	(0)	1	0	97622	1

Signal:

SSPC_ADD

	Element	From	To	Count	Threshold
Bin	(14)	0	1	165	1
Bin	(14)	1	0	1766	1
Bin	(13)	0	1	325	1
Bin	(13)	1	0	1926	1
Bin	(12)	0	1	655	1
Bin	(12)	1	0	2256	1
Bin	(11)	0	1	1310	1
Bin	(11)	1	0	2911	1
Bin	(10)	0	1	2780	1
Bin	(10)	1	0	4381	1
Bin	(9)	0	1	5245	1
Bin	(9)	1	0	6846	1
Bin	(8)	0	1	10884	1
Bin	(8)	1	0	12485	1
Bin	(7)	0	1	22205	1
Bin	(7)	1	0	23806	1
Bin	(6)	0	1	44938	1
Bin	(6)	1	0	46539	1
Bin	(5)	0	1	153617	1
Bin	(5)	1	0	155218	1
Bin	(4)	0	1	250586	1
Bin	(4)	1	0	252187	1
Bin	(3)	0	1	557717	1
Bin	(3)	1	0	559318	1
Bin	(2)	0	1	1180033	1
Bin	(2)	1	0	1181634	1
Bin	(1)	0	1	2232061	1
Bin	(1)	1	0	2230460	1
Bin	(0)	0	1	4460817	1
Bin	(0)	1	0	4462418	1

Signal:

FIRST_SSP_D

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

Signal:

FIRST_SSP_Q

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

Signal:

SSPC_ENA_D

	From	To	Count	Threshold
Bin	0	1	3728	1
Bin	1	0	5329	1

Signal:

SSPC_ENA_Q

	From	To	Count	Threshold
Bin	0	1	2151	1
Bin	1	0	3752	1

Uncovered expressions:

Excluded expressions:

Covered expressions:

"=" expression on line 172:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	22848796	1
Bin	True	84396	1

"and" expression on line 173:

 dbt_measure_start = '1' and tx_trigger = '1' 
 <---------LHS--------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11403906	1
Bin	True	False	4302	1
Bin	True	True	4302	1

"=" expression on line 173:

dbt_measure_start = '1'

	Evaluated to	Count	Threshold
Bin	False	22840192	1
Bin	True	8604	1

"=" expression on line 173:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11440588	1
Bin	True	11408208	1

"=" expression on line 174:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11440588	1
Bin	True	11403906	1

"=" expression on line 179:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 192:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	465429	1
Bin	True	31390	1

"=" expression on line 193:

btmc_meas_running_q = '1'

	Evaluated to	Count	Threshold
Bin	False	39882	1
Bin	True	425547	1

"=" expression on line 203:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 206:

btmc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	546958856	1
Bin	True	215478	1

"and" expression on line 217:

 gen_first_ssp = '1'and tx_trigger = '1' 
 <-------LHS------->    <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11551790	1
Bin	True	False	6717	1
Bin	True	True	6453	1

"=" expression on line 217:

gen_first_ssp = '1'

	Evaluated to	Count	Threshold
Bin	False	23257445	1
Bin	True	13170	1

"=" expression on line 217:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11712372	1
Bin	True	11558243	1

"=" expression on line 218:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	774690	1
Bin	True	22489472	1

"=" expression on line 223:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"and" expression on line 236:

 gen_first_ssp = '1' and tx_trigger = '1' 
 <-------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	11429887	1
Bin	True	False	4302	1
Bin	True	True	4302	1

"=" expression on line 236:

gen_first_ssp = '1'

	Evaluated to	Count	Threshold
Bin	False	22877979	1
Bin	True	8604	1

"=" expression on line 236:

tx_trigger = '1'

	Evaluated to	Count	Threshold
Bin	False	11452394	1
Bin	True	11434189	1

"=" expression on line 237:

ssp_enable = '0'

	Evaluated to	Count	Threshold
Bin	False	396461	1
Bin	True	22485820	1

"=" expression on line 242:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 260:

first_ssp_q = '1'

	Evaluated to	Count	Threshold
Bin	False	197995	1
Bin	True	24952	1

"or" expression on line 274:

 btmc_reset = '1' or sspc_expired = '1' 
 <-----LHS------>    <------RHS------->

	LHS	RHS	Count	Threshold
Bin	False	False	17718346	1
Bin	False	True	420870	1
Bin	True	False	3069	1

"=" expression on line 274:

btmc_reset = '1'

	Evaluated to	Count	Threshold
Bin	False	18139216	1
Bin	True	31201	1

"=" expression on line 274:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	17721415	1
Bin	True	449002	1

"=" expression on line 275:

sspc_ena_q = '1'

	Evaluated to	Count	Threshold
Bin	False	12596	1
Bin	True	17705750	1

"=" expression on line 283:

rst_n = '0'

	Evaluated to	Count	Threshold
Bin	False	1094358647	1
Bin	True	2422674	1

"=" expression on line 286:

sspc_ce = '1'

	Evaluated to	Count	Threshold
Bin	False	538123875	1
Bin	True	9050459	1

"and" expression on line 295:

 sspc_expired = '1' and sspc_ena_q = '1' 
 <------LHS------->     <-----RHS------>

	LHS	RHS	Count	Threshold
Bin	False	True	195141	1
Bin	True	False	4994	1
Bin	True	True	195230	1

"=" expression on line 295:

sspc_expired = '1'

	Evaluated to	Count	Threshold
Bin	False	203248	1
Bin	True	200224	1

"=" expression on line 295:

sspc_ena_q = '1'

	Evaluated to	Count	Threshold
Bin	False	13101	1
Bin	True	390371	1

Hierarchy

Instance: CTU_CAN_FD_TB.TB_TOP_CTU_CAN_FD.I_DUT.I_BM_TOP.I_BM_SSP_GENERATOR

File: /__w/CTU-CAN-FD/CTU-CAN-FD/src/bus_management/bm_top.vhd

Details:

The limit of printed items was reached (5000). Total 260336 items are not displayed.

Uncovered statements:

Excluded statements:

Covered statements:

If statement on lines 172 to 175:

Signal assignment statement on line 172:

Signal assignment statement on line 173:

Signal assignment statement on line 174:

Signal assignment statement on line 175:

If statement on lines 179 to 183:

Signal assignment statement on line 180:

Signal assignment statement on line 182:

If statement on lines 192 to 194:

Signal assignment statement on line 192:

Signal assignment statement on line 193:

Signal assignment statement on line 194:

Signal assignment statement on line 196:

If statement on lines 198 to 199:

Signal assignment statement on line 198:

Signal assignment statement on line 199:

If statement on lines 203 to 209:

Signal assignment statement on line 204:

If statement on lines 206 to 208:

Signal assignment statement on line 207:

If statement on lines 217 to 219:

Signal assignment statement on line 217:

Signal assignment statement on line 218:

Signal assignment statement on line 219:

If statement on lines 223 to 227:

Signal assignment statement on line 224:

Signal assignment statement on line 226:

If statement on lines 236 to 238:

Signal assignment statement on line 236:

Signal assignment statement on line 237:

Signal assignment statement on line 238:

If statement on lines 242 to 246:

Signal assignment statement on line 243:

Signal assignment statement on line 245:

If statement on lines 260 to 262:

Signal assignment statement on line 260:

Signal assignment statement on line 262:

If statement on lines 264 to 265:

Signal assignment statement on line 264:

Signal assignment statement on line 265:

Signal assignment statement on line 267:

If statement on lines 274 to 276:

Signal assignment statement on line 274:

Signal assignment statement on line 275:

Signal assignment statement on line 276:

If statement on lines 278 to 279:

Signal assignment statement on line 278:

Signal assignment statement on line 279:

If statement on lines 283 to 289:

Signal assignment statement on line 284:

If statement on lines 286 to 288:

Signal assignment statement on line 287:

If statement on lines 295 to 296:

Signal assignment statement on line 295:

Signal assignment statement on line 296:

Uncovered branches:

Excluded branches:

Covered branches:

"if" / "when" / "else" condition on line 172:

"if" / "when" / "else" condition on line 173:

"if" / "when" / "else" condition on line 174:

"if" / "when" / "else" condition on line 179:

"if" / "when" / "else" condition on line 181:

"if" / "when" / "else" condition on line 192:

"if" / "when" / "else" condition on line 193:

"if" / "when" / "else" condition on line 198:

"if" / "when" / "else" condition on line 203:

"if" / "when" / "else" condition on line 205:

"if" / "when" / "else" condition on line 206:

"if" / "when" / "else" condition on line 217:

"if" / "when" / "else" condition on line 218:

"if" / "when" / "else" condition on line 223: