NVC code coverage report

Signal assignment statement on line 208:

208:    txtb_port_b_data_out <= txtb_port_b_data_out_i; 
Count: 3629
Threshold: 1

---

If statement on lines 277 to 280:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
279:                   else 
280:               '0'; 
Count: 1602
Threshold: 1

---

Signal assignment statement on line 277:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
Count: 64
Threshold: 1

---

Signal assignment statement on line 280:

280:               '0'; 
Count: 1538
Threshold: 1

---

If statement on lines 283 to 285:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
284:                                                 else 
285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 10341213
Threshold: 1

---

Signal assignment statement on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 
Count: 10335251
Threshold: 1

---

Signal assignment statement on line 285:

285:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 5962
Threshold: 1

---

If statement on lines 287 to 289:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
288:                                             else 
289:                           mr_tst_control_twrstb; 
Count: 95893
Threshold: 1

---

Signal assignment statement on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 
Count: 94950
Threshold: 1

---

Signal assignment statement on line 289:

289:                           mr_tst_control_twrstb; 
Count: 943
Threshold: 1

---

If statement on lines 291 to 293:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
292:                                              else 
293:                          mr_tst_wdata_tst_wdata; 
Count: 682070
Threshold: 1

---

Signal assignment statement on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 
Count: 678752
Threshold: 1

---

Signal assignment statement on line 293:

293:                          mr_tst_wdata_tst_wdata; 
Count: 3318
Threshold: 1

---

If statement on lines 296 to 298:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
297:                                                 else 
298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 85785
Threshold: 1

---

Signal assignment statement on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 
Count: 84542
Threshold: 1

---

Signal assignment statement on line 298:

298:                             mr_tst_dest_tst_addr(4 downto 0); 
Count: 1243
Threshold: 1

---

If statement on lines 300 to 302:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
301:                                                     else 
302:                                     (others => '0'); 
Count: 3922
Threshold: 1

---

Signal assignment statement on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 
Count: 528
Threshold: 1

---

Signal assignment statement on line 302:

302:                                     (others => '0'); 
Count: 3394
Threshold: 1

"if" / "when" / "else" condition on lines 277 to 278:

277:    tst_ena <= '1' when (mr_tst_control_tmaena = '1') and 
278:                        (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 

	Evaluated to	Count	Threshold
Bin	True	64	1
Bin	False	1538	1

---

"if" / "when" / "else" condition on line 283:

283:    txtb_port_a_address_i <= txtb_port_a_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	10335251	1
Bin	False	5962	1

---

"if" / "when" / "else" condition on line 287:

287:    txtb_port_a_write_i <= txtb_port_a_write when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	94950	1
Bin	False	943	1

---

"if" / "when" / "else" condition on line 291:

291:    txtb_port_a_data_i <= txtb_port_a_data_in when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	678752	1
Bin	False	3318	1

---

"if" / "when" / "else" condition on line 296:

296:    txtb_port_b_address_i <= txtb_port_b_address when (tst_ena = '0') 

	Evaluated to	Count	Threshold
Bin	True	84542	1
Bin	False	1243	1

---

"if" / "when" / "else" condition on line 300:

300:    mr_tst_rdata_tst_rdata <= txtb_port_b_data_out_i when (tst_ena = '1') 

	Evaluated to	Count	Threshold
Bin	True	528	1
Bin	False	3394	1

Port:

 CLK_SYS

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 RST_N

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_SETTINGS_PCHKE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TMAENA

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_CONTROL_TWRSTB

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_ADDR

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_DEST_TST_MTGT

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 MR_TST_WDATA_TST_WDATA

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_DATA_IN

	Element	From	To	Count	Threshold	Excluded due to
Bin	(31)	0	1	0	1	Exclude file
Bin	(31)	1	0	0	1	Exclude file
Bin	(30)	0	1	0	1	Exclude file
Bin	(30)	1	0	0	1	Exclude file
Bin	(29)	0	1	0	1	Exclude file
Bin	(29)	1	0	0	1	Exclude file
Bin	(28)	0	1	0	1	Exclude file
Bin	(28)	1	0	0	1	Exclude file
Bin	(27)	0	1	0	1	Exclude file
Bin	(27)	1	0	0	1	Exclude file
Bin	(26)	0	1	0	1	Exclude file
Bin	(26)	1	0	0	1	Exclude file
Bin	(25)	0	1	0	1	Exclude file
Bin	(25)	1	0	0	1	Exclude file
Bin	(24)	0	1	0	1	Exclude file
Bin	(24)	1	0	0	1	Exclude file
Bin	(23)	0	1	0	1	Exclude file
Bin	(23)	1	0	0	1	Exclude file
Bin	(22)	0	1	0	1	Exclude file
Bin	(22)	1	0	0	1	Exclude file
Bin	(21)	0	1	0	1	Exclude file
Bin	(21)	1	0	0	1	Exclude file
Bin	(20)	0	1	0	1	Exclude file
Bin	(20)	1	0	0	1	Exclude file
Bin	(19)	0	1	0	1	Exclude file
Bin	(19)	1	0	0	1	Exclude file
Bin	(18)	0	1	0	1	Exclude file
Bin	(18)	1	0	0	1	Exclude file
Bin	(17)	0	1	0	1	Exclude file
Bin	(17)	1	0	0	1	Exclude file
Bin	(16)	0	1	0	1	Exclude file
Bin	(16)	1	0	0	1	Exclude file
Bin	(15)	0	1	0	1	Exclude file
Bin	(15)	1	0	0	1	Exclude file
Bin	(14)	0	1	0	1	Exclude file
Bin	(14)	1	0	0	1	Exclude file
Bin	(13)	0	1	0	1	Exclude file
Bin	(13)	1	0	0	1	Exclude file
Bin	(12)	0	1	0	1	Exclude file
Bin	(12)	1	0	0	1	Exclude file
Bin	(11)	0	1	0	1	Exclude file
Bin	(11)	1	0	0	1	Exclude file
Bin	(10)	0	1	0	1	Exclude file
Bin	(10)	1	0	0	1	Exclude file
Bin	(9)	0	1	0	1	Exclude file
Bin	(9)	1	0	0	1	Exclude file
Bin	(8)	0	1	0	1	Exclude file
Bin	(8)	1	0	0	1	Exclude file
Bin	(7)	0	1	0	1	Exclude file
Bin	(7)	1	0	0	1	Exclude file
Bin	(6)	0	1	0	1	Exclude file
Bin	(6)	1	0	0	1	Exclude file
Bin	(5)	0	1	0	1	Exclude file
Bin	(5)	1	0	0	1	Exclude file
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_PARITY

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_WRITE

	From	To	Count	Threshold	Excluded due to
Bin	0	1	0	1	Exclude file
Bin	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_A_BE

	Element	From	To	Count	Threshold	Excluded due to
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

---

Port:

 TXTB_PORT_B_ADDRESS

	Element	From	To	Count	Threshold	Excluded due to
Bin	(4)	0	1	0	1	Exclude file
Bin	(4)	1	0	0	1	Exclude file
Bin	(3)	0	1	0	1	Exclude file
Bin	(3)	1	0	0	1	Exclude file
Bin	(2)	0	1	0	1	Exclude file
Bin	(2)	1	0	0	1	Exclude file
Bin	(1)	0	1	0	1	Exclude file
Bin	(1)	1	0	0	1	Exclude file
Bin	(0)	0	1	0	1	Exclude file
Bin	(0)	1	0	0	1	Exclude file

Port:

 MR_TST_RDATA_TST_RDATA

	Element	From	To	Count	Threshold
Bin	(31)	0	1	113	1
Bin	(31)	1	0	278	1
Bin	(30)	0	1	109	1
Bin	(30)	1	0	274	1
Bin	(29)	0	1	117	1
Bin	(29)	1	0	282	1
Bin	(28)	0	1	126	1
Bin	(28)	1	0	291	1
Bin	(27)	0	1	120	1
Bin	(27)	1	0	285	1
Bin	(26)	0	1	132	1
Bin	(26)	1	0	297	1
Bin	(25)	0	1	123	1
Bin	(25)	1	0	288	1
Bin	(24)	0	1	115	1
Bin	(24)	1	0	280	1
Bin	(23)	0	1	117	1
Bin	(23)	1	0	282	1
Bin	(22)	0	1	118	1
Bin	(22)	1	0	283	1
Bin	(21)	0	1	122	1
Bin	(21)	1	0	287	1
Bin	(20)	0	1	120	1
Bin	(20)	1	0	285	1
Bin	(19)	0	1	117	1
Bin	(19)	1	0	282	1
Bin	(18)	0	1	124	1
Bin	(18)	1	0	289	1
Bin	(17)	0	1	120	1
Bin	(17)	1	0	285	1
Bin	(16)	0	1	125	1
Bin	(16)	1	0	290	1
Bin	(15)	0	1	127	1
Bin	(15)	1	0	292	1
Bin	(14)	0	1	111	1
Bin	(14)	1	0	276	1
Bin	(13)	0	1	122	1
Bin	(13)	1	0	287	1
Bin	(12)	0	1	118	1
Bin	(12)	1	0	283	1
Bin	(11)	0	1	124	1
Bin	(11)	1	0	289	1
Bin	(10)	0	1	122	1
Bin	(10)	1	0	287	1
Bin	(9)	0	1	125	1
Bin	(9)	1	0	290	1
Bin	(8)	0	1	122	1
Bin	(8)	1	0	287	1
Bin	(7)	0	1	128	1
Bin	(7)	1	0	293	1
Bin	(6)	0	1	125	1
Bin	(6)	1	0	290	1
Bin	(5)	0	1	112	1
Bin	(5)	1	0	277	1
Bin	(4)	0	1	124	1
Bin	(4)	1	0	289	1
Bin	(3)	0	1	119	1
Bin	(3)	1	0	284	1
Bin	(2)	0	1	123	1
Bin	(2)	1	0	288	1
Bin	(1)	0	1	122	1
Bin	(1)	1	0	287	1
Bin	(0)	0	1	120	1
Bin	(0)	1	0	285	1

---

Port:

 TXTB_PORT_B_DATA_OUT

	Element	From	To	Count	Threshold
Bin	(31)	0	1	199	1
Bin	(31)	1	0	354	1
Bin	(30)	0	1	342	1
Bin	(30)	1	0	497	1
Bin	(29)	0	1	196	1
Bin	(29)	1	0	351	1
Bin	(28)	0	1	631	1
Bin	(28)	1	0	783	1
Bin	(27)	0	1	347	1
Bin	(27)	1	0	499	1
Bin	(26)	0	1	680	1
Bin	(26)	1	0	830	1
Bin	(25)	0	1	648	1
Bin	(25)	1	0	798	1
Bin	(24)	0	1	369	1
Bin	(24)	1	0	519	1
Bin	(23)	0	1	575	1
Bin	(23)	1	0	728	1
Bin	(22)	0	1	646	1
Bin	(22)	1	0	797	1
Bin	(21)	0	1	459	1
Bin	(21)	1	0	609	1
Bin	(20)	0	1	433	1
Bin	(20)	1	0	585	1
Bin	(19)	0	1	563	1
Bin	(19)	1	0	712	1
Bin	(18)	0	1	519	1
Bin	(18)	1	0	671	1
Bin	(17)	0	1	484	1
Bin	(17)	1	0	637	1
Bin	(16)	0	1	466	1
Bin	(16)	1	0	621	1
Bin	(15)	0	1	493	1
Bin	(15)	1	0	647	1
Bin	(14)	0	1	435	1
Bin	(14)	1	0	590	1
Bin	(13)	0	1	454	1
Bin	(13)	1	0	609	1
Bin	(12)	0	1	434	1
Bin	(12)	1	0	588	1
Bin	(11)	0	1	379	1
Bin	(11)	1	0	533	1
Bin	(10)	0	1	401	1
Bin	(10)	1	0	554	1
Bin	(9)	0	1	758	1
Bin	(9)	1	0	907	1
Bin	(8)	0	1	383	1
Bin	(8)	1	0	536	1
Bin	(7)	0	1	834	1
Bin	(7)	1	0	977	1
Bin	(6)	0	1	714	1
Bin	(6)	1	0	861	1
Bin	(5)	0	1	497	1
Bin	(5)	1	0	650	1
Bin	(4)	0	1	359	1
Bin	(4)	1	0	513	1
Bin	(3)	0	1	587	1
Bin	(3)	1	0	735	1
Bin	(2)	0	1	682	1
Bin	(2)	1	0	833	1
Bin	(1)	0	1	619	1
Bin	(1)	1	0	767	1
Bin	(0)	0	1	641	1
Bin	(0)	1	0	785	1

---

Port:

 PARITY_MISMATCH

	From	To	Count	Threshold
Bin	0	1	450	1
Bin	1	0	615	1

---

Signal:

 TXTB_PORT_A_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	101611	1
Bin	(4)	1	0	5037891	1
Bin	(3)	0	1	128538	1
Bin	(3)	1	0	5010954	1
Bin	(2)	0	1	109216	1
Bin	(2)	1	0	5030410	1
Bin	(1)	0	1	4897666	1
Bin	(1)	1	0	242246	1
Bin	(0)	0	1	3849464	1
Bin	(0)	1	0	1291033	1

---

Signal:

 TXTB_PORT_A_WRITE_I

	From	To	Count	Threshold
Bin	0	1	11367	1
Bin	1	0	11555	1

---

Signal:

 TXTB_PORT_A_DATA_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	15137	1
Bin	(31)	1	0	321793	1
Bin	(30)	0	1	16463	1
Bin	(30)	1	0	320469	1
Bin	(29)	0	1	15098	1
Bin	(29)	1	0	321840	1
Bin	(28)	0	1	22039	1
Bin	(28)	1	0	314901	1
Bin	(27)	0	1	20799	1
Bin	(27)	1	0	316133	1
Bin	(26)	0	1	19670	1
Bin	(26)	1	0	317264	1
Bin	(25)	0	1	21967	1
Bin	(25)	1	0	314973	1
Bin	(24)	0	1	21248	1
Bin	(24)	1	0	315682	1
Bin	(23)	0	1	20720	1
Bin	(23)	1	0	316212	1
Bin	(22)	0	1	21513	1
Bin	(22)	1	0	315421	1
Bin	(21)	0	1	20881	1
Bin	(21)	1	0	316043	1
Bin	(20)	0	1	20950	1
Bin	(20)	1	0	315980	1
Bin	(19)	0	1	36072	1
Bin	(19)	1	0	300868	1
Bin	(18)	0	1	43844	1
Bin	(18)	1	0	293091	1
Bin	(17)	0	1	41387	1
Bin	(17)	1	0	295553	1
Bin	(16)	0	1	83361	1
Bin	(16)	1	0	253587	1
Bin	(15)	0	1	19008	1
Bin	(15)	1	0	317926	1
Bin	(14)	0	1	20438	1
Bin	(14)	1	0	316492	1
Bin	(13)	0	1	19220	1
Bin	(13)	1	0	317722	1
Bin	(12)	0	1	19283	1
Bin	(12)	1	0	317669	1
Bin	(11)	0	1	41737	1
Bin	(11)	1	0	295197	1
Bin	(10)	0	1	40417	1
Bin	(10)	1	0	296517	1
Bin	(9)	0	1	47249	1
Bin	(9)	1	0	289691	1
Bin	(8)	0	1	50383	1
Bin	(8)	1	0	286559	1
Bin	(7)	0	1	44070	1
Bin	(7)	1	0	292878	1
Bin	(6)	0	1	44732	1
Bin	(6)	1	0	292210	1
Bin	(5)	0	1	45543	1
Bin	(5)	1	0	291385	1
Bin	(4)	0	1	51069	1
Bin	(4)	1	0	285873	1
Bin	(3)	0	1	53192	1
Bin	(3)	1	0	283748	1
Bin	(2)	0	1	57398	1
Bin	(2)	1	0	279547	1
Bin	(1)	0	1	95711	1
Bin	(1)	1	0	241230	1
Bin	(0)	0	1	84226	1
Bin	(0)	1	0	252726	1

---

Signal:

 TXTB_PORT_B_ADDRESS_I

	Element	From	To	Count	Threshold
Bin	(4)	0	1	3351	1
Bin	(4)	1	0	3516	1
Bin	(3)	0	1	113	1
Bin	(3)	1	0	278	1
Bin	(2)	0	1	5325	1
Bin	(2)	1	0	5490	1
Bin	(1)	0	1	3951	1
Bin	(1)	1	0	3951	1
Bin	(0)	0	1	11226	1
Bin	(0)	1	0	11391	1

---

Signal:

 TXTB_PORT_B_DATA_OUT_I

	Element	From	To	Count	Threshold
Bin	(31)	0	1	199	1
Bin	(31)	1	0	354	1
Bin	(30)	0	1	342	1
Bin	(30)	1	0	497	1
Bin	(29)	0	1	196	1
Bin	(29)	1	0	351	1
Bin	(28)	0	1	631	1
Bin	(28)	1	0	783	1
Bin	(27)	0	1	347	1
Bin	(27)	1	0	499	1
Bin	(26)	0	1	680	1
Bin	(26)	1	0	830	1
Bin	(25)	0	1	648	1
Bin	(25)	1	0	798	1
Bin	(24)	0	1	369	1
Bin	(24)	1	0	519	1
Bin	(23)	0	1	575	1
Bin	(23)	1	0	728	1
Bin	(22)	0	1	646	1
Bin	(22)	1	0	797	1
Bin	(21)	0	1	459	1
Bin	(21)	1	0	609	1
Bin	(20)	0	1	433	1
Bin	(20)	1	0	585	1
Bin	(19)	0	1	563	1
Bin	(19)	1	0	712	1
Bin	(18)	0	1	519	1
Bin	(18)	1	0	671	1
Bin	(17)	0	1	484	1
Bin	(17)	1	0	637	1
Bin	(16)	0	1	466	1
Bin	(16)	1	0	621	1
Bin	(15)	0	1	493	1
Bin	(15)	1	0	647	1
Bin	(14)	0	1	435	1
Bin	(14)	1	0	590	1
Bin	(13)	0	1	454	1
Bin	(13)	1	0	609	1
Bin	(12)	0	1	434	1
Bin	(12)	1	0	588	1
Bin	(11)	0	1	379	1
Bin	(11)	1	0	533	1
Bin	(10)	0	1	401	1
Bin	(10)	1	0	554	1
Bin	(9)	0	1	758	1
Bin	(9)	1	0	907	1
Bin	(8)	0	1	383	1
Bin	(8)	1	0	536	1
Bin	(7)	0	1	834	1
Bin	(7)	1	0	977	1
Bin	(6)	0	1	714	1
Bin	(6)	1	0	861	1
Bin	(5)	0	1	497	1
Bin	(5)	1	0	650	1
Bin	(4)	0	1	359	1
Bin	(4)	1	0	513	1
Bin	(3)	0	1	587	1
Bin	(3)	1	0	735	1
Bin	(2)	0	1	682	1
Bin	(2)	1	0	833	1
Bin	(1)	0	1	619	1
Bin	(1)	1	0	767	1
Bin	(0)	0	1	641	1
Bin	(0)	1	0	785	1

---

Signal:

 TST_ENA

	From	To	Count	Threshold
Bin	0	1	64	1
Bin	1	0	229	1

---

Signal:

 PARITY_WORD

	Element	From	To	Count	Threshold
Bin	(20)	0	1	23	1
Bin	(20)	1	0	637	1
Bin	(19)	0	1	1	1
Bin	(19)	1	0	659	1
Bin	(18)	0	1	2	1
Bin	(18)	1	0	658	1
Bin	(17)	0	1	3	1
Bin	(17)	1	0	657	1
Bin	(16)	0	1	4	1
Bin	(16)	1	0	656	1
Bin	(15)	0	1	7	1
Bin	(15)	1	0	653	1
Bin	(14)	0	1	6	1
Bin	(14)	1	0	654	1
Bin	(13)	0	1	10	1
Bin	(13)	1	0	650	1
Bin	(12)	0	1	8	1
Bin	(12)	1	0	652	1
Bin	(11)	0	1	14	1
Bin	(11)	1	0	646	1
Bin	(10)	0	1	17	1
Bin	(10)	1	0	643	1
Bin	(9)	0	1	19	1
Bin	(9)	1	0	641	1
Bin	(8)	0	1	27	1
Bin	(8)	1	0	633	1
Bin	(7)	0	1	27	1
Bin	(7)	1	0	633	1
Bin	(6)	0	1	21	1
Bin	(6)	1	0	639	1
Bin	(5)	0	1	69	1
Bin	(5)	1	0	591	1
Bin	(4)	0	1	148	1
Bin	(4)	1	0	512	1
Bin	(3)	0	1	267	1
Bin	(3)	1	0	393	1
Bin	(2)	0	1	345	1
Bin	(2)	1	0	315	1
Bin	(1)	0	1	197	1
Bin	(1)	1	0	463	1
Bin	(0)	0	1	212	1
Bin	(0)	1	0	448	1

---

Signal:

 PARITY_READ_REAL

	From	To	Count	Threshold
Bin	0	1	985	1
Bin	1	0	841	1

---

Signal:

 PARITY_READ_EXP

	From	To	Count	Threshold
Bin	0	1	744	1
Bin	1	0	909	1

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold	Exclude Command
Bin	False	True	0	1	Copy to Clipboard

"and" expression on lines 277 to 278:

 (mr_tst_control_tmaena = '1') and (mr_tst_dest_tst_mtgt = std_logic_vector(to_unsigned(G_ID + 2, 4))) 
  <-----------LHS----------->       <------------------------------RHS------------------------------>  

	LHS	RHS	Count	Threshold
Bin	True	False	607	1
Bin	True	True	64	1

---

"=" expression on line 277:

 mr_tst_control_tmaena = '1' 

	Evaluated to	Count	Threshold
Bin	False	931	1
Bin	True	671	1

---

"=" expression on line 283:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	5962	1
Bin	True	10335251	1

---

"=" expression on line 287:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	943	1
Bin	True	94950	1

---

"=" expression on line 291:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	3318	1
Bin	True	678752	1

---

"=" expression on line 296:

 tst_ena = '0' 

	Evaluated to	Count	Threshold
Bin	False	1243	1
Bin	True	84542	1

---

"=" expression on line 300:

 tst_ena = '1' 

	Evaluated to	Count	Threshold
Bin	False	3394	1
Bin	True	528	1